Logic Design

Boolean Functions
3 lectures
Boolean Functions Minimization. Combinational Logic Design
Principles
4 lectures
Brief Description of Verilog
3 lectures
Basic Combinational Circuits
4 lectures
Finite States Machines (FSM)
3 lectures
Synthesis of Synchronous FSM
5 lectures
Content (1/2)
Basic Sequential Circuits
3 lectures
Problems of Synchronous Design
3 lectures
Asynchronous FSM. Self-Timed Circuits
3 lectures
Arithmetic Units
4 lectures
Programmable Logical Integrated Circuits (PLDs)
3 lectures
Memory Devices
3 lectures
Content (2/2)
2
n
words
2
n
words
m bit per word
n address lines
m data input lines
m data output lines
Memory is a collection of binary cells together with
associative circuits needed to transfer information to or
from any desired location.
Two primary categories of
memory: RAM and ROM
Semiconductor Memory
Read-Write Memory
Two types: SRAM and DRAM
SRAM: memory cell flip-flop
DRAM: memory cell capacity (drain substrate of MOS-
transistor).
The kinds of IC memory organization:
Linear-select (2D), two-dimensional (3D), compromise
(2DM).
RAM
module memory (enable, address, data_in, data_out, we,
read_write);
input enable, read_write;
input [3:0 ] data_in;
input [5:0] address;
output [3:0] data_out;
reg [3:0] mem[0:63]; // 644 memory
always @(data_in or enable)
if (enable)
if (!we) mem[address] = data_in; // write
else data_out = mem[address]; // read
else data_out = 4bz; // high impedance state
endmodule
RAM in Verilog
SRAM generally is used as a cache to hold recently used
instructions and data, to store data in small microprocessor
systems, often in embedded systems.
SRAM cell is RS or D latch.
Select
Input
Write
S
R
Out
S
I
W
O
Static RAM (SRAM)
O
0
S S
I
W
O
S
I
W
O
S
I
W
O I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
S
I
W
O
Write
Read
O
3
O
2
O
1
D
C
D
3
D
2
D
1 D
0
A
0
A
1
Four-
address
memory
with 4 bits
per word
Linear Select SRAM (Internal Structure)
Select 1
Input
Write
S T
R
Out
Select 2
S2
S1
I O
W
Two-dimensional memory cell
Word Line
Bit Line ~Bit Line
SRAM Cell
Data (bit)
CS
Memory
cells matrix
A
2
(n/2bits)
Row
deco-
der
(DC
X
)
Column decoder (DC
Y
)
1
A
1
(n/2bits)
CS
S1
S1
S1
S1
S1
S1
S1
S1
S1
S2
S2
S2 S2
S2
S2 S2
S2
S2
All O outputs from cells
are connected to this point
O
I W
O
I W
O
I W
O
I W
O
I W
O
I W
O
I W
O
I W
O
I W
Input
Two-dimensional IC memory organization
Dout
(m
bits)
A
k
A
n-1
Memory array
2
n-k
m2
k
Data buffers
(column I/O)
Row
deco-
der
m2
k
bits
Din
(m bits)
A
0
. . . A
k-1
Column decoder
WR/RD
CS
Compromise
The structure IC with selectors (2DM)
The linear-select organization is used for IC memory with
small capacity. Address decoder is complicated:
2
n
AND elements (with n inputs).
Address decoder for two-dimensional IC organization is
simpler : 2 2
n/2
AND elements (with n/2 inputs).
Properties of SRAM:
fast
density is not very large six transistors per bit
doesnt need to be refreshed (data stays as long as
power is on).
basically is used for cache memory
SRAM
CS OE W
E
I/O
pins
Mode
1 x x z Not
selected
0 1 1 z Output
disable
0 0 1 Dout Read
0 x 0 Din Write
A
0
A
1
A14
WE
OE
CS
0
1 SRAM 0
. 1
. 2
. 3
14 4
5
W 6
OE 7
CS
.
.
.
SRAM has bidirectional data bus the same data pins are used
for both reading and writing.
Example: SRAM IC Memory
0
1
2

511
CS
WE
OE
Row
Deco-
der
Memory Array
51282
6
bit
Input
data
control
Column I/O
Multiplexers

A
2
A
3
A
4
A
5
A
6
A
8
A
9
A
11
A
13
A
0
A
1
A
7
A
10
A
12
A
14
Din/out 0

Din/out 7

Example: SRAM IC Memory

Read Cycle Write Cycle Write Cycle
(CS Controlled) (WE Controlled)
ADDR
~CS
~OE
~WE
DATA
Dou
t
Din
Din
T
AA
Timing Waveforms
128 KB 512 KB
HM628128
A0
A1
A2
A16
WE
CS1
CS1
OE
IQ0
IQ1
IQ2
IQ3
IQ4
IQ5
IQ6
IQ7
.
.
.
A0
A1
A2
.
A17
A18
WE
CS
OE
IQ0
IQ1
IQ2
IQ3
IQ4
IQ5
IQ6
IQ7
HM628512
.
.
Logic Symbols for SRAMs
Implement a 1M8 SRAM module using 512K8 IC
Data bus
Signal MEM
memory request .
Signal ~WR/RD
specify operation
A0
A18
WE
CS
OE
IQ0
IQ7
.
.
.
.
.
.
IQ1
A0
A18
WE
CS
OE
IQ0
IQ7
.
.
.
.
.
.
IQ1
A0
A18
A0
A18
D0
D1
D7
D7
D1
D0
.
.
.
D1
D0
D7
A0
A1
A18
A19
MEM
~WR
~CS0
~WR
~CS1
~CS0
~WR/RD
~CS1
.
.
.
.
.
.
Address
bus
Control
signals
~WR
~RD
~RD
~RD
Design of SRAM Module (Example 1)
Implement a
512K 16
SRAM module
using 128 K8IC
~WR
0
1
2
3
A0
A1
A16
CS
A0
A1
A16
CS
A0
A1
A16
CS
A0
A1
A16
CS
WE
WE
OE
OE
WE
WE
OE OE
OE
A0
A1
A16
CS
WE
OE
A0
A1
A16
CS
WE
OE
A0
A1
A16
CS
WE
OE
A0
A1
A16
WE
CS
A0
A1
A2
A16
A17
A18
A17
A18
0
1
EN
MEM
~WR/
RD
~MEM
~RD
~WR
A0
A1
A16
A1
A0
A16
A0
A1
A16
A0
A0
A1
A1
A0
A0
A0
A1
A16
A16
A16
A16
CS0
CS0 CS0
CS1
CS1 CS1
CS2
CS2 CS2
CS3
CS3
CS3
~WR
~WR
~WR
~WR ~WR
~WR
~RD ~RD
~RD ~RD
~RD ~RD
~RD
~RD
D0
D0
D1
D7
D7
D1
D0
D1
D7
D0
D1
D7
D8
D8
D8
D8
D9
D9
D9
D9
D15
D15
D15
D15
D0
D1
D15
Example 2
CE
ADDRESS
CS
WE
DIN DOUT
CREG
INREG
OUTREG
Control Logic
ADDR
~ADS
CLK
CS
~QW
DIO
OE
AREG
Synchronous SRAM (1)
AREG, CREG, INREG store address, control signals and data input
by rising edge of the clock.
An operation that is set up before the rising edge of the clock is
performed internally during a subsequent clock period
The result of previous read operation is placed in OUTREG.
The device supports a burst mode (data at a sequence of addresses
is read). AREG serves as a counter.
Bust mode for write (sequence of addresses can be written without
supplying a new address).
SSRAM is used in high-performance systems.
QDR (quad-data-rate) SSRAM transfers data on both edges of the
clock.
ADS Address Set
QW Global Write
Synchronous SRAM (2)
CLK
CS,
ADDR
ADS_L
AREG,
CREG
Readin
g
OUTREG
X Y Z
X Y
Z
X
Y
Y+1
Y+2 Y+3
Z
X
Y
Y+1 Y+2 Y+3
Z
X Y Y+1 Y+2 Y+3
Z
X Y Y+1 Y+2 Y+3 Z
DIO (out)
Timing Waveforms for SSRAM
DRAM memory cell construction
n
+
n
+
C
c
Polysilicon
wordline
Select
SiO
2
Bitline (Data in/out)
wordline
(select)
Cc
R
Cl
Bit stored as a charge in capacitor C
c
to read
Drive the wordline and discharge into the bit line
Sense amplifiers to detect change on the bit line
Read is destructive: write back immediately
Dynamic Random Access Memory
(DRAM)
High density (1 transistor for DRAM vs. 6 (or 4)
transistors for SRAM)
Destructive read (capacitor discharge on a read)
Read is automatically followed by a write (to restore)
Charge leaks away over time (needs to refresh)
DRAM
Column 0 Column 1 Column 2 Column 3
Row 0
The Matrix of Memory Elements
Memory Array
(square matrix)
Column
decoder
Column I/O
Column address
buffer
Din
Dout
A0
.
.
An-1
CAS
RAS
WE
MUX
Address
row buffer
DRAM Chip Organization
Multiplexed address lines
To perform the operation next five cycles are needed:
put row address on lines
set row address strobe (RAS)
read row into row buffer
put column address on line (to switch external
multiplexer)
set column address strobe (CAS)
read column bits out of internal row buffer
write row bits content to row
return RAS and CAS to inactive state
DRAM Chip Organization (Contd.)
0 DRAM
1
.
.
.
10
WE
RAS
CAS
D
in/out
MA
IC capacity:
2
11+11
4 bit =
= 2
22
4 bit =
= 4M 4 bit
IC DRAM usually two-dimensional
Example: IC DRAM
SRAM is faster than DRAM:
1/4 - 1/8 access time of DRAM.
The density SRAM is lower than DRAM 1/4 density of DRAM.
Static: bit is not erased on a read.
SRAM does not need to refresh.
Unlike DRAM, there is no difference between access time and
cycle time.
Access time: time to read
Cycle time: time between reads > access time (DRAM)
Cycle time = access time (SRAM)
SRAM address lines are not multiplexed.
SRAM is more expensive than DRAM: about 8-16 times.
Comparison SRAM with DRAM
Standard DRAM chip - operation: read row into buffer,
read column from buffer. The methods to improve of
standard DRAM chip performance:
Nibble mode: additional bits per access.
Fast page mode: change column address
Static column mode (SCRAM): dont toggle CAS
Cached DRAMs: multiple row buffers.
Further improvement: synchronous DRAM
SDRAM, DDR SDRAM, DDR2 SDRAM
DDR2 has the most potential possibilities to increase
performance
Rambus quite new interface (fast but expensive).
DRAM Optimization
CAS
RAS
MA
WE
Data
Read cycle Write cycle
t
RCD
t
RAC
Z Data Out Data In
t
CAC
t
RAS
t
WCH
t
RP
t
CP
Row
Address
Row
Address
Column
Address
Column
Address
t
RC
t
CAS
Timing Waveforms IC DRAM
trac (access time from RAS)delay of appearance of real data
on the outputs regarding RAS negative edge. For
contemporary ICs 40-100ns.
t
RC
- time of read cycle or write cycle minimum period
between the beginnings of neighboring cycle of accesses
(75 125ns).
t
PC
- period of CAS sequence in page mode.
t
RAS
, t
CAS
minimum duration of low level of RAS and CAS
signals.
t
RP
- ~RAS precharge time
t
CP
- ~CAS precharge time
t
RCD
- ~RAS to ~CAS delay time
t
CAC
(access time from CAS) - Data delay regarding CAS#.
Timing parameters
RAS only refresh (ROR) CAS before RAS (CBR)
RAS
CA
S
MA
t
RF
t
RF
= T
RF
/n 15,6 ns
T
RF
Refresh
Memory
address
Write
Read
AR
Matrix of Memory ICs
WR RAS CAS CS
Controller
Refresh
timer
Refresh
Decoder of high
address bits
A
d
d
r
e
s
s

m
u
l
t
i
p
l
e
x
e
r
D
a
t
a

b
u
f
f
e
r
Mem
Structure of Module of Asynchronous
DRAM
Difference from asynchronous DRAM:
Synchronous method of data transfer on bus
Pipelining
Application of several memory banks
Transfer of part of control functions to IC memory
Partitioning into banks allows combining access to cell of
one bank prepared for the next operation in other banks.
At recurrent access to the banks, the frequency of other
banks accesses reduces
Synchronous DRAM (SDRAM)
Clocked by both edges of synchrosignal (it duplicates
throughput of memory interface)
Clock is carried out as usual in internal blocks of ICs
Synchronization of DDR technology has the following
requirements:
Synchrosignal is generated and transferred in differential
form(simultaneously CLK and ~CLK).
Special signal DQS (DQ Strobe) is inserted for data
synchronization.
DLL blocks are inserted to IC for self-tuning of the delay.
DLL (Delay Locked Loops) corrects clock skew and multiplies
frequency if necessary.
DDR SDRAM (1)
CK,~CK
Addr
Input data register
And converter
Bank0
Bank1
Bank2
Bank2
S
e
n
s
e

a
m
p
l
i
f
i
e
r
s
R
o
w

d
e
c
o
d
e
r
I
/
O

c
o
n
t
r
o
l
W
o
r
d

l
e
n
g
t
h

c
h
a
n
g
i
n
g
O
u
t
p
u
t

b
u
f
f
e
r
DLL
CK ~CK
Strobe
generator
C
o
l
u
m
n

b
u
f
f
e
r
Column decoder
Burst length and
latency
Register of
pogramming
Timing Register
CK ~CK ~CKE ~CS ~RAS ~CAS ~WE DM
DM
WE
DM
R
o
w

b
u
f
f
e
r

a
n
d

r
e
f
r
e
s
h

c
o
u
n
t
e
r
LRAS
LCBR
LCKE
A
d
d
r
e
s
s

r
e
g
i
s
t
e
r
CK,~CK
LCAS
LWE LCBR
Data strobe
1M1 bit IC Memory Structure (Samsung)
IC consists from 4 banks. Each bank has a capacity of 32M
bit with organization 216.
CK and ~CK differential synchrosignal.
Address and control signals are accepted by positive edges
of CK (negative edges of ~CK), data by both edges.
Internal synchrosignal is produced from CK and ~CK.
CKE allows internal clocking
Operations Precharge, Power-Down and Self Refresh are
produced if CKE is down
~CS decoding enable
DM masks input data at writing
Addr (A
11
A
0
) address inputs.
DDR SDRAM (2)
Receiving data under the influence of positive and negative
edges.
Inputs and outputs are carried out by the help of register pairs.
At data input of one of the registers, the register is clocked by
positive edge and the other one by negative edge.
Data output with double rate is carried out by the help of
multiplexer.
DDR Technology
Out
D
CE
CK
CK
CE
D
CLK0
CLK1
CE
DATA
Reset
0
1
DDR Technology
ROM is non-volatile memory
ROM is a combinational circuit with n inputs and m outputs
Types of ROM: mask ROM, programmable ROM, erasable
ROM
2
n
m ROM
A0
A1
A2
A
n-1

Address
inputs
Data
outputs
D0
D1
D
m-1
Read Only Memory (ROM)
Horizontal lines lines of word selection,
Vertical lines lines of bit selection.
m output lines
Decoder
0
1
2
2
n
-1
n address
lines
Internal ROM Structure
Information is recorded with the help of mask in the final stage of
technological process.
As a connecting link diodes or MOS transistors are used.
11010001
10101011
Word line
bit line
+5V
Active
low
word
line (WL)
Active low bit lines (BL)
Mask Programmable ROM
A PROM chip is manufactured with all of its diodes or transistors
connected. The customer may program the ROM using PROM
programmer.
Fuse
A link is vaporized by selecting it using PROM address and data
lines and then applying a high voltage pulse (10-30V) to the
device through a special input pin (for programming).
DC
0
1
2
0
1
2
3
4
5
6
7
OR Matrix
Programmable ROM
Programmed by removing or creating special links.
1 0
0
1
WL
WL
BL BL
BL BL BL
Programmable ROM
BL
WL
WL
GND
BL
BL
WL
VDD
Word Line
Bit Line
1
0
ROM Cells
DC

V
DD


A
0
A
1

A
n-1
~D
0
~D
1
~D
7
Active high
word line
Active
low
bit lines
Application of MOS Transistors as
Memory Cells
Erasing old information and its replacement with the new one is
possible.
Erasing is carried out by ultraviolet rays in EPROM (erasable PROM)
In EEPROM (electrically PROM) by electrical signals.
Floating gate MOS transistors are used as connection links.
G
S
D Floating gate
Source
Substrate
Gate
Drain
n
+
p
Device cross-section
n
+
Polysilicon
SiO
2
Si
Erasable PROM
Active-high
word lines

Active-low bit lines
Storage Matrix in EEPROM
DC
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
Mat
-rix
512
x64
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
6
A
14
A
0
A
5
64-1
MUX
64-1
MUX
64-1
MUX
64-1
MUX
64-1
MUX
64-1
MUX
64-1
MUX
64-1
MUX
0
1
511

Organization of IC size 32Kx8

A0
A1
A2
A3
A4
A5
A6
A7
CS
A0
A1
A2
A3
B0
B1
B2
B3
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
A7A6A5A4A3A2A1A0 Q7Q6Q5Q4Q3Q2Q1Q0
B3B2B1B0A3A2A1A0 P7 P6 P5P4P3P2 P1 P0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

0 0 1 1 0 1 1 1 0 0 0 1 0 1 0 1
0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0
0 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1

1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1
1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 0
1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1
A,B 4-bit integer
unsigned
A= (a3a2a1a0)
B=(b3b2b1b0)
AB = P
Using ROM for Realization of Integer
Multiplication
x1x2x3x4x5x6x7x8 y1y2y3y4y5y6y7y8
0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0
0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0
0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0
0 0 0 0 0 1 0 1 1 0 0 1 0 1 0 1

1 1 1 1 1 1 0 1 1 0 0 1 0 1 1 1
1 1 1 1 1 1 1 0 1 1 0 0 1 0 1 1
1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1
A0
A1
A2
A3
A4
A5
A6
A7
CS
X8
X7
X6
X5
X4
X3
X2
X1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Using ROM for Realization of logic
Functions (LUT)
Flash memory similar to EPROM. Particular qualities:
Data erasing is accomplished by blocks (not separate words).
EPROM
EEPROM
Flash
+
=
2 power supplies
ultra-violet erasing
1-transistor cell
1 power supplies
electrical signals
erasing
2-transistors cell
1 or 2 power
supplies
electrical signals
erasing
1-transistor cell
Flash Memory
X
1
X
2
X
m
R
VDD
F
To form a low level in the output F it is enough the presence
in chain of transistors even if on transistor.
All transistors except of addressable must be closed.
Fast access at random sample.
NOR Flash Memory
To form in the output of a high level it
is enough the presence in chain of
transistors even if off transistor.
All transistors except of addressable
must be open.
Compact structure, but random mode
is not provided.
X
m
X
1
X
2
V
DD
F

NAND Flash Memory

Bit lines
Bit selection lines
Word
lines
Structure of Matrix Based on NOR Gates