ECE480/580 Digital Systems Design

Lab 3: Arithmetic Circuits and Arbitrary Finite State Machines

1. INTRODUCTION

In this lab, you will use the QUARTUS II software package to design and simulate several designs. The
requirements for this lab consist of completing QUARTUS II designs and printing the VHDL files, timing
simulation results and laboratory report.

All simulations should be done using the ModelSim-Altera Simulator. You may use VHDL testbenches or
ModelSim DO files to control the simulation. All simulations must be timing-based simulations (i.e. no
functional simulations).

2. DESIGN

Implement the following circuits using VHDL. Devise a set of test vectors to verify each circuit in simulation.

DESIGN 1: 8-bit Arithmeti c-Logic Unit (ALU)

Implement the equivalent of the circuit given below using behavioral VHDL. A single VHDL file (alu.vhd)
describing the design is to be used. Devise a set of test vectors to verify the correct operation of the circuit.




Figure 1. Simple 8-bit ALU.


ALU operations to be implemented are: ADD (A+B), SUB (A-B), AND, OR, SHR (shift right), SHRA (shift
right arithmetic), SHL (shift left), NOT, C=B, and INC (increment). Assume all single source instructions (i.e.
all shift operations, NOT, C=B and INC) operate on the B input to the ALU.

For the shift operations, assume the ALU is capable of only single-bit shifts. A 4-bit control signal will be
sufficient to specify all the ALU operations.

Table 1 summarizes the operations for given control signal values.

ALU Control Signal Operation
0000 A+B
0001 A-B
0010 A AND B
0011 A OR B
0100 SHR B
0101 SHRA B
0110 SHL B
0111 NOT B
1000 C=B
1001 INC B

Table 1. ALU Control Signals and Corresponding Operations.

In testing all of the operations requiring two operands, you are to (in the simulation) place a value onto the
8-bit bus, clock that value into the A register by asserting the Aen signal and then clocking the register.
Then place a second value on the bus (which will represent the B input). Finally, after an appropriate delay
the result is to be gated into the 8-bit C register by asserting the Cen signal and then clocking the register.
Verify the value held in the C register is output onto ALUout.

For testing the design on the Altera DE2-115 board, SW[7]-SW[0] should be used as the ALU input, the
KEY[0] pushbutton should be used as the clock signal, the KEY[1] pushbutton should be used as Aen, the
KEY[2] pushbutton should be used as Cen, and SW[17]-SW[14] should be used as the 4-bit ALU control
signal.

View the compilation report files (*.rpt) that are generated when you compile your design for the Cyclone
IV EP4CE115F29C7 device.

The Fitter Report Fil e (*.fit.rpt) summarizes the logic element (LE), memory block, and interconnect usage
for your design. In your lab report, summarize LE, memory, and interconnect usage for your design. This
information can also be found in the Compil ation Report using Processing->Compilation Report-
>Fitter->Summary.

Include RTL Viewer (Tools->NetList Viewers->RTL Viewer) and Technology Map Viewer (Tools-
> NetList Viewers->Technology Map Viewer) schematics in your lab report.

A ModelSim simulation should show all operations the ALU is capable of performing. You must use either
a VHDL testbench or ModelSim DO file for controlling your simulation. The testbench or DO file must be
included in your lab report.

DESIGN 2: Vending Machine as an Arbitrary Finite State Machine

Design a digital circuit as an arbitrary finite state machine (FSM) using behavioral VHDL that implements a
simple vending machine. Assume a product is to cost 50 cents and the machine is to accept nickels, dimes
and quarters. Assume three binary inputs reflect the three currency inputs: N=1 implies a nickel input, D=1
implies a dime input, and Q=1 implies a quarter input. When 50 cents or more have been input, a product
is to be output by energizing an output (P) for one clock cycle.

Begin your design by drawing a finite state diagram for the design. This must be turned in with your design.

In your lab report, summarize LE, memory, and interconnect usage for your design. Include RTL Viewer
(Tools->NetList Viewers->RTL Viewer) and Technology Map Viewer (Tools-> NetList
Viewers->Technology Map Viewer) schematics in your lab report. Include the output from the State
Machine Viewer (Tools->NetList Viewers->State Machine Viewer) in your report as well.

For testing the design on the Altera DE2-115 board, KEY[0] should be used as the clock signal, KEY[1]
should be used as the nickel input, KEY[2] should be used as the dime input, and KEY[3] should be used
as the quarter input. Assume only one of the three coin inputs will be pressed when the clock is asserted.
LEDG[0] should be used as the output.

A ModelSim simulation should show operation of the vending machine. You must use either a VHDL
testbench or ModelSim DO file for controlling your simulation. The testbench or DO file must be included in
your lab report.

BONUS FOR DESIGN 2: Keep track of the total amount of money entered using the seven segment
displays in the DE2-115 board. No help will be given for this portion of the design.

DESIGN 3 (ECE580 onl y): Expanded Vending Machine

Expand the design from the previous vending machine to allow selection of one of 4 products for output
from the vending machine. A product should only be selected after 50 cents or more are entered into the
machine. On the Altera development board use SW[3]-SW[0] as product selection indicators. Use
LEDG[3]-LEDG[0] as four outputs from the design (one for each potential product selected).

In your lab report, summarize LE, memory, and interconnect usage for your design. Include RTL Viewer
(Tools->NetList Viewers->RTL Viewer) and Technology Map Viewer (Tools-> NetList
Viewers->Technology Map Viewer) schematics in your lab report. Include the output from the State
Machine Viewer (Tools->NetList Viewers->State Machine Viewer) in your report as well.

A ModelSim simulation should show operation of the vending machine. You must use either a VHDL
testbench or ModelSim DO file for controlling your simulation. The testbench or DO file must be included in
your lab report.