Analog Integrated Circuits and Signal Processing, 21, 213228 (1999)

# 1999 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.

Fully-Depleted SOI CMOS Technology for Low-Voltage Low-Power
Mixed Digital/Analog/Microwave Circuits
D. FLANDRE, J. P. COLINGE, J. CHEN, D. DE CEUSTER, J. P. EGGERMONT, L. FERREIRA,
B. GENTINNE, P. G. A. JESPERS AND A. VIVIANI
Microelectronics Laboratory, Universite Catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium
E-mail: andre@dice.ucl.ac.be
R. GILLON, J. P. RASKIN, A. VANDER VORSTAND D. VANHOENACKER-JANVIER
Microwaves Laboratory, Universite Catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium
F. SILVEIRA
Instituto de Ingeniera Electrica, Universidad de la Republica Casilla de Correos 30, Montevideo, Uruguay
Received December 7, 1995; Revised September 3, 1996; Accepted December 12, 1996
Abstract. This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique
opportunities in the eld of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic
capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold
slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit
studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low
supply voltage of analog, digital and microwave components with properties signicantly superior to those
obtained on bulk CMOS. Experimental circuit realizations support the analysis.
Key Words: SOI Technology, CMOS circuits, LVLP mixed-mode, RF components
1. Introduction
Thin-lm Silicon-on-Insulator (SOI) technology has
evolved from a mere laboratory curiosity in the early
1980s to a technology in which large circuits such as
16 Mbit DRAMs can be made [1]. SOI CMOS is also
considered as a very attractive technology for the
realization of low-voltage low-power (LVLP) digital
ULSI circuits for a number of well-known advantages
over conventional bulk Si CMOS [2,3]:
dielectric isolation provides reduced parasitic
capacitances and leakage currents when compared
to junction isolation;
full-depletion (FD) operation of thin-lm SOI
MOSFETs yields quasi-ideal device properties
such as sharper subthreshold slope, lower body
effect and smaller vertical eld mobility degrada-
tion. Improved subthreshold slopes in turn allow for
the use of lower threshold voltages for identical
subthreshold leakage current values. These char-
acteristics all add up to signicantly increase the
drive capability, in particular for reduced supply
voltages;
thinned lms and dielectic isolation result in
simplied submicron CMOS processes: threshold
voltage roll-off is minimized, reliable ultra-shallow
junctions are easily obtained, wells and latch-up are
suppressed and complicated lateral isolation pro-
cess can be avoided. SOI process yield may
actually be higher than that of bulk since SOI
devices and circuits are much more tolerant to
defects.
The impact of the improved FD SOI CMOS
characteristics on speed and power consumption has
already received a lot of attention in digital circuitry.
Circuits built on a 0.5 mm FD SOI CMOS 1 M gate
array showed twice the speed or half the power
consumption of similar bulk CMOS circuits when
operated at 2 V supply voltage [4]. It can be evaluated
that around 40% of the improvement results from the
capacitance reduction and the other 60% from the
drive current increase. Athreefold enhancement of the
power times speed gure of merit has been
demonstrated for 1 V supply voltage, in particular in
the case of a 512 K SRAM [5]. Frequency dividers
operating at 1 GHz with a 1 V supply voltage have
also been realized in a 0.12 mm SOI CMOS process,
consuming only 50 mW [6].
The challenges for LVLP analog and microwave
SOI CMOS circuits, however, have not been as
widely investigated so far. Preliminary theoretical
results nevertheless show that analog circuits, in
particular op-amps, will benet from the lower body
effect and load capacitances in FD SOI CMOS [710].
On the other hand, preliminary experimental results
also show that submicron FD SOI MOSFETs may
achieve transition frequencies in excess of 20 GHz for
supply voltages on the order of 3 V [11]. Combined
with the ability to realize low-loss matching or
interconnection lines on high-resistivity SOI sub-
strates [12] and the drastic reduction of substrate
crosstalk gures [13], these properties may lead to the
future development of single-chip mixed digital/
analog/microwave solutions.
In the present paper, the properties which make FD
SOI CMOS process and devices attractive for LVLP
applications will be briey recalled. Then the LVLP
performances of digital and analog building blocks
will be analyzed and compared to bulk. Finally, the
microwave properties of SOI MOSFETs operated at
low voltage will be described.
2. Fully-Depleted SOI CMOS Process and
Devices
a. Fabrication Process
The devices which will be described next are
fabricated using a standard fully-depleted SOI
CMOS process with N

polysilicon gate. P-type

SIMOX substrates having a resistivity of 20 or
500 O cm (the latter being used for microwave
transistors) are used as starting material. The initial
200 nm-silicon lm thickness is reduced to 100 nm by
oxidation and oxide strip. The buried oxide thickness
is 380 nm. Semi-recessed LOCOS is used to isolate the
devices, which implies the deposition and patterning
of a 200 nm silicon nitride layer, etching half the
thickness, implanting boron around the edges of the n-
channel devices to suppress edge leakage currents and
growing a eld oxide to consume the remaining
silicon in the eld area. A 30 nm-thick gate oxide is
grown and boron is implanted to adjust the threshold
voltages, which for zero back gate-to-source bias, lie
around 400 mV for the n-channel inversion-mode
devices and 700 mV for the p-channel accumula-
tion-mode devices. When the devices are in operation,
the threshold voltage of the p-channel devices
increases through a back-gate bias effect, and the
threshold voltages of both n- and p-channel devices
become symmetrical ( +400 mV for 3 V supply
voltage and back substrate contact commun to all
devices xed at 0 V) [3]. Polysilicon is then deposited
and N-type doped using a solid phosphorous source.
After gate patterning, arsenic is implanted to form the
sources and drains, and 150 nm-thick spacers are
formed through oxide deposition and reactive ion
etching. A 30 nm-thick layer of titanium is then
deposited and 2-step annealed in a rapid thermal
annealing furnace to form TiSi
2
on the gates, sources
and drains. This silicidation process allows for a sheet
resistance reduction from 35 to 6.2 O/square for the
gate material and from 300 to 6.3 O/square for the
sources and drains. A nitride/oxide layer is deposited
and contact holes are opened to access the devices.
Aluminum/silicon is then sputtered, patterned, sin-
tered and capped with a passivation oxide to complete
the process. The nal silicon lm thickness is
80 nm+5 nm. The lm thickness nonuniformity
does not impair however the realization and control
of low threshold voltage values. The threshold voltage
sensitivity to lm thickness, usually stated as an
important problem for FD SOI MOSFETs, can indeed
be minimized holding the lm total dose constant
rather than the doping concentration [14]. Threshold
voltage standard deviations similar to bulk devices
have been achieved for FD SOI MOSFETs.
In Fig. 1 a cross section of the devices is presented,
and Fig. 2 shows the symmetrical current-gate voltage
characteristics of the devices with reduced threshold
voltage and low leakage current.
b. Properties of Fully-Depleted SOI MOSFETs
One interesting feature of FD SOI MOSFETs is the
low value of the body-effect coefcient, which
inuences both the current drive of the device and
its subthreshold swing. The body-effect coefcient,
214 D. Flandre et al.
noted n, is an image of the ideality of the coupling
between gate voltage and surface potential. It is well
known that FD SOI devices offer near-ideal coupling,
which yields a value of n close to unity.
The inuence of the body-effect coefcient on the
current drive of the device can best be understood by
using a simple device model. The saturation drain
current of a MOSFET is given by the following
expression:
I
Dsat

1
2n
mC
ox
W
L
V
GS
V
TH

2
1
m being the effective mobility, C
ox
the gate oxide
capacitance per unit area, V
GS
the gate-to-source bias,
V
TH
the threshold voltage and W and L the width and
length of the device respectively.
In a bulk transistor, n is given by
n 1
e
si
C
ox
X
d max
%1:4 to 1:6; typically 2
where X
d max
is the maximum depletion width in
strong inversion.
In a SOI FD MOS transistor, on the other hand, the
body effect is given by
n 1
e
si
t
si
C
oxb
C
ox
e
si
t
si
C
oxb
h i %1:05 to 1:1 typically 3
where C
ox
, C
oxb
and t
si
are the gate oxide capacitance,
the buried oxide capacitance and the silicon lm
thickness, respectively. From the above equations, it
follows that the saturation drain current may be 30
40% higher in a FD SOI device than in a bulk device
with similar parameters [3].
A more accurate model for submicron devices
would include velocity saturation and series resistance
effects [15]. These tend to somewhat degrade the
superior current drive capability of FD SOI
MOSFETs as short channel lengths are considered.
It has been shown however that non-optimally
designed FD SOI transistors still present a 25%
current drive improvement over comparable bulk
devices for gate lengths down to 0.2 mm which could
be restored to superior values after correct device
structure optimization [16].
The subthreshold swing (inverse subthreshold
slope) of a MOSFET is also affected by the body
effect. Indeed, the subthreshold swing is given by the
following expression [3]:
S(mV/dec) n
kT
q
ln10 4
if the inuence of the interface traps is neglected. The
low value of n in FD SOI devices yields an
improvement of the subthreshold slope over bulk
devices. Almost ideal subthreshold swings of 60 mV/
dec at room temperature corresponding to the
predicted n values have been experimentally demon-
strated for optimally designed FD SOI MOSFETs
with channel lengthes down to 0.2 mm [17]. As a
result, a lower threshold voltage can be used in SOI
devices without jeopardizing the OFF leakage current,
Fig. 2. Experimental drain current vs. gate voltage characteristics
of n- and p-channel SOI MOSFETs with symmetrical low threshold
voltages (W=L 3 mm=3 mm, V
DS
100 mV, V
THn
0:4 V,
V
THp
0:45 V).
Fig. 1. Cross section of an n ( p)-channel thin-lm SOI MOS
transistor.
Fully-Depleted SOI CMOS Technology 215
and ON drive current much higher than in bulk
devices can be obtained, in particular for reduced
supply voltage.
As far as analog micropower circuits are con-
cerned, it is known that the maximum performance
may be obtained when the value of the transconduc-
tance/drain current ratio g
m
=I
D
is the largest. This
condition appears in the weak inversion regime for
MOS transistors [18]. The value of g
m
=I
D
can be
rewritten as:
g
m
I
D

dI
D
I
D
dV
G

ln10
S

q
nkT
5
The low body-effect coefcient of SOI devices thus
allows for obtaining near-optimal micropower designs
(g
m
=I
D
values of 35 V
1
are obtained, while g
m
=I
D
reaches only values of 25 V
1
in bulk MOSFETs).
[9,10,19]
In strong inversion, the g
m
=I
D
becomes (for long-
channel devices):
g
m
I
D

2 ? m ? C
ox
? W=L
n ? I
D
s
6
and will still remain higher in FD SOI than in bulk
MOSFETs with similar technological characteristics.
Experimental SOI and bulk n-MOSFET g
m
=I
D
characteristics are compared in Fig. 3.
c. Modeling
Several analytical modeling alternatives exist for the
electrical simulation of FD SOI CMOS circuits. The
best known SOI SPICE model [20] was originally
developed for 5 V-digital application. It has recently
been proved efcient for the reliable simulation of
LVLP digital circuits down to a 1 V-supply voltage
[21]. However, as it is a strong inversion-based model,
it is inadequate for reliable analog design. It indeed
suffers from the troubles common to this family of
models such as unproper modeling of moderate
inversion current, discontinuous transition from
triode to saturation, discontinuities of the current
and charge derivatives (i.e. the small-signal con-
ductance and capacitance parameters) between the
different regions of operation, unphysical overshoot
of the transconductance/drain current ratio in mod-
erate inversion, etc. . . [22]. On the contrary, efcient
analog design, and especially for LVLP applications,
requires a model valid from weak to strong inversion
and non-saturation to saturation conditions with
smooth continuous transitions. The EKV model
recently developed for bulk MOSFETs provides
such properties [23]. It has been proved that it can
successfully be extended to FD SOI MOSFETs
[10,24]. In particular the good agreement between
measured and modeled g
m
=I
D
characteristics is
demonstrated in Fig. 3 for both bulk and SOI devices.
The EKV model will be used throughout the rest of
this paper.
3. LVLP Digital Circuits
A simple analysis can be used to demonstrate the
potential of FD SOI technology for LPLV CMOS
applications. Simulation will be performed next with
the EKV model. Using this model, the characteristics
of transistors and simple circuit elements can readily
be modeled. Fig. 4 presents the I
D
V
G
characteristics
of bulk and fully depleted SOI n-channel MOSFETs
plotted using the EKV model. The varying parameter
between the different curves is the (uniform) dopant
concentration in the channel region, ranging from
10
16
to 1.2 10
17
cm
3
. The gate oxide thickness is
15 nm and the channel length is 1 mm. It can be seen
that, for any given threshold voltage, the SOI device
presents a lower OFF (at V
G
0 V) current and a
higher ON current (at V
G
1 V) that a bulk device
Fig. 3. Experimental (symbols) and modeled (lines) Transcon-
ductance over drain current ratios vs. Normalized drain current in
saturation: (a) Bulk (6) and SOI (s) measurements, (b) EKV
model with n 1:1 (- - -) or 1.5 ().
216 D. Flandre et al.
does. The I
ON
=I
OFF
ratio in bulk and SOI saturated
MOSFETs is presented in Fig. 5 as a function of
threshold voltage. Again, it can be seen that the SOI
transistor presents better switching characteristics
than the bulk device, regardless of the value of the
threshold voltage. The I
ON
=I
OFF
ratio advantage of the
SOI device becomes smaller as the threshold voltage
is reduced, but it still is ten times larger than in the
bulk transistor for a threshold voltage of 250 mV.
In order to estimate the ``ultimate'' theoretical
reduction of supply voltage and power consumption
the EKV model has been used to calculate the power
needed to discharge a constant load capacitor by a
MOSFET in a realistic circuit environment. A
constant discharge time constant of 100 psec has
been chosen, which is consistent with a typical value
of 250 MHz for the clock frequency. The load
capacitor of the transistor being a combination of
the next gate input capacitance (which is almost the
same in SOI and in bulk) and of drain/source
diffusion, polysilicon and metal line capacitances,
the value of the load capacitance was chosen to be
25% higher in bulk than in SOI. This value is quite
conservative, since the improvement of speed
performance of SOI over bulk observed in the
literature is in the 30 to 100% range, which tends to
indicate capacitance reduction much over 25% [25].
Similarly, a previous study indicates that compared to
bulk, a reduction of total node capacitances by a factor
of 2 is statistically observed in SOI, when the layout is
optimized taking full advantage of the absence of
wells and substrate/well bias contacts to bring n- and
p-MOSFETs closer and minimize the interconnection
length and number [26].
The average power dissipated by the device is
given by the sum of the static and dynamic power
dissipations
P
total
P
stat
P
dyn
I
OFF
V
DD
a f C
L
V
2
DD
7
where V
DD
is the supply voltage, f the input signal
frequency, C
L
the load capacitance and a the degree of
activity of the gate. An activity of 1% is assumed here,
and both SOI and bulk devices operate at the same
clock frequency. The algorithm used for calculating
the power consumption is the following. In a rst step,
the current I
ON
required to discharge the load
capacitor with a time constant of 100 psec is
estimated. This current is obtained for a gate voltage,
V
G
, equal to V
DD
. Knowing the magnitude of I
ON
and
the value of V
G
at which I
ON
is obtained, one curve
from Fig. 4 can be identied as being the one which
will discharge the load capacitor with the required
time constant. This curve being selected, I
OFF
and the
threshold voltage (Fig. 6) can be extracted. Finally the
static and dynamic power consumption can readily be
obtained from equation (7).
The results of this computation are presented on
Fig. 7. The dynamic power consumption increases
naturally as the square of the supply voltage. The
static power consumption is given by the I
OFF
? V
DD
product. As the supply voltage is reduced, the
threshold voltage decreases (Fig. 6) and, hence, I
OFF
increases. As a result, the static power consumption
increases when the supply voltage is reduced, until it
Fig. 4. Semilog plot of drain current vs. gate voltage in bulk and
SOI MOSFETs for ten values of channel doping concentration
(10
16
to 10
17
cm
3
for the bulk device and 3610
16
to
1:2610
17
cm
3
for the SOI device). The gate oxide thickness is
15 nm.V
DS
100 mV=m
n
500 cm
2
=V ? s, W=L 1 mm=0:6 mm.
Fig. 5. I
ON
V
G
1V=I
OFF
V
G
0 V ratio in bulk and SOI
MOSFETs as a function of threshold voltage. V
DS
1 V.
Fully-Depleted SOI CMOS Technology 217
reaches a maximum before dropping to zero as the
supply voltage tends to zero volt. The following
additional observations can be made. Firstly, the
dynamic power consumption of the SOI device is 25%
lower than that of the bulk transistor, which is quite
logical considering our previous assumption on the
load capacitance values. Secondly, the static power
consumption is lower in SOI than in bulk, which
results from the better I
ON
=I
OFF
ratio of SOI devices.
Finally, the point of minimum power dissipation
occurs for a lower supply voltage in SOI than in bulk,
at which point the consumption is twice as small in
SOI than in bulk, eventhough the load capacitance
was chosen to be only 25% lower in SOI than in bulk.
These results depend of course on the values chosen
for the clock frequency and the gate activity factor.
For higher values of these parameters, the dynamic
power consumption will completely dominate the
overall consumption, but, in any case, the consump-
tion of the SOI device remains lower than that of the
bulk device.
This brief analysis of gate switching enlights the
benets which low-voltage low-power CMOS digital
circuits can draw from the low body-effect coefcient
of FD SOI MOSFETs and reduced load capacitance in
SOI CMOS designs. Based on this analysis one may
furthermore extrapolate that threshold voltages of
about 0.3 V may be compatible with the realization of
high-speed low-power FD SOI CMOS digital circuits
operated at supply voltages reduced down to 11.2 V.
4. LVLP Analog Building Blocks
a. The CMOS Analog Switch
The CMOS analog switch combining parallel nMOS
and pMOS transistors with complementary inverted
gate signals is a key block of sampled-data analog
circuits. A well- known problem of this structure is
that the switch on-resistance increases when the
supply voltage is lowered. It may even peak to very
high values for mid-range input signals when V
DD
is
decreased below a value which can be estimated by
2:V
TH
=2 n, assuming identical threshold voltage
and body effect parameters for n- and p-MOSFETs
[27]. FD SOI CMOS featuring reduced values for
these parameters clearly allows for correct switch
operation at much lower voltages than in bulk [8,10].
We have rened the analysis using the EKV model,
with similar bulk and SOI parameter sets as above and
minimal switch dimensions (i.e. W=Ln 1,
W=Lp 2:5), in order to compute as a function of
V
DD
, rst the maximum permissible threshold voltage
which keeps the on-resistance below 50 kO (Fig. 8),
then the resulting switch off-current (Fig. 9). A 50 kO
maximum on-resistance is a typical value corre-
sponding to a maximum settling error of 0.01% for a
500 kHz clock frequency and a 2 pF capacitance. We
observe that the required bulk threshold voltages
become extremely low for reduced V
DD
. The
corresponding bulk off-current then exceeds the
Fig. 6. N-channel threshold voltage as a function of supply
voltage for given capacitance discharge time.
Fig. 7. Power consumption of a bulk or SOI CMOS gate as a
function of supply voltage.
218 D. Flandre et al.
maximum admissible current which limits to 0.01%
the relative error due to the discharge of the
capacitance during the holding phase. Therefore we
believe that low threshold bulk CMOS processes do
not represent a viable solution for sampled-data
analog circuits. Double threshold processes are
required with charge-pump circuits to boost the
switch gate signal above the supply voltage. On the
contrary FD SOI CMOS technology offers the
simplest solution to the problem of the low-voltage
CMOS switch, when using a threshold voltage of
0.33 V compatible with both maximum on-resistance
and off-current switch typical specications for a
supply voltage of 1.2 V.
b. Operational Transconductance Ampliers
(OTA)
The better g
m
=I
D
of FD SOI MOSFETs may be
directly used to increase the performance of CMOS
OTAs as illustrated by the analysis of the intrinsic gain
stage consisting of a common source MOS transistor
loaded by an ideal current source I
D0
and a
capacitance C
L
. The DCopen-loop gain and transition
frequency are indeed given by
A
vo

g
m
I
D0
? V
A
8
and
f
T

g
m
I
D0
?
I
D0
2 ? p ? C
L
9
where g
m
is the active device small-signal transcon-
ductance and V
A
the Early voltage parameter
corresponding to a small-signal output conductance
g
d
in saturation equal to I
D0
=V
A
.
Larger g
m
=I
D
ratios increase the DC open-loop
gain and can be exploited to either enhance f
T
for
constant DC current dissipation or reduce power for
constant f
T
[9,10].
In the case of practical 2-stage OTAs, the DCopen-
loop gain will be further enhanced since it results from
the product of the g
m
=I
D
ratios of all stages.
Considering closed-loop stability specications (i.e.
the phase margin at the transition frequency), these
will be eased in SOI technology because the reduction
of parasitic node capacitances helps repelling the non-
dominant OTA internal poles to higher frequencies.
FD SOI CMOS single-stage OTAs and two-stage
Fig. 8. Maximum admissible symmetrical threshold voltage of
the n- and p-channel devices of a minimal-dimension CMOS
switch for a maximum on-resistance of 50 kO as a function of the
supply voltage. The computation was performed using the EKV
model with n 1:1 in the SOI case, n 1:5 in the bulk case and
m
n
? C
ox
50 mA/V
2
and m
p
? C
ox
20 mA/V
2
in both cases.
Fig. 9. Bulk and SOI CMOS switch off-currents resulting from
the threshold voltages of Fig. 8 as a function of the supply
voltage. The computations were based on the EKV model using
the same parameters as in Fig. 8. Also represented is the limit
corresponding to a relative error of 10
4
due to the discharge of a
2 pF-capacitance during a 1 ms-holding phase.
Fully-Depleted SOI CMOS Technology 219
Miller OTAs have previously been demonstrated to
signicantly outperform bulk CMOS counterparts for
supply voltages above 3 V [810].
A yet unstudied characteristic of FD SOI CMOS
OTAs concerns the noise performance, of particular
interest in low-voltage op-amp implementations in
order to retain adequate signal-to-noise ratios. In this
preliminary study, we will focus on the thermal noise
analysis. The input-referred thermal noise power
spectral density of a differential pair is given by:
S
V
2 ?
g ? n ? kT
g
m
10
where g is a factor ranging from 2 in weak inversion to
8/3 in strong inversion [23]. It is then clear that for a
constant f
T
? C
L
and hence g
m
specication, S
V
will be lower in SOI than in bulk due to the reduction
of the n body factor and the possible use of devices in
weaker inversion.
The input-referred power spectral density added by
a current mirror is:
S
V;mirror
2 ?
g
m;mirror
g
m

2
?
g ? n ? kT
g
m;mirror
2 ?
g ? n ? kT
g
m
2
?
g
m;mirror
I
D0
? I
D0
11
This equation shows that for constant f
T
and g
m
, we
can either use the same g
m
=I
D

mirror
in bulk and SOI
and obtain lesser added noise in SOI due to the
reduction of n and I
D0
, or achieve similar noise
performance in bulk and SOI using higher
g
m
=I
D

mirror
in SOI which will improve the input
range and output swing. In this case, the possible
increase of g
m
=I
D

mirror
in SOI can be larger than a
factor of 2 when compared to bulk as will be discussed
later.
To demonstrate the feasibility and the performance
of low-voltage FD SOI CMOS OTAs, the design of the
typical 1-stage OTA of Fig. 10 using high g
m
=I
D
ratios
for all the transistors was rst investigated. The OTA
design parameters and experimental characteristics
under a 1.2 V-supply voltage and 3 mA-total current
bias are given in Table 1. They are also compared to
the estimated characteristics of a bulk CMOS
implementation with as similar as possible f
T
and
phase margin performance. Due to the increase of the
body factor and parasitic capacitances, this can only
be achieved at the expense of an increase of the
current bias and a decrease of the DC open-loop gain
and output swing, since the g
m
=I
D
ratios and transistor
widths have to be reduced. For the same reasons we
estimate that the input range will be lower in bulk than
in SOI by an amount similar to the output swing
reduction if the threshold voltages are identical. The
output swing can be further reduced by the V
TH
-
difference if larger threshold voltages are used in bulk
for the leakage current considerations.
The second implementation presented here is that
of the cascoded OTA of Fig. 11. The highest possible
g
m
=I
D
values were used for the active transistors, i.e.
input differential pair g
m
=I
D
28 and output
cascode g
m
=I
D
30 devices, in order to optimize
the performance for minimal supply current con-
Fig. 10. 1-stage CMOS OTA architecture.
Fig. 11. Cascoded CMOS OTA architecture.
220 D. Flandre et al.
sumption. These upper values are limited by stability
considerations because as we increase g
m
=I
D
for a
xed current, the transistor sizes and capacitances are
increased and the phase margin hence decreased. The
bias current and mirror transistors are operated in
stronger inversion g
m
=I
D
8.
This OTA experimentally achieved a 103 dB-DC
open-loop gain and a 271 kHz-transition frequency
over a 12.3 pF-load capacitance with a 60

-phase
margin and a total bias current of only 2 mA under a
3 V-supply voltage, in accordance with the targeted
and simulated specications. The output swing was
almost equal to 2 V. We estimated that to achieve a
similar f
T
performance with same C
L
and phase
margin, the bulk implementation could have only used
g
m
=I
D
ratios of 19 and 17 for the input differential pair
and output cascode devices respectively and would
then have dissipated 45% more supply current for a
DC open-loop gain reduced by 8 dB. Furthermore, we
simulated that for higher transition frequencies, the
FD SOI benets over bulk increase up to a reduction
of the supply current by a factor larger than 3.5 and an
improvement of the gain by more than 20 dB for f
T
equal to 10 MHz (Fig. 12), even though the active
device g
m
=I
D
values have to be reduced towards
strong inversion (13 and 3.5 in SOI and bulk
respectively at 10 MHz). Similar results were partly
demonstrated in a previous analysis of Miller OTAs
[10]. In these estimations, the g
m
=I
D
ratios of both SOI
and bulk current mirrors were taken constant and
equal to 5.
Concerning the output swing and noise perfor-
mance, the results of the above analysis as a function
of f
T
were used to compute the total input-referred
thermal noise power spectral density in bulk and SOI
from equations (10)(11). The bulk to SOI noise ratio
ranges from 1.54 for 100 kHz to 3.11 for 10 MHz. To
achieve the same thermal noise performance, lower
g
m
=I
D
values could be used in bulk for the current
Table 1. Experimental SOI and simulated bulk design parameters and performance of the 1-stage CMOS OTA of Fig. 10 C
L
10 pF. The
bulk simulations used the same technology parameters as SOI simulations in good agreement with the measurements, except for the body effect
and junction capacitances. The gate oxide thickness is 30 nm. The n body factor was equal to 1.1 in SOI and 1.5 in bulk, while the drain
extension bottom capacitance per unit area C
jpn
and sidewall capacitance per unit length C
jswpn
of a p(n)-type device were equal to, in the SOI
case, C
jn
C
jp
0:06 fF=mm
2
, C
jswn
C
jswp
0:05 fF=mm and in the bulk case, C
jn
0:18 fF=mm
2
, C
jp
0:4 fF=mm
2
, C
jswn
0:4 fF=mm,
C
jswp
0:5 fF=mm typically.
SOI Bulk
(W/L) 12 30/3 27/3
(W/L) 34 33/3 23/3
(W/L) 56 66/3 46/3
(W/L) 78 30/3 17/3
g
m
=I
D
12 25.8 18
g
m
=I
D
36 22.3 14.5
g
m
=I
D
78 22.7 14
I
DD
(mA) 3 4.32
f
T
(kHz) 350 350
A
v0
(dB) 44 41
phase margin (

) 85.6 85.4
output swing (V) 0.9 0.75
Fig. 12. Comparison of simulated total current dissipation and
DC open-loop gain performance of the bulk and SOI cascoded
CMOS OTAs of Fig. 11 (with B-mirror ratio equal to 2) as a
function of the transition frequency. The computations were based
on the EKV model using similar sets of parameters as in Fig. 8
and Table 1.
Fully-Depleted SOI CMOS Technology 221
mirrors according to equation (11): the higher the
transition frequency, the higher bulk to SOI bias
current ratio, the lower the bulk mirror g
m
=I
D
for same
noise and the larger the output swing reduction in bulk
when compared to SOI. In our case this output swing
reduction can be up to several volts, even for low f
T
,
resulting in unpractical designs.
5. LVLP Microwave Mosfets
Recently, it has been demonstrated that the use of SOI
(SIMOX) wafers on high-resistivity Si substrates
(5000 or 10,000 O? cm) yields MOSFETs which
offer interesting microwave performances. Indeed,
unity-gain frequencies f
T
of 14 and 23.6 GHz and
maximum oscillation frequencies f
max
of 21 and
32 GHz have been reported for gate lengths of 1 and
0.25 mm, respectively [11,28]. Such devices can be
integrated with strip lines or slot lines to implement
MMIC circuits [12,29]. These transistors were
fabricated using a dedicated MOS process, called
MICROX
TM
, which uses non-standard CMOS fea-
tures, such as a metal gate and air-bridge
metallization. The devices which will be described
next were fabricated, contrarily to the MICROX
TM
process, using a standard fully-depleted SOI CMOS
process with N

polysilicon gate, in order to be

compatible with regular analog and digital circuit
parts. The silicon lm thickness is 80 nm, the gate
oxide thickness is 30 nm, and the resistivity of the P-
type substrate is 500 O.cm. The SALICIDE process
was used such that the gates, sources and drains are
covered with TiSi
2
.
Fig. 13 presents the current gain H
21
, the
Maximum Available Gain (MAG) and the Unilateral
Gain (ULG) as a function of frequency in an n-
channel SOI transistor having a length of 0.75 mm and
a width of 125 mm (the gate is composed of 10 parallel
ngers of 12.5 mm each). These parameters were
measured through s-parameter extraction under a
supply voltage V
DS
V
GS
of 0.9 volt. The
Maximum Available Gain is 11 dB at 2 GHz. The
unit-gain frequency, f
T
(found when H
21
0 dB) is
equal to 10 GHz, and the maximum oscillation
frequency, f
max
, (found when ULG 0 dB) is equal
to 11 GHz.
The unit-gain frequency, f
T
and the maximum
oscillation frequency, f
max
, are presented in Fig. 14 as
a function of supply voltage V
DS
V
GS
. These
frequencies rapidly increase as the supply voltage is
increased, up to 1 volt. At higher frequencies, f
T
and
f
max
tend to saturate, due to electron velocity
saturation in the transistors. The values of f
T
and
f
max
are 13 and 15.8 GHz, respectively, for a supply
voltage of 3 volts. The DC power consumption as a
function of supply voltage is also presented in Fig. 14.
Fig. 13. Extraction from S-parameter measurements of the
current gain H
21
, Maximum Available Gain (MAG) and
Unilateral Gain (ULG) as a function of frequency in a 0.75 mm-
long and 125 mm-wide n-channel SOI transistor (the gate is
composed of 10 parallel ngers of 12.5 mm each).
V
DS
V
GS
0:9 V.
Fig. 14. Experimental unit-gain frequency f
T
, maximum
oscillation frequency f
max
and DC power dissipation in the SOI n-
MOSFET of g. 13 as a function of the supply voltage.
222 D. Flandre et al.
The DC power consumed at V
DD
0:9 V, where
f
T
10 GHz and f
max
11 GHz, is equal to 3 mW.
The noise parameters of the SOI MOSFET have
been calculated from a ``50 O'' noise gure measure-
ment [30,31]. Fig. 15 presents the minimum noise
gure and the associated gain produced by the SOI
MOSFET. The associated gain is the gain obtained
when input and output impedance loads are tuned
such as to obtain the minimum noise gure, and is,
therefore, lower than the gain values presented in Fig.
13. Fig. 15 shows that the noise gure gets reduced as
the supply voltage is lowered. At 2 GHz the minimum
noise gure is equal to 2 dB for supply voltage of
1.5 V, and that the associated gain is equal to 9 dB.
These values are competitive with other technologies
[31,32].
These results show that reasonable microwave
performances can be obtained by using n-channel
MOSFETs fabricated using a regular CMOS fully
depleted SOI process, without the use of metal (gold)
gates nor air-bridge interconnections. Such devices
can be integrated along with CMOS analog and digital
low-power functions to yield circuits for e.g. portable
telecommunication applications.
6. Conclusions
We have investigated both theoretically and experi-
mentally the advantages of fully-depleted SOI CMOS
technology, devices and circuits for the realization of
low-voltage low-power circuits signicantly out-
performing bulk CMOS implementations.
The results demonstrate that a basic low-cost
CMOS process on SIMOX substrates with symme-
trical threshold voltages around 0.33 V allows for the
mixed fabrication and operation under a supply
voltage of 1.2 V, of:
digital components with enhanced speed and static
and dynamic power performance;
analog components with enhanced speed, precision,
power, swing and noise performance;
and microwave components with enhanced gain
and frequency performance over bulk counterparts.
Acknowledgments
The authors are thankful to A. Crahay, P. Francis, P.
Loumaye, B. Katschmarskyj and P. Proesmans for
device fabrication. This work is sponsored by the
Belgian French Community under the programs
``Actions Concertees 91/96-147 and 93/-161''. D.
Flandre is Research Associate of the National Fund for
Scientic Research (FNRS, Belgium). L. F. Ferreira is
sponsored by CAPES (Post-Graduate Federal Agency,
Brazil).
List of Notations
a device activity degree
A
vo
amplier DC open-loop gain
C
j
drain extension bottom capacitance per unit area
C
jsw
drain extension sidewall capacitance per unit length
C
L
load capacitance
C
ox
gate oxide capacitance per unit area
C
oxb
SOI buried oxide capacitance per unit area
e
si
Si absolute permittivity
f frequency
f
max
maximum oscillation frequency
F
min
minimum noise gure
f
T
unity-gain frequency
g thermal noise inversion factor
G
ass
associated gain to minimum noise gure
g
d
small-signal output conductance
g
m
small-signal transconductance
H
21
current gain
I
D
drain current
Fig. 15. Variation of the minimum noise gure, F
min
, and the
associated gain, G
ass
, as a function of frequency on a
20625=0:75 mm SOI n-MOSFET biased at V
DS
V
GS
1:5 V
and 2 V.
Fully-Depleted SOI CMOS Technology 223
I
DD
total supply current
I
D0
amplier bias current
I
OFF
OFF state drain leakage current at V
G
0 V
I
ON
drive drain current in ON state
k T/q thermal voltage
L device length
MAG maximum available gain
m effective mobility
n body-effect coefcient
P
dyn
dynamic power dissipation
P
stat
static power dissipation
P
total
total power dissipation
S inverse subthreshold slope
S
V
input-referred noise power spectral density
t
si
SOI lm thickness
ULG unilateral gain
V
A
Early voltage parameter
V
D
drain voltage
V
DD
supply voltage
V
G
gate voltage
V
S
source voltage
V
TH
threshold voltage
W device width
X
d max
maximum depletion width in strong inversion
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Denis Flandre was born in Charleroi, Belgium, in
1964. He received Electrical Engineer and Ph.D.
degrees from the Universite Catholique de Louvain,
Louvain-la-Neuve, Belgium, in 1986 and 1990,
respectively. His doctoral research was on the
modeling of Silicon-on-Insulator (SOI) MOS devices
for characterization and circuit simulation.
In 1985, he was a summer student trainee at NTT
Headquarters, Tokyo, Japan. From October 1990 to
September 1991, he was with the Centro Nacional de
Microelectronica, Barcelona, Spain, working on the
characterization and numerical simulation of SOI
MOS process and devices. He is now at the
Laboratoire de Microelectronique (DICE), Louvain-
la-Neuve, Belgium, as a Research Associate of the
National Fund for Scientic Research (FNRS,
Belgium) and an Invited Lecturer at the Universite
catholique de Louvain giving courses on ``Integrated
analog circuit design''. He is currently involved in the
development of digital and analog SOI MOS circuits
for special applications, more specically high-speed,
low-voltage low-power, microwave, rad-hard and
high-temperature electronics.
Dr. Flandre is co-recipient of the 1992 Biennial
Siemens-FNRS Award for an original contribution in
the elds of electricity and electronics. He has
authored or co-authored more than 90 technical
papers or conference contributions. He is a member
of the Advisory Board of the EU Network of
Excellence for High-Temperature Electronics
(HITEN).
Jean-Pierre Colinge received Electrical Engineer,
and Ph.D. degrees in Applied Sciences from the
Universite Catholique de Louvain, Louvain-la-Neuve,
Belgium, in 1980, and 1984, respectively. He then
worked at the CNET, France, the Hewlett-Packard
Laboratories, USA, and IMEC, Belgium. Dr. Colinge
is now professor at the Universite catholique de
Louvain, leading a research team in the eld of SOI
technology. He has been on the committee of several
conferences, including IEDM and SSDM, has been
general chairman of the IEEE SOS/SOI Technology
Conference in 1988, and is a Fellow of the IEEE. He
has published over 140 scientic papers and two
books on the eld of SOI.
Fully-Depleted SOI CMOS Technology 225
Jian Chen was born in February 26, 1996, in
Zheng Jiang, China. He got his B.S. and M.S. degree
from the Electronics Engineering Department of
Fudan University, Shanghai, China, in 1988 and
1992, respectively. He is currently working as a
research assistant and a Ph.D. candidate in the
Microelectronics Laboratory of Universite
Catholique de Louvain, Louvain-la-Neuve, Belgium.
His research subject is on the development of CMOS-
compatible Thin-Film SOI technology for microwave
and high-temperature applications.
D. De Ceuster is currently at the Microelectronics
Laboratory, Universite Catholique de Louvain, Place
du Levant 3, 1348 Louvain-la-Neuve, Belgium.
Jean-Paul Eggermont (S'92) was born in Braine-
l'Alleud, Belgium, in 1970. He received Electrical
Engineer degree from the Universite Catholique de
Louvain (UCL). Louvain-la-Neuve, Belgium, in
1992. Since then, he has been working towards the
Ph.D. degree at the Microelectronics Laboratory,
UCL, where he is involved in the development of
analog SOI CMOS circuits for high temperature and
high frequency applications.
Luiz Fernando Ferreira was born in Canela, RS,
Brazil, in 1962. He received a B.Sc. degree in
electrical engineering from the Federal University of
Rio Grande do Sul, Porto Alegre, RS, Brazil, in 1986,
and a M.Sc. degree from the Graduate Division on
Computer Science, Microelectronics Group, Federal
University of Rio Grande do Sul.
From 1990 to 1992, he worked at the same
University as an Associated Researcher,
Microelectronics Group. In December 1993, he
joined the Microelectronics Laboratory of the
Applied Science Faculty, Universite Catholique de
Louvain, Louvain-la-Neuve, Belgium. He is now
pursuing a Ph.D. degree there. His research interests
are in high frequency modeling of MOS/SOI
transistors and design of VHF networks.
Bernard Gentinne was born in Huy, Belgium, in
1966. He received a Electrical Engineer and Ph.D.
degrees from the Universite Catholique de Louvain,
Louvain-la-Neuve, Belgium, in 1990 and 1996,
respectively.
From August 1990 to August 1991, he was with the
Ecole Royale Militaire, Brussels, Belgium, working
on real time image processing for giant video screens
with optical bers. From September 1991 to June
1996, he has been working as a Ph.D. student at the
226 D. Flandre et al.
Universite catholique de Louvain, Louvain-la-Neuve,
Belgium. His research concerned the modeling of SOI
MOS devices for characterization and circuits
simulation as well as the conception of analog circuits
working at high temperatures. Since July 1996, Dr.
Gentinne is working with Alcatel-Mietec in Brussels.
P. Jespers got an Electrical Engineer degree from
the Universite Libre de Bruxelles in 1953 and the
doctoral degree from the Universite Catholique de
Louvain in 1959. He was appointed full professor at
the Universite Catholique de Louvain in 1963 where
he headed the Microelectronics Laboratory till 1991.
He became professor emeritus in 1994. His main eld
of interest is analog I.C. design. He has been a visiting
professor in several universities in Europe, USA,
Latin America and fullled missions in India as a
UNIDO expert. Professor Jespers is a Fellow of the
IEEE.
Alberto Viviani received the ``Laurea'' degree in
Electrical Engineering in 1994 from the Universita
degli Studi di Genova, Italy.
He is currently a Ph.D. candidate in Electrical
Engineering at the Universite Catholique de Louvain,
Louvain-la-Neuve, Belgium.
His research interests include analog design in
thin-lm SOI technology.
He is currently working on the implementation of
sigma-delta modulators for low-power and high-
temperature applications.
Renaud Gillon was born in Brussels, Belgium, in
January 1968. He received the electrical engineering
degree from the Universite Catholique de Louvain, in
1991. He is presently preparing a doctoral thesis on
Modeling and Characterizing of the SOI MOSFET in
view of MMIC Applications at the microwave
laboratory of the UCL. His current research interests
include MOSFET modeling, microwave on-wafer
characterization techniques, CMOS mixer and down-
converter design.
Jean-Pierre Raskin was born in Belgium on
March 3, 1971. He received the industrial engineer
degree in Institut Superieur Industriel d'Arlon and BS
in Applied Sciences at the Catholic University of
Louvain, Louvain-la-Neuve, Belgium, in 1993 and
1994, respectively. Since 1994 he has been research
engineer and Ph.D. student at the Microwave
Laboratory of Catholic University of Louvain. His
current research interests include modeling and
characterization of passive and active devices in SOI
technology for microwave applications.
A. Vander Vorst is currently at Microwaves
Laboratory, Universite Catholique de Louvain Place
du Levants, 1348 Louvain-la-Neuve, Belgium.
Fully-Depleted SOI CMOS Technology 227
Danielle Vanhoenacker-Janvier was born in
Brussels, Belgium, in 1955. She received a degree
in Electrical Engineering in 1978, and the Ph.D.
degree in Applied Sciences from the Universite
Catholique de Louvain, Belgium, in 1987.
She is associated with the Universite Catholique de
Louvain, where she was Assistant from 1979 to 1987,
Senior Scientist from 1987 to 1994 and Associate
Professor since 1994 at the Microwave Laboratory.
She is involved in the study of atmospheric effects on
propagation above 10 GHz and the modelization of
the transmission channel for xed and mobile
communications and she is presently responsible for
propagation research. She extended her research
activity to microwave planar circuits in 1989, being
mainly involved in the analysis and measurement of
microwaveplanar active and passive circuits. She is
presently involved in the modelization and measure-
ment of active and passive integrated circuits on SOI.
Professor Vanhoenacker-Janvier is an associated
member of the National Committee of the
International Union of Radio Science, Administrator
of the Belgian Society of Telecommunication and
Electronic Engineers (SITEL) and a Senior Member
of IEEE.
Fernando Silveira was born in Montevideo,
Uruguay, in 1963. He received the electrical engineer
degree in 1990 from Universidad de la Republica,
Montevideo, Uruguay, where he is now Associate
Professor, and a M.S.E.E. from Universite Catholique
de Louvain, Belgium in 1995. He is currently working
toward the Ph.D. degree at the Microelectronics
Laboratory of the Universite Catholique de Louvain.
His research interest is the design of low-power and
low-voltage analog CMOS integrated circuits, parti-
cularly Silicon-on-Insulator technology.
228 D. Flandre et al.