A TWO-PHASE INTERLEAVED POWER FACTOR

CORRECTION BOOST CONVERTER WITH A

VARIATION-TOLERANT PHASE SHIFTING
TECHNIQUE
ABSTRACT
This paper presents a two-phase interleaved critical conduction mode (CRM)
power factor correction boost converter with a variation-tolerant phase shifter
(VTPS), which ensures accurate 180 phase shift between the two interleaved
converters. A feedback loop similar to a phase-locked loop controls the amount of
the phase shifting of the VTPS. The proposed VTPS has better immunity of
process, supply, and temperature variations than the conventional phase shifter.
EXISTING STSTEM
For a heavy load, the CCM is usually employed because it can handle more
current than the DCM and CRM. At the CCM, however, the hard switching of the
freewheeling diode may result in decreased power conversion efficiency. On the
contrary, the freewheeling diode is switched softly at the DCM and CRM and thus
higher power efficiency can be expected. The lower power handling capability of
the DCM and CRM can be overcome by paralleling multiple converters. For the
DCM and CCM operation, it is easy to generate the switching signals M and S
spaced by 180 because the switching frequency fsw is fixed. A clock signal whose
frequency is 2 fsw is divided by 2 to get a 50% duty reference clock for
switching signal generation .The rising and falling edges of the 50% duty reference
clock are used to generate the switching signals M and S , respectively, while
ensuring 180 spacing between them. If a converter operates at the CRM, however,
the switching frequency changes according to the instantaneous input line voltage
and output current at every switching cycle; therefore, it is impossible to generate
the 180 out of phase switching signals by the method explained

PROPOSED SYSTEM
The simplest way of measuring the switching period of the master converter
is to use a ramp generator with UP and DOWN current sources. The mismatch
between the two current sources, however, results in the error of the phase shifting,
increasing the current ripple Iin. A sample-and-hold circuit can be used to
measure the period where only one current source is required. The sampling
capacitor has to be discharged at every cycle and the time required for this results
in phase shifting error. In this paper, a two-phase PFC boost converter operating at
the CRM is described which employs a variation-tolerant phase shifter (VTPS)
ensuring the accurate 180o phase shifting.
BLOCK DIAGRAM
AC INPUT

RECTIFIER

12V DC SUPPLY

5V DC SUPPLY

INTERLEAVED
BOOST
CONVERTER

DRIVER UNIT

PIC MICRO
CONTROLLER

OUTPUT

CIRCUIT DIAGRAM

ADVANTAGES
The input current ripple can be greatly reduced with the proposed phase
shifter compared with the conventional phase shifting techniques. Although
the proposed phase shifter has been applied to a PFC boost converter, it can
be used in any type of two-phase interleaved switching power converter.

LITERATURE SURVEY
[1] Power Factor Correction Basics, Application Note 42047, Fairchild
Semiconductor, San Jose, CA, USA, 2004.
ABSTRACT
A power control system provides immunity from power supply dropout for a
controller without compromising a startup time of the controller. In at least one
embodiment, the power control system includes separate startup and dropout
immunity capacitors. In at least one embodiment, selection of the capacitance of
the startup capacitor is independent of selection of the capacitance of the dropout
immunity capacitance. In at least one embodiment, the startup capacitance can be
minimized to provide sufficient energy for the controller to normally operate
during one missed cycle of an input voltage and, thus, provide a minimum startup
time for the controller. The capacitance of the dropout immunity capacitor can be
maximized to provide sufficient energy for the controller to operate normally
during a time period longer than one cycle of the input voltage.
[2] R. W. Erickson and D. Maksimovic, Fundamental of Power Electronics,
2nd ed. Norwell, MA, USA: Kluwer, 2001, pp. 589630.
ABSTRACT
This book edited and coauthored by a world-renowned team of specialists in
this area is a great asset to industry. It focuses on the following topics:
Fundamentals of Power Electronics; Photovoltaic Power Electronics; Wind Power
Generation; Small Hydroelectric Systems; Fuel Cell Systems; Variable-Speed
Power Generation; Microturbines; Battery Energy Storage Systems; Fast Response
Energy Storage Systems; Modular Power Electronics; Resource Aggregation
Using Microgrids; Power Electronics for Smart Distribution Grids; Advanced
Electric Vehicles; and Multi-Agent Technology for Power System Control. All of
the chapters are well written and richly illustrated, and the material is easy to read.
A table of contents, hundreds of references (presented in each chapter), and an
index are also included.

[3] O. Garcia, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, Single phasepower

factor correction: A survey, IEEE Trans. Power Electron., vol. 18,no. 3, pp. 749
755, May 2003.
ABSTRACT
In recent years, power converters are used to get high power factor. This
PAPER presents an integrated converter topology for driving HB LEDs which
provides high power factor. The integrated buck flyback converter is a single stage,
low cost, high power factor AC-DC converter with fast output regulation. The
converter is used to provide power factor correction in streetlight application. To
obtain high power factor, the buck stage and flyback stage are operated in
discontinuous mode. Dimming operation of HB LED is also described. A closed
loop is used for enabling the PWM dimming..
[4] L. H. Dixon, High power factor pre-regulator for off-line power supplies,
in Proc Unitrode Power Supply Des. Sem, 1990, vol. 700, pp. I2.1I2.6.
ABSTRACT
Design of power factor correction in modern switching power supplies has
evolved in recent years due to the introduction of many new controller chips. It is
possible to design a variety of circuits power factor correction with different
modes of operation, each with its own set of advantages and disadvantages. The
need for greater efficiency stage power factor correction has taken a close look at
all sections of the circuit and develop alternatives with minor losses. A section that
contributes significantly to the losses is the input rectifier bridge. So alternative
methods to eliminate the diode bridge or turn it into a dual-use circuit have been
explored.
[5] M. S. Elmore, Input current ripple cancellation in synchronized parallel
connected critically continuous boost converters, in Proc. IEEE Appl.Power
Electron. Conf., Mar. 1996, pp. 152158.

ABSTRACT
In this paper, a multiphase boost converter is proposed to achieve high
voltage gain and high power gain. The proposed converter operates in continuous
conduction mode (CCM) with soft switching of main and auxiliary devices. The
transformer in a conventional converter is replaced by an auxiliary circuit which
provides the desired voltage and power levels. The zero voltage switching (ZVS)
and zero current switching (ZCS) of the devices is achieved in this topology. The
proposed converter is configured with proper number of series and parallel
connected basic cells in order to obtain the required output voltage and power
levels respectively.
[6] T. Ishii and Y. Mizutani, Power factor correction using interleaving technique
for critical mode switching converters, in Proc. IEEE Power Electron.Spec.
Conf., May 1998, pp. 905910.
ABSTRACT
A new interleaving technique for critical mode switching power
converters (CMSCs) is proposed. The interleaving technique may be
applied to power converters whose switching frequency is variable like
CMSCs. This paper describes the interleaving technique and its operation.
A power factor correction converter composed of two interleaved boost
power converters is also presented

INTRODUCTION
The Power Factor is defined as the ratio between the Real Power and the
Apparent Power in an AC circuit. The Real Power represents the net transferred
energy transferred to the load over one complete AC cycle while the Reactive
Power represents the fraction that is only temporarily stored by the load.
The Real Power is the one measured and monitored for power consumption,
and its associated energy being is used to produce mechanical work and heating.
Traditionally, the power factor is associated with the cosine of angle between the
real and apparent power components. For simplicity the apparent power can be
represented as the vector sum of the real and reactive power, but in the case of non
sinusoidal periodical signals a more complex relationship between these
components is considered.

IPFC Design Overview

A power factor correction block diagram can be divided into 3 main blocks:
First, the rectifier which provides DC voltage to the PFC converter stage, then we
have the PFC converter itself which provides the control over the current shape and
phase lag while regulating the output voltage. Finally we have the controller block.
The PFC converter can be implemented using different circuit topologies, each of
them with their advantages and disadvantages. As it may be observed, the input is
an AC supply, the output of the PFC is a DC voltage. An ideal PFC makes sure
that its input impedance is purely resistive. This allows maximum use of usable
power, or real power. The feedback signals needed for the control loop are the
rectified AC voltage, input AC current and output DC voltage. The output of the
control block is a Pulse Width Modulation (PWM) signal.
The Boost converter has the output voltage greater than the input (also
known as step up converter). When using this topology for power factor correction
the current is continuous. As shown in the current diagram, Continuous
Conduction Mode allows a continuous current through the inductor.

The combination of the Buck Boost converter, as the name suggests, is a

combination of a buck converter and a boost converter, so that the characteristics
of both are achievable. The output voltage can be greater of lower that the input
voltage. One disadvantage of the buck and buck-boost topologies is that the switch
is not referenced to ground, which makes the driver circuitry more complex.
The buckboost topology also inverts the sign of the output voltage, which
brings another disadvantage when comes to a cost effective implementation of the
sensing circuitry. The preferred method for implementing PFC and Interleaved
PFC is the boost converter due to the reduced current ripple, simplicity of gate
driver implementation and also because it meets our requirements of output
voltage. The discontinuous conduction mode of buck and buck-boost topologies
would have a negative influence on the total harmonic distortion, or THD, and
higher gate driver cost.

The boost converters operation is based on the energy stored in inductance

L1 as shown.When Q1 transistor is ON, the current through the inductance is
raising and fly-back diode D1 stops conduction. As soon as Q1 switch opens,
theres no path for the current that was flowing through the inductor, except the
diode D1, the output capacitor C3 and the load. D1 diode closes and starts
conducting since the voltage on its anode is higher than the rectified voltage of AC
source.
The voltage across inductance L1 reverses its sign to maintain current flow.
This way, both the energy supplied by the AC source and the one previously stored
in the inductor are transferred to the load and the output capacitor through diode
D1. The input rectified voltage Vac and the output DC voltage Vdc are measured
using resistor dividers, while the input current is measured using a shunt resistor.
The role of the inductance in this power factor correction topology is essential. The
physical size of the inductor increases with the power rating. Component size is
one of the main reason for implementing an Interleave PFC design.

An interleaved PFC consists of a two boost converter sharing the same load
capacitor. As we can see in the simplified schematic, if we assume we have the
same inductance for each boost converter, we can see that the energy stored by the
system is doubled.
Since the energy stored in the inductors is a key factor for determining the
output power capabilities of the system, the output power provided by single stage
PFC can be provided by an Interleaved PFC with much lower inductance values.
Lower inductance means smaller inductors for a given power rating.

IPFC Reference Design

The difference between an Interleaved PFC and a single stage PFC is that
two inductors are used for energy storage. Since energy should be distributed
equally, a load balancing controller is added to the interleaved PFC to make sure
the system compensates for variation in inductance values or feedback circuits.
The Interleaved PFC system has three main compensators: one for voltage, one for
current and one for load balance. Additionally, a feed-forward controller is
implemented to compensate for sudden input voltage changes. The voltage error
controller makes sure that the output voltage is not affected by load variations. The
inputs to this controller are DC output voltage and the corresponding reference.
The output of this controller is the current compensator reference.
The current error controller regulates the phase and shape of the input
current. This input current is the sum of both inductors currents, and it is measured
using a shunt resistor. The output of this controller is a Pulse Width Modulation
(PWM) duty cycle which will be applied to the power MOSFETS. To balance the
currents through both inductors, a Load Balance Loop is implemented. The inputs
to this compensator are the two currents Im1 and Im2. Ifthese currents are different
an unbalance is detected. The PI controller will regulate this error and adjust the
MOSFETs duty cycles. The output of the load balance control loop will be a duty
cycle correction term (or delta PWM), which is subtracted from PWM1 to get the
final duty cycle of the first boost converter, and it is added to PWM2 to
determine the balanced duty cycle of the second boost converter.

PFC circuits can be classified as either passive or active PFC among which
active PFC is preferred due to its small form factor and higher PF .The operation
modes of an active PFC converter can be classified as the continuous conduction
mode (CCM), discontinuous conduction mode (DCM), or critical conduction mode
(CRM) depending on the current flowing through the inductor.For a heavy load,
the CCM is usually employed because it can handle more current than the DCM
and CRM . At the CCM, however, the hard switching of the freewheeling diode
may result in decreased power conversion efficiency. On the contrary, the
freewheeling diode is switched softly at the DCM and CRM and thus higher power
efficiency can be expected.

Fig. 1. (a) Two-phase interleaved PFC boost converter and (b) waveforms of
a two-phase interleaved CRM PFC converter.

The lower power handling capability of the DCM and CRM can be
overcome by parallelingmultiple converters [6]. Fig. 1(a) shows a simplified block
diagram of a two-phase interleaved PFC boost converter. As shown in Fig. 1(b), if
the switching signals M and S of the two converters are exactly 180 out of
phase, the ripple Iin of the input current can be greatly reduced, which allows
smaller input filter. For the DCM and CCM operation, it is easy to generate the
switching signals M and S spaced by 180 because the switching frequency fsw
is fixed. A clock signal whose frequency is 2 fsw is divided by 2 to get a 50%
duty reference clock for switching signal generation.
The rising and falling edges of the 50% duty reference clock are used to
generate the switching signals M and S , respectively, while ensuring 180
spacing between them. If a converter operates at the CRM, however, the switching
frequency changes according to the instantaneous input line voltage and output
current at every switching cycle; therefore, it is impossible to generate the 180 out
of phase switching signals by the method explained previously.

Fig. 2. Two-phase interleaved PFC boost converter with a VTPS. The components
in the shaded regions are off-chip.

For an interleaved power converter operating at the CRM, a masterslave

scheme has been widely used .Among the multiple paralleled converters, a master
converter operates as a stand-alone one, while the switching of the other converter,
that is, a slave converter, is synchronized with that of the master. For a two-phase
interleaved converter, a phase shifter measuring the switching period of the master
converter can be used to generate the switching signal of the slave converter, so its
switching instant is 180 out of phase from that of the master converter .The
simplest way of measuring the switching period of the master converter is to use a
ramp generator with UP and DOWN current sources . The mismatch between the
two current sources, however, results in the error of the phase shifting, increasing
the current ripple Iin . A sample-and-hold circuit can be used to measure the
period where only one current source is required. The sampling capacitor has to be
discharged at every cycle and the time required for this results in phase shifting
error.
In this paper, a two-phase PFC boost converter operating at the CRM is
described which employs a variation-tolerant phase shifter (VTPS) ensuring the
accurate 180o phase shifting. In Section II, the operation principle and circuit
implementation of the two-phase PFC boost converter are explained and the
stability of the variation-tolerant phase shifting technique is analyzed. The
experimental results follow in Section III and the paper is concluded in Section IV.

TWO-PHASE INTERLEAVED CRM PFC BOOST CONVERTER WITH A

VTPS
Architecture
Fig. 2 shows the block diagram of the two-phase interleaved PFC boost
converter with the proposed VTPS operating at the CRM. The upper converter
consisting of LM ,DM , and SM is the master and the lower one consisting of
LS,DS , and SS is the slave. The output voltage level is compared with the
reference level generated by the bandgap reference (BGR) to generate the error
voltage VCOMP.
For the master converter, the fixed slope ramp signal VRM is compared with
the error voltage VCOMP and the switching signal M becomes LOW when VRM
is larger than VCOMP, decreasing the inductor current IM . The voltage level of
the secondary winding of the transformers is utilized to detect the zero current of
the primary winding. The zero current detector (ZCD) generates the pulse VDTM,
setting M to HIGH when the voltage level of the secondary winding is lower than
the reference level.
The operation of the slave converter is similar to that of the master except
that the slope of the ramp signal VRS is variable to get the accurate 180 phase
difference between the master and slave converters. The slope of VRS is adjusted
by the phase shifting loop consisting of the phase-frequency detector (PFD),
charge pump (CP), loop filter, and ramp generator, so the rising edge of the ZCD
output VDTS of the slave converter is locked to that of HP which is 180 phase
shifted from VDTM by the phase shifter. Because the switch SS of the slave
converter is turned ON by the rising edge of VDTS, the turn-ON instant of the
slave converter is 180 phase shifted from that of the master converter.

Fig. 4. (a) Proposed VTPS and (b) its timing diagram.

Variation-Tolerant Phase Shifter

Fig. 4(a) shows the proposed VTPS with its timing shown in Fig. 4(b).
When the inductor current of the master converter is zero, the ZCD of the master
converter generates a short pulse of VDTM and the next switching period is
started. At this instant, the state of 1 is changed by the toggle flip flop.
When 1 =LOW and C 1 =HIGH, the capacitor C1 is fully discharged and
VR1 is initialized to VREF. When 1 becomes HIGH at t = 0, the capacitor C1 is
now charged by the current source I1 , and VR1 is ramped up. At t = t1, the VDTM
pulse generated by the ZCD toggles 1 to LOW, which flips the connection of C1
, and VR1 is changed to VREF (I1 TSW,n1 )/C1 . Because1 =LOW and C
1 =LOW,C1 is now charged by the two current sources I1 and I2. At t = t2, VR1
can be calculated as

and t2 can be rearranged as

Since the switching frequency for PFC control changes slowly due to the
low bandwidth of the PFC control loop, the previous switching period Tsw,n1 is
almost equal to the present switching period Tsw,n and, therefore, t2 is

At t = t2 , C 1 becomes HIGH to set HP, meaning HP is delayed by

180 from VDTM. As explained previously, the phase shifter cell 1 generates HP
delayed by 180 from VDTM when 1 = LOW. When 1 = HIGH, C 2 becomes
HIGH by the phase shifter cell 2 to generate HP delayed by 180 from VDTM.
While the conventional phase shifter requires UP and DOWN current sources
whose matching is critical but cannot be very good, the proposed one requires only
UP current sources, which can be easily matched. A Monte Carlo simulation has
been performed to see the achievable accuracy of the phase shift under
environmental variations and the results are shown in Fig. 5. The x-axis is the
phase difference between the input signal VDTM and the output signal HP; the yaxis represents the number of events. In order to compare the phase shifting
accuracy with the conventional ones, the conventional phase shifters with UP and

DOWN current sources and with a sample-and-hold circuit are also simulated. As
can be seen in the figure, the proposed VTPS shows much better phase shifting
accuracy than the others against the environmental variations. the importance of
the accurate phase shift between the two converters, where the simulated ripple of
the input current at the peak of the input line ac voltage is shown as a function of
the phase difference of the two converters for the input line voltage of 90 VRMS
and the output current of 700 mA.
Ramp Generator

For the proper operation of the interleaved PFC boost converter, the slope of
the ramp signal VRS of the slave converter should be adjusted by the loop filter
output Vctrl .On the contrary, the ramp signal VRM of the master converter has a
fixed slope. The ramp generators shown in Fig. 7 provide the required VRM and
VRS accordingly. The currents of the transistors M21 and M24 are given as
Vctrl /RB and VREF/RB , respectively, and are copied to the transistors M14
and M11, respectively. Then, the charging current IRS of the ramp generator 2 is
IPWM(VREFVctrl)/RB . Therefore, the ramp slope of the slave converter
increases when the loop filter output Vctrl becomes larger. Because the charging
current IRM of the ramp generator 1 is constant, the ramping slope of the master
converter is fixed.

Stability of the Phase Shifting Loop With the VTPS

In the CRM PFC boost converter, the switching period tsw is the sum of the
on-time ton and off-time toff of the switch and is given as

where vin and vout are input and output voltages, respectively. The variables
in (4) can be represented as the sum of the dc value and small-signal variation
component as

Assuming vin and vo are zero, the aforementioned equation becomes

Therefore, tsw of the nth cycle is the sum of the tsw of the (n1)th cycle
and the variation due to the change in the on-time ton, which can be represented
as

Fig. 9. (a) Small signal model of the slave converter with the VTPS and
(b) its open-loop model.

Perturbation of the switching period when the small on-time perturbation

ton is induced at the slave converter.

Fig. 13. Measured PF and efficiency of the PFC boost converter with the
proposed VTPS.

The variation of the charging current IRS of the ramp generator changes the
on-time as

The magnitude and phase of the open-loop transfer function G(s) are shown
in Fig. 10 when the input line voltage and output current are 90 VRMS and 700
mA, respectively. The crossover frequency of the phase shifting loop is about 5
kHz and the phase margin is 67, which means the phase shifting network is stable.
EXPERIMENTAL RESULTS
In order to verify the performance of the proposed VTPS, three types of twophase interleaved CRM PFC boost converter providing 320 W maximum output
power have been implemented in a 0.35-m BCDMOS process. The three
converters have the same circuitry except the phase shifting network. Two of them
have the conventional phase shifter, that is, the conventional one with the UP and
DOWN current sources and the one with the sample-and-hold circuit . The third
one has the proposed VTPS. Among the three converters, Fig. 11 shows the
microphotograph of the one with the proposed phase shifter. The area of the whole
chip is 2.65 mm2 where the proposed phase shifter occupies 0.14 mm2 .
Fig. 12 shows the measured waveforms of the PFC output VO and the input
current Iin with the three types of phase shifters under different line conditions. As
shown in the figure, the PFC boost converter with the proposed phase shifter
shows the lowest input current ripple because the proposed variation-tolerant phase
shifter provides the most accurate 180 phase shift.
The PFC boost converter provides 393-V dc output fromthe ac input line
voltage of 90264 VRMS. The maximum output current is 800 mA, while 6 mA is
dissipated internally for the operation of the interleaved PFC controller excluding
the driving current of power switch. In Fig. 13, the PF and power efficiency of the
PFC boost converter are shown for the input line voltage of 90, 150, 200, and 264
VRMS with the proposed VTPS. The harmonics of the current are measured for
the input line voltage of 90 and 264 VRMS and the results are shown in Fig. 14(a)
and (b) when the output current is 200 and 800 mA, respectively. The harmonics
are lower than the IEC 61000-3-2 Class-D specifications.
The performance of the PFC boost converter employing the proposed VTPS
is summarized in Table I.

CONCLUSION
For a two-phase interleaved PFC converter, a variation tolerant 180 phase
shifter has been developed and applied to a 320-W CRM PFC boost converter
implemented in a 0.35-m BCDMOS process. The input current ripple can be
greatly reduced with the proposed phase shifter compared with the conventional
phase shifting techniques. Although the proposed phase shifter has been applied to
a PFC boost converter, it can be used in any type of two-phase interleaved
switching power converter.
CONCLUSION
Interleaved PFC allows a more efficient power factor correction design. It
also allows space savings since with a much smaller inductors are needed
compared to single stage PFC design. Interleaved PFC also reduces output current
ripple since two inductors are sharing one load at different times. Ds PIC digital
signal controllers combine the right set of peripherals and computational power to
enable Interleaved PFC control with a single device. This reference design offers a
starting platform for these types of applications and the modular design of the
software makes it easy to understand and to add other functions

SIMULATION

GENERAL
This chapter deals with complete explanation of simulation. In this chapter
complete analysis of simulation circuit is explained. The waveforms obtained in
simulation are shown with simulation diagrams.
PURPOSE OF SIMULATION
Simulation is the discipline of designing a model of an actual or theoretical
physical system, executing the model on a digital computer, and analyzing the
execution output. There are many methods of modeling systems which do not
involve simulation but which involve the solution of a closed-form system (such as
a system of linear equations). Simulation is often essential in the following cases:
1) the model is very complex with many variables and interacting components; 2)
the underlying variables relationships are nonlinear; 3) the model contains random
variants; 4) the model output is to be visual as in a 3D computer animation. The
software used for simulation is MATLAB.
MATLAB
MATLAB is a simulation package specifically designed for power
electronics. With MATLAB interactive simulation capability; you can change
parameter values and view voltages/currents in the middle of a simulation. It is like
having a virtual test bench running on your computer. You can design and simulate
digital power supplies using MATLAB Digital Control Module. The digital control
can be implemented in either block diagram or custom C code.

MATLAB is extremely fast since non-linear elements are only used where
we choose that they are important. Furthermore, the fact that MATLAB separates
power and control has a major effect on reducing simulation time. Another very
useful feature is the ability to integrate DLL blocks into the circuit with the code
that we wrote. This is of great help to emulate a software routine that would be
used in a microcontroller used in our power supplies. We also use those DLL to
emulate all our control logic to again reduce simulation time. In summary, with
MATLAB, we can improve our power supply performance, increase reliability
because we can do virtual testing beyond what we could do in the real life, and
drastically reduce the time to market from design to the final product

SIMULATION DIAGRAM

SUBSYSTEM CIRCUIT

SIMULATION OUTPUTS

SIMULATION DESCRIPTION

PULSE WIDTH MODULATION (PWM)

In pulse width modulation control a fixed DC input voltage is given to the
inverter and controlled AC output voltage is obtained by adjusting the ON and
OFF periods of the inverter components.
The advantages possessed by PWM technique are:
1. The output voltage control with this method can be obtained without any
additional components.
2. With this method, lower order harmonics can be eliminated or minimized
along with its output voltage control. As higher order harmonics can be
filtered easily, the filtering requirements are minimized.

PULSE WIDTH MODULATION INVERTER

DC to AC converters are known as inverters. The function of an
inverter is to change a dc input voltage to a symmetric ac output voltage of desired
magnitude and frequency. The output voltage could be fixed or variable at a fixed
or variable frequency. A variable output voltage can be obtained by varying the
input dc voltage and maintaining the gain of the inverter constant. On the other
hand if the dc input voltage is fixed and it is not controllable a variable output
voltage can be obtained by varying the gain of the inverter which is normally
accomplished by pulse - width modulation (PWM) control within the inverter.
The inverter gain may be defined as the ratio of the ac output voltage to dc input
voltage.
The output voltage waveforms of ideal inverters should be sinusoidal.
However the waveforms of practical inverters are non- sinusoidal and contain
certain harmonics. For low and medium power applications square wave or quasi

square wave voltages may be acceptable and for high power applications low
distorted sinusoidal waveforms are required. With the availability of high speed
power semiconductor devices the harmonic contents of output voltage can be
minimized or reduced significantly by switching techniques.

PWM GENERATION TECHNIQUE:

In the generation of gating signals with sinusoidal PWM there are three
sinusoidal reference waves each shifted by 120. A carrier wave is compared with
the reference signal corresponding to a phase to generate the gating signals for that
phase. Comparing the carrier signal with the reference phases produces gate
signals.

ADVANTAGES OF INVERTER
1. The proposed scheme can be used in high-power, medium- or highfundamental-frequency applications.

2. The fourth leg of the topology makes the inverter have the ability of
handling unbalanced loads.
3. This type of inverter provides balanced load with boosted output.
OBJECTIVE
To Boost the input voltage by two-phase interleaved power factor correction
boost converter which ensures accurate 180 phase shift between the
interleaved converters.

BLOCK DESCRIPTION
GENERAL

This chapter deals with block diagram description of the whole project. In
this chapter we have given complete description of the block diagram.

BLOCK DIAGRAM

AC INPUT

RECTIFIER

12V DC SUPPLY

5V DC SUPPLY

POWER SUPPLY

INTERLEAVED
BOOST
CONVERTER

DRIVER UNIT

PIC MICRO
CONTROLLER

OUTPUT

Power supply unit consists of Step down transformer and a bridge rectifier.
The rating of step down transformer is 12 V. The transformer steps down 230V AC
to 12V AC which is fed to the rectifier unit. The Rectifier unit is used to convert
12V AC to 5V DC which is fed to the PIC Microcontroller.

PERIPHERAL INTERFACE CONTROLLER (PIC)

PIC Microcontroller is used to interface software with hardware. It is
programmed to generate PWM pulses. PIC Microcontroller produces sinusoidal
waves and compares with triangular wave which is produced by crystal oscillator
and thus for each cycle 8 PWM Pulses of 5V are generated. These pulses are fed
to driver circuit.
DRIVER CIRCUIT
The generated PWM pulses are given to the driver circuit in order to amplify
the amplitude of 5V PWM pulse to 12V since 5V pulse generated by PIC
microcontroller is not sufficient to drive the MOSFETs present in the inverter.
Pulse-width modulation

Pulse-width modulation (PWM), or pulse-duration modulation (PDM), is

a modulation technique that conforms the width of the pulse, formally the pulse
duration, based on modulator signal information. Although this modulation
technique can be used to encode information for transmission, its main use is to
allow the control of the power supplied to electrical devices, especially to inertial

loads such as motors. In addition, PWM is one of the two principal algorithms used
in photovoltaic solar battery chargers the other being MPPT.
The average value of voltage (and current) fed to the load is controlled by turning
the switch between supply and load on and off at a fast pace. The longer the switch
is on compared to the off periods, the higher the power supplied to the load is.

The PWM switching frequency has to be much faster than what would affect
the load, which is to say the device that uses the power. Typically switchings have
to be done several times a minute in an electric stove, 120 Hz in a lamp dimmer,
from few kilohertz (kHz) to tens of kHz for a motor drive and well into the tens or
hundreds of kHz in audio amplifiers and computer power supplies.
The term duty cycle describes the proportion of 'on' time to the regular
interval or 'period' of time; a low duty cycle corresponds to low power, because the
power is off for most of the time. Duty cycle is expressed in percent, 100% being
fully on.
The main advantage of PWM is that power loss in the switching devices is
very low. When a switch is off there is practically no current, and when it is on,
there is almost no voltage drop across the switch. Power loss, being the product of
voltage and current, is thus in both cases close to zero. PWM also works well with
digital controls, which, because of their on/off nature, can easily set the needed
duty cycle.
PWM has also been used in certain communication systems where its duty
cycle has been used to convey information over a communications channel.

HARDWARE DISCRIPTION
POWER SUPPLU UNIT

As we know any invention of latest technology cannot be activated without

the source power. So in this fast moving world we deliberately need proper power
source which will be apt for a particular requirement. All the electronic
components starting from diode to Intel ICs work with DC supply ranging from
+5v to +12v. We are utilizing the same cheapest and commonly available energy
source 230V-50Hz and stepping down transformer, rectifier, filter and voltage
regulator. These are described in detail in upcoming topics.
STEP DOWN TRANSFORMER
When AC is applied to the primary winding of the power transformer it can
either be stepped down or stepped up depending on the value of DC, which is
needed. In our circuit the circuit of 230V/12-0-12V is used to perform the step
down operation where a 230V AC appears 12V AC across the secondary winding.
One alteration of input causes the top of the transformer to be positive and the

bottom negative. The next alteration will temporarily cause the reverse. The
current rating of transformer used in our project is 1A. Apart from stepping down
AC voltages, it gives isolation between power source and power supply circuitries.
RECTIFIER UNIT
In the power supply unit, rectification is normally achieved using a solid
state diode. Diode has the property that will let the electron flow easily in one
direction at proper biasing condition. As AC is applied to the diode, electrons only
flow when the anode and cathode is negative. Reversing the polarity of voltage
will not permit electron flow.
A commonly used circuit for supplying large amounts of DC power is the
bridge rectifier. A bridge rectifier of four diodes (4*IN4007) are used to achieve
full wave rectification. Two diodes conduct during negative half cycle and the
other two during positive half cycle. The DC voltage appearing across the output
terminals of the bridge rectifier will be somewhat less than 90% of the applied
RMS value. Normally one alteration of the input voltage will reverse the polarities.
Opposite ends of the transformer will therefore always be 180 degree out of phase
with each other. For a positive cycle, two diodes are connected to the positive
voltage at the top winding and only one diode conducts. At the same time one of
the other two diodes conducts for the negative voltage that is applied from the
bottom winding due to the forward bias for that diode In this circuit due to positive
half cycle D1 and D2 will conduct to give 10.8V pulsating DC. The DC output has
a ripple frequency of 100Hz.
Since each alteration produces a resulting output pulse, frequency=2*50Hz. The
output obtained is not pure DC and therefore filtration has to be done.

FILTERATION UNIT
Filter circuits which are usually capacitors acting as a surge arrester always
follow the rectifier unit. The capacitor is also called as a decoupling capacitor or a
bypassing capacitor, is used not only to short the ripple with frequency of 120Hz
to ground but also to leave the frequency of the DC to appear at the output. A load
resistor R1 is also to leave the frequency to the ground is maintained.C1R1 is for
bypassing ripples.C2R2 is used as a low pass filter, i.e. it passes only low
frequency signals and bypasses high frequency signals. The load resistor should be
1% to 2.5% of the load.
VOLTAGE REGULATORS
The voltage regulators play an important role in any power supply unit. The
primary purpose of a regulator is to aid the rectifier and filter circuit in providing a
constant DC voltage to the device. Power supplies without regulators have a
inherent problem of changing DC voltage values due to variations in the load or
due to fluctuations in the AC linear voltage. With a regulator connected with the
DC output, the voltage can be maintained within a close tolerant region of the
desired output. IC 7812 is used in this project for providing +12V and -12V DC
supply.

PIC MICROCONTROLLER
Features:

High-Performance RISC CPU:

Only 35 single-word instructions to learn
All single-cycle instructions except for program branches, which are
two-cycle
Operating speed: DC 20 MHz clock input DC 200 ns instruction cycle
Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bytes of
Data Memory (RAM), Up to 256 x 8 bytes of EEPROM Data Memory
Pin out compatible to other 28-pin or 40/44-pin
PIC16CXXX and PIC16FXXX microcontrollers
Peripheral Features:
Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler, can be incremented during
Sleep via external crystal/clock
Timer2: 8-bit timer/counter with 8-bit period register, prescaler and
postscaler
o Two Capture, Compare, PWM modules
o Capture is 16-bit, max. resolution is 12.5 ns
o Compare is 16-bit, max. resolution is 200 ns
PWM max. resolution is 10-bit
Synchronous Serial Port (SSP) with SPI (Master mode) and I2C
(Master/Slave)
Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI)
with 9-bit address detection
Parallel Slave Port (PSP) 8 bits wide with external RD, WR and CS
controls (40/44-pin only)

 Brown-out detection circuitry for Brown-out Reset (BOR)

Analog Features:
10-bit, up to 8-channel Analog-to-Digital Converter (A/D)
Brown-out Reset (BOR)
Analog Comparator module with:
o Two analog comparators
o Programmable on-chip voltage reference (VREF) module
o Programmable input multiplexing from device inputs and internal
voltage reference
o Comparator outputs are externally accessible
Special Microcontroller Features:
100,000 erase/write cycle Enhanced Flash program memory typical
1,000,000 erase/write cycle Data EEPROM memory typical
Data EEPROM Retention > 40 years
Self-reprogrammable under software control
In-Circuit Serial Programming (ICSP) via two pins
Single-supply 5V In-Circuit Serial Programming
Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable
operation
Programmable code protection
Power saving Sleep mode
Selectable oscillator options
In-Circuit Debug (ICD) via two pins
CMOS Technology:
Low-power, high-speed Flash/EEPROM technology

 Fully static design

Wide operating voltage range (2.0V to 5.5V)
Commercial and Industrial temperature ranges
Low-power consumption

Pin Diagram:

DEVICE OVERVIEW:

This document contains device specific information about the following devices:
PIC16F873A
PIC16F874A
PIC16F876A
PIC16F877A
PIC16F873A/876A devices are available only in 28-pin packages, while
PIC16F874A/877A devices are available in 40-pin and 44-pin packages. All
devices in the PIC16F87XA family share common architecture with the following
differences:
The PIC16F873A and PIC16F874A have one-half of the total on-chip
memory of the PIC16F876A and PIC16F877A
The 28-pin devices have three I/O ports, while the 40/44-pin devices have
five
The 28-pin devices have fourteen interrupts, while the 40/44-pin devices
have fifteen
The 28-pin devices have five A/D input channels, while the 40/44-pin
devices have eight
Memory Organization:
There are three memory blocks in each of the PIC16F87XA devices. The
program memory and data memory have separate buses so that concurrent access
can occur .

Program Memory Organization:

The PIC16F87XA devices have a 13-bit program counter capable of

addressing an 8K word x 14 bit program memory space. The PIC16F876A/877A
devices have 8K words x 14 bits of Flash program memory, while
PIC16F873A/874A devices have 4K words x 14 bits. Accessing a location above
the physically implemented address will cause a wraparound.

Data Memory Organization:

The data memory is partitioned into multiple banks which contain the
General Purpose Registers and the Special Function Registers. Bits RP1
(Status<6>) and RP0 (Status<5>) are the bank select bits. Each bank extends up to
7Fh (128 bytes). The lower locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose
Registers, implemented as static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special Function Registers from one
bank may be mirrored in another bank for code reduction and quicker access.
I/O PORTS:
Some pins for these I/O ports are multiplexed with an alternate function for
the peripheral features on the device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin. Additional information on I/O
ports may be found in the PICmicro Mid-Range Reference Manual (DS33023).
PORTA and the TRISA Register:
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction
register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in a High-Impedance mode).
Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output
(i.e., put the contents of the output latch on the selected pin). Reading the PORTA
register reads the status of the pins, whereas writing to it will write to the port
latch. All write operations are read-modify-write operations. Therefore, a write to a
port implies that the port pins are read; the value is modified and then written to
the port data latch. Pin RA4 is multiplexed with the Timer0 module clock input to
become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and
an open-drain output. All other PORTA pins have TTL input levels and full CMOS

output drivers. Other PORTA pins are multiplexed with analog inputs and the
analog VREF input for both the A/D converters and the comparators. The
operation of each pin is selected by clearing/setting the appropriate control bits in
the ADCON1 and/or CMCON registers. The TRISA register controls the direction
of the port pins even when they are being used as analog inputs. The user must
ensure the bits in the TRISA register are maintained set when using them as analog
inputs.
PORTB and the TRISB Register:
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction
register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output
(i.e., put the contents of the output latch on the selected pin). Three pins of PORTB
are multiplexed with the In-Circuit Debugger and Low-Voltage Programming
function: RB3/PGM, RB6/PGC and RB7/PGD. The alternate functions of these
pins are described in Special Features of the CPU. Each of the PORTB pins
has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is
automatically turned off when the port pin is configured as an output. The pull-ups
are disabled on a Power-on Reset.
This interrupt can wake the device from Sleep. The user, in the Interrupt Service
Routine, can clear the interrupt in the following manner:
a) Any read or write of PORTB. This will end the mismatch condition.
b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF. Reading PORTB
will end the mismatch condition and allow flag bit RBIF to be cleared. The
interrupt-on-change feature is recommended for wake-up on key depression
operation and operations where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while using the interrupt-onchange feature. This interrupt-on-mismatch feature, together with software
configurable pull-ups on these four pins, allow easy interface to a keypad and
make it possible for wake-up on key depression.
PORTC and the TRISC Register:
PORTC is an 8-bit wide, bidirectional port. The corresponding data direction
register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output
(i.e., put the contents of the output latch on the selected pin). PORTC is
multiplexed with several peripheral functions (Table 4-5). PORTC pins have
Schmitt Trigger input buffers. When the I2C module is enabled, the PORTC<4:3>
pins can be configured with normal I2C levels, or with SMBus levels, by using the
CKE bit (SSPSTAT<6>).
When enabling peripheral functions, care should be taken in defining TRIS
bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to make a pin an input. Since
the TRIS bit override is in effect while the peripheral is enabled, read-modify write
instructions (BSF, BCF, and XORWF) with TRISC as the destination, should be
avoided. The user should refer to the corresponding peripheral section for the
correct TRIS bit settings.

PORTD and TRISD Registers:

PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is
individually configurable as an input or output. PORTD can be configured as an 8bit wide microprocessor port (Parallel Slave Port) by setting control bit,
PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
PORTD Functions:

PORTE and TRISE Register:

PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7)
which are individually configurable as inputs or outputs. These pins have Schmitt
Trigger input buffers. The PORTE pins become the I/O control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user
must make certain that the TRISE<2:0> bits are set and that the pins are configured
as digital inputs. Also, ensure that ADCON1 is configured for digital I/O. In this
mode, the input buffers are TTL.
Register 4-1 shows the TRISE register which also controls the Parallel Slave Port
operation. PORTE pins are multiplexed with analog inputs. When selected for

analog input, these pins will read as 0s. TRISE controls the direction of the RE
pins, even when they are being used as analog inputs. The user must make sure to
keep the pins configured as inputs when using them as analog inputs.
ALGORITHM
The PIC Microcontroller is programmed using MPLAB software. The
program is similar to C program.
Step 1: Start the process
Step 2: Configure the IC.
Step 3: Configure I/P and O/P.
Step 4: Set PWM Period by writing to the PR2 register.
Step 5: Set the PWM duty cycle by writing to the CCPR1L and CCP1CON
register.
Step 6: Make CCP1 pin an output by clearing the TRISC2.
Step 7: Set the TMR2 prescale value and enable timer2 by writing to T2CON.
Step 8: Configure CCP1 module for PWM operation.
Step 9: On the timer.
Step 10: Stop.

FLOW CHART

PROGRAM
include<pic.h>
delay(unsigned int value);
int main()
{
unsigned char dc,i=0xFF;
TRISC = 0 ;
PORTC = 0 ;
PR2 = 0x7c ;
T2CON = 0x05 ;
CCP1CON = 0x0c;
CCP2CON = 0x3c ;
for(;;)
{
CCPR1L = i ;
CCPR2L = ~(i) ;
delay(10) ;
CCPR1L = ~(i) ;
CCPR2L = i;

delay(10) ;
}
}

delay(unsigned int value)

{
int i;
for(i=0;i<value;i++);
}

DRIVER CIRCUIT

OPTOCOUPLER
The main purpose of an opto-isolator is "to prevent high voltages or rapidly
changing voltages on one side of the circuit from damaging components.
Relays can of course provide this kind of isolation, but even small relays
tend to be fairly bulky compared with ICs and many of today's other
iniature circuit components. Because they.re electro-mechanical, relays are
also not as reliable . and only capable of relatively low speed operation.
Where small size, higher speed and greater reliability are important, a much
better alternative is to use an optocoupler.

BUFFER IC

High-to-low level logic conversion

High sink and source current capability.

 5v, 10v and 15v parametric ratings

Impedance matching
DARLINGTON AMPLIFIER

It consists of two emitter followers in cascaded mode. The overall gain is

lose to unity.
The main advantage of Darlington amplifier is very large increase in input
impedance and an equal decrease In output impedance and high current gain.
The emitter current of the first transistor became the base current for the
second transistor.
Hence it is used as high gain operational amplifier.

MOSFET

MOSFET Regions of Operation

There are three regions of operation in the MOSFET
When VGS < VT, no conductive channel is present and ID = 0, the cutoff
region.
If VGS < VT and VDS < VDS, sat, the device is in the triode region of
operation. Increasing VDS increases the lateral field in the channel, and
hence the current. Increasing VGS increases the transverse field and hence
the inversion layer density, which also increases the current.
If VGS < VT and VDS > VDS, sat, the device is in the saturation region of
operation. Since the drain end channel density has become small, the current
is much less dependent on VDS , but is still dependent on VGS, since
increased VGS still increases the inversion layer density

DIODE

A Diode is the simplest two-terminal unilateral semiconductor device. It

allows current to flow only in one direction and blocks the current that flows
in the opposite direction. The two terminals of the diode are called as anode
and cathode.

CONCLUSION
For a two-phase interleaved PFC converter, a variation tolerant 180 phase
shifter has been developed and applied to a 320-W CRM PFC boost converter
implemented in a 0.35-m BCDMOS process. The input current ripple can be
greatly reduced with the proposed phase shifter compared with the conventional
phase shifting techniques. Although the proposed phase shifter has been applied to
a PFC boost converter, it can be used in any type of two-phase interleaved
switching power converter.
CONCLUSION
Interleaved PFC allows a more efficient power factor correction design. It
also allows space savings since with a much smaller inductors are needed
compared to single stage PFC design. Interleaved PFC also reduces output current
ripple since two inductors are sharing one load at different times. Ds PIC digital
signal controllers combine the right set of peripherals and computational power to
enable Interleaved PFC control with a single device. This reference design offers a
starting platform for these types of applications and the modular design of the
software makes it easy to understand and to add other functions