My VHDL cheat sheet by Ramy Rady October 2014

A ) Data Flow (concurrent statements)

______________________________________
used for Gates and simple comb.
concurrent statements:
______________________
1) assignment <= usage " gates , arithmetic operations , shift ,rotation ."
2) conditional assignment (when-else) : "priority encoders , tristate buffers"
target signal <= value1 when condition1 else
value2 when condition2 else
...
valueN-1 when conditionN-1 else
valueN;
3) selected assignment (with-select-when): "Mux , Demux , Decoder "
with choice_expression select
target_signal <= expression1 when choice1,
expression2 when choice2,
expression3 when choice3,
...
expressionN when choiceN;
formats of choices
1- value
2- value1 to valueN

3- value1|value2|... oring boolean

4) generate scheme for equations (for-generate)

label: FOR identifier IN range GENERATE
BEGIN
{concurrent statements}
end GENERATE label;

B) Behavioral (sequential statement)process statement

_____________________________________________________
complex combinational ex (mux,...), state machines,
(registers"collection of
D flip-flops",counters,shift registers,...);
sequential statements used inside process :
___________________________________________
1) if statement
if (boolean expression) then
statements
elsif(boolean expression) then
statements
elsif(boolean expression) then
statements
...
else
end if;

sequential logic

My VHDL cheat sheet by Ramy Rady October 2014

2) Case statement
case condition is
when choice1 =>
statements
when choice2 =>
statements
when choice3 =>
statements
......
when others =>
statements
end case;
3) loop statement (for,while,pure loop)
label: FOR identifier IN range loop
{sequential statements}
end loop label;
label: while condition loop
{sequential statements}
end loop label;
4) wait statement
WAIT UNTIL signal_condition;waits until condition before go to next
WAIT ON signal1 [,signal2,...]; till any signal change
WAIT FOR time; unsynthesizable
WAIT ; forever

C) Structural
_______________

components and interconnects

1-component instantiation (port map)
2-generate for component instantiation (for-generate)
3-component instantiation with generic (generic map,port map)
A component is an instantiation of an entity (plus an architecture)
METHOD #1(used): Explicit component declaration Components declared in main
code , Actual instantiations and port maps always in main code.
METHOD #2: Package component declaration Components declared in a package
EX: written before begin with signal instantiation
COMPONENT mux2to1
PORT (w0, w1, s : IN
STD_LOGIC ;
f : OUT
STD_LOGIC ) ;
END COMPONENT ;
COMPONENT regn
GENERIC (N : INTEGER := 8 ) ; -- default size
PORT (D:IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Enable,Clock:IN
STD_LOGIC ;
Q :OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)) ;
END COMPONENT ;
.....
begin
u1: mux2to1 PORT MAP (w0 => r(0),w1 => r(1),s => s(0),f => p(0));
u5: regn GENERIC MAP (N => 4)
PORT MAP (D => z ,Enable => En , Clock => Clk,Q => t );

My VHDL cheat sheet by Ramy Rady October 2014

Mixed style Modeling

______________________
architecture ARCHITECTURE_NAME of ENTITY_NAME is
Here you can declare signals, constants, functions, procedures
Component declarations
No variable declarations !!
begin

Concurrent statements:
Concurrent simple signal assignment
Conditional signal assignment
Selected signal assignment
Generate statement
Component instantiation statement
Process statement (two process are concurrent)
inside process you can use only sequential statements
end ARCHITECTURE_NAME;

notes
_______
1-Use Processes with IF and CASE statements only. Do not use LOOPS or VARIABLES.
2-Given a single signal, the assignments to this signal should only be made
within a single process block in order to avoid possible conflicts in assigning
values to this signal.as two processes are concurrent
3-in entity

generic( N : INTEGER := 4 );

4- The if statement is identical to when ...else concurrent statement in

synthesis. (they use priority)
5-Also, the case statement is identical to with...select...when
statement in synthesis.
6-For combinational circuits, be careful about the incomplete if statement,
it is synthesized as a latch. (every if should be terminated by else,
and every case should be terminated by when others)
7- CONSTANT name : type := value; declared in (PACKAGE, ENTITY,
ARCHITECTURE,Process)
type WeekDay is (Mon,Tue,Wed,Thu,Fri,Sat,Sun);
type NumericCode is array (7 downto 0) of Integer range 0 to 9;

My VHDL cheat sheet by Ramy Rady October 2014

and
the

shift register is

sample
waveform :

we can have parallel input shift register and also synchronous counters

My VHDL cheat sheet by Ramy Rady October 2014

synchronous counters :
Enable (synchronous): when high enables the counter, when low counter holds its value
Load (synchronous) : when load = 1, load the desired value into the counter
output carry: indicates when the counter rolls over
D3 downto D0, Q3 downto Q0 is how to interpret MSB to LSB

Decoders : Decoders are often used for RAM/ROM addressing

'
If enable=1, one output is asserted high, the other outputs are asserted low , If enable=0, all outputs asserted low

Encoder : only work when exactly one binary input is equal to 1

Priority encoder allows for multiple inputs to have a value of '1', as it encodes the input with the highest priority (MSB = highest
priority, LSB = lowest priority)
"valid" output indicates when priority encoder output is valid
Priority encoder is more common than an encoder