Module 11 Tape Out

Learning
Outcome

At the end of this unit, participants will

Know what is beyond chip and core design.
Know basic tapeout flows and activities involved.
Know how your design style may impact final product.
What we draw is NOT what we get.
Course is mainly for PD education and awareness.

Introduction

Tapeout is the completion of a major milestone in the whole IC

development cycle whereby
o The actual product design is done. All layout work completed.
Design timing/power requirements etc. met. Full chip layout
assembled and verified. Database sent for fracturing.
o Circuit layout is translated into Electron Beam (E-beam)
readable data for process of mask generation by Fab
o Release of Fracture data to Mask vendors, this is the start of
manufacturing of the product

Tapeout

Tape In
o All layout done. Design timing/power etc. met. Full chip
layout assembled and verified. Database sent for
fracturing.
Fracture
o Circuit layout is translated into Electron Beam (E-beam)
readable data for process of mask generation by Fab
Tapeout
o Release of Fracture data to Mask vendors, this is the start
of manufacturing of the product

CMOS VLSI Layout Design

Module 11 Tape Out

Types of tape
out

Tape In

TO Flow

New Product: A-stepping. (first time, brand new: A0)

New Stepping: B0, C0, A full set with design change to an
existing product. All layers are taped out.
Retrofit (Dash stepping):A1, A2, B1, B2 ... Some layers are
modified on an existing product. Only those layers that are
changed are taped out.

All layout done. Full chip assembled. Verification CLEAN!!

Layout audit/review done with design engineers and expert users.
Design timing, power, clocks requirements met!!
o Went through few Dry runs (MOCK tapeouts) to test out
the fracturing, DFM flows, machines usage etc.
Dry runs (MOCKs): Pre-Tapeout activities to
check and decide the proper TapeOut tools/flows
and machines.
Enables best estimation for required resources
o Tapeout deals with the whole Chip at a time, this required
large CPU, huge disks & memory.
All checklists(e.g layout) or waivers(e.g drcs) signed-off by
respective owners.

1.
2.
3.
4.

Create Golden DB
Run Fullchip Verification jobs in parallel (e.g. 22 jobs)
FC verification results analyzed, debugged and fixed.
Send Stream file (GDSII) to Tapeout Team for fracturing and
release to Mask Shop for mask generation.
5. Archive the Whole Data-Base and tools.

GDS = Graphic Database System

is a database file format which is the de facto industry standard for data exchange of integrated
circuit or IC layout artwork. It is a binary file format representing planar geometric shapes,
text labels, and other information about the layout in hierarchical form. The data can be used
to reconstruct all or part of the artwork to be used in sharing layouts, transferring artwork
between different tools, or creating photomasks.

CMOS VLSI Layout Design

Module 11 Tape Out

Fracturing
Process

OPC

Fracture Purpose:
o Flatten the data by removing the hierarchy. (.stm), Breaks
up polygons to rectangles/ trapezoids that the Ebeam can
read.
OPC: (Optical Proximity Correction)
o Improves yield in synthesis flow (dog ears).
Fracture Verification:
o Validate that theres no data dropped or drcs after
fracture (MRC). Also, for retrofits, to validate changes
between old stepping and current changes.
MRC:
o Manufacturing Rule Checker. Checks minimum spacing,
end of line.

OPC stands for Optical Proximity Corrections.

Flow manipulates the drawn and/or synthesized geometries to
improve FAB patterns

Dogears are added to line ends to reduce exterior corner

rounding.
Cutouts are subtracted from interior corners to reduce interior
corner rounding.

CMOS VLSI Layout Design

Module 11 Tape Out

Post OPC

Purpose of OPC

Improve yield

OPC Guidelines

Minimize the total number of jog segments

o Device layout
o Dummification

CMOS VLSI Layout Design

Module 11 Tape Out

Avoid small jog segments

o Interior corners on opposite sides of same line
Avoid interior diffusion corners next to gates
o Minimize such occurrences
Avoid horseshoe layouts
o Increase spacing between end of line segment and
opposite feature

General OPC
Guidelines

CMOS VLSI Layout Design

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CMOS VLSI Layout Design

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Dummification

Why
Dummification?

CMOS VLSI Layout Design

Process of generating dummies - metal, poly, diffusions in the

layout design.
Dummies have no electrical representation but have physical
impact/interference to circuit performance
Dummification is generated during design phase (mainly metals)
and also during fracturing flow (mainly poly and diffusions).
For Pattern density/Uniformity during fabrication.
The ability to control smaller transistor dimensions is
increasingly influenced by the distribution of pattern density
o The number of process steps influenced by pattern density
is growing
Lithography

Module 11 Tape Out

Etch
Polish
Annealing
Design rules that restrict pattern density are improving with each
generation of technology, however, there are still density issues
that are difficult to cover with design rules

Dummification
Dimension

What is
CAMDEX

CAMDEX stands for CATS based Metal Density Extraction

(CATS stands for Computer Aided Transcription System)
Metal Density and CAMDEX- Pre-Tapeout layers density
review.(STR/PLY/Metals)
CAMDEX provides die level modeling of mask layer pattern
density and polish thickness variation
CAMDEX pattern density and polish simulation plots are one of
the primary tools the factories use to assess the manufacturability
of a given device design prior to final tapeout.

CMOS VLSI Layout Design