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High-Speed Addition
Deanna Sessions
ECEN 248-511
TA: Priya Venkatas
Date: November 6, 2013
Objectives:
This lab is designed to teach us why certain circuits are used for certain purposes. In particular
we are going to be looking at carry-lookahead addition for fast addition in high speed arithmetic
units. This particular circuit is better than a ripple carry adder when it comes to high speed
addition and it minimizes the delay that would be encountered in the ripple carry. This will
involve the implementation of dataflow of structural Verilog.
Design:
Below is the source code for all of the different modules that are used in this lab.
//clu
`timescale 1ns/1ps
`default_nettype none
module carry_lookahead_unit (C, G, P, C0);
output wire [4:1] C;
input wire [3:0] G, P;
input wire C0;
endmodule
//cla_4bit
`timescale 1ns/1ps
`default_nettype none
module carry_lookahead_4bit ( Cout, S, X, Y, Cin);
output wire Cout;
//Assigns input and output wires
output wire [3:0] S;
input wire [3:0] X, Y;
input wire Cin;
wire [3:0] G, P;
wire [4:0] C;
endmodule
//block_carry_lookahead_unit
`timescale 1 ns/ 1 ps
`default_nettype none
module block_carry_lookahead_unit(G_star, P_star, C, G, P, C0);
output wire G_star, P_star;
output wire [3:1] C;
input wire [3:0] G, P;
input wire C0;
wire [16:0] C;
wire [15:0] P, G;
wire [3:0] P_star, G_star;
//each of the units called from this point forward are set up based on the schematic from the manual
generate_propagate_unit GPU(G, P, X, Y);
block_carry_lookahead_unit BCLAU0( //calling the block-carry-lookahead and setting up variables
.G_star (G_star[0]),
.P_star (P_star[0]),
.C (C[3:1]),
.G (G[3:0]),
.P (P[3:0]),
.C0 (C[0])
);
block_carry_lookahead_unit BCLAU1(
.G_star (G_star[1]),
.P_star (P_star[1]),
.C (C[7:5]),
.G (G[7:4]),
.P (P[7:4]),
.C0 (C[4])
);
block_carry_lookahead_unit BCLAU2(
.G_star (G_star[2]),
.P_star (P_star[2]),
.C (C[11:9]),
.G (G[11:8]),
.P (P[11:8]),
.C0 (C[8])
);
block_carry_lookahead_unit BCLAU3(
.G_star (G_star[3]),
.P_star (P_star[3]),
.C (C[15:13]),
.G (G[15:12]),
.P (P[15:12]),
.C0 (C[12])
);
carry_lookahead_unit CLAU(
.C({C[16], C[12], C[8], C[4]}),
.G(G_star[3:0]),
.P(P_star[3:0]),
.C0(C[0])
);
summation_unit SU(
.S(S[15:0]),
.P(P[15:0]),
.C(C[15:0])
);
//summation unit
assign Cout=C[16];
endmodule
Questions:
Student Feedback:
1. I liked working with Verilog again. Its really a wonderful program. I disliked that some
of this stuff is confusing to look at and plug into Verilog.
2. Nothing was unclear.
3. I dont really have any suggestions other than possibly a bit more guidance about what
Cin and Cout should be assigned to seeing as that gave me a bit of grief.