Department of Electrical Engineering, IIT Madras Website: http://www.iitm.ac.in/mems/iolab Miniature, accurate, and cost-effective functional photonic/optoelectronic devices/circuits are at high demands now-a-days for applications in the area of computation, communication, biomedical, space and defense environments. Optical grade silicon-on-insulator (SOI) substrate has been established to be an attractive platform for a photonic/optoelectronic integrated circuit (PIC/OEIC). Compact, light-weight, cost-effective, multifunctional and efficient PIC/OEIC can be realized in SOI platform by integrating various photonic and electronic components via low-loss, broad-band and high-speed optical interconnects. Thus, completely a new research area namely, Silicon Photonics had been introduced. Very recently, it has been excellently shown how SOI based CMOS technologies can be exploited to integrate both electronic and photonic devices monolithically. Realizing the trend and prospects, we at IIT Madras have been intensively engaged in silicon photonics research since 2007. We have already succeeded to fabricate and characterize the single-mode ( ~ 1550 nm) SOI rib waveguides, integrated optical polarizer, compact directional coupler, 1X2 & 1X8 power splitters, 100 GHz ITU channel interleaver exploiting the 2-m silicon technology available in our Integrated Optoelectronics / Microelectronics Labs, Dept. of Electrical Engineering, IIT Madras. The rib waveguides used to develop these devices are single-moded (for ~ 1550 nm) and have large mode-size (~10 m 5 m) comparable to that of standard single-mode telecommunication fiber. As a consequence of large cross-sectional area and weakly guiding fundamental mode, typical size of an integrated optical device is very large (~ 1 cm2). The major issue in size reduction is the bend induced waveguide losses. We observed that the bending radius of our large crosssection symmetrically etched rib waveguide should be as large as ~ 10 mm to limit the bend induced waveguide loss to a tolerable level of 1 dB. The bending radius could be reduced to ~ 2 mm by introducing a novel asymmetric slab design of ribs at the bend regions. However, it is still quite large and this large bending radius is the bottleneck for the development of any novel and compact multifunctional IO chip. As we have already acquired the expertise in silicon photonics technology for 2-m feature size, we have decided to explore further for more challenging silicon nanophotonics research with a futuristic goal of 3D integration of optics and electronics. Recently, we have undertaken following research projects in our group: (i) Realization of large bandwidth and high-speed optical interconnects (ii) Photonic wire (PhW) waveguide based pin phase modulator (iii) 1D photonic crystal (PhC) / Bragg grating / ring resonator based waveguide devices (iv) Multimode interference (MMI) based waveguide devices (v) Integrated optical evanescent field sensor For pursuing research project (BTech/MTech/DD) or research thesis (MS/PhD) in any of the above mentioned sub-topics, students need to compulsorily attend one of the following elective courses along with other institute requirements: 1.
GSM-Based Monitoring of PV Power GenerationCurrent A31600.4Voltage VFig. 1. Equivalent circuit of a PV cell.Fig. 2. Typical I–V and P–I characteristics of a PV cell
GSM-Based Monitoring of PV Power GenerationCurrent A31600.4Voltage VFig. 1. Equivalent circuit of a PV cell.Fig. 2. Typical I–V and P–I characteristics of a PV cell