RNC

Hardware Description

8 DIP Switches on RNC Components

DIP Switches on RNC Components

About This Chapter

This part describes the DIP switches on the RNC subracks and RNC boards.
8.1 DIP Switches on RNC Subracks
The DIP switch on the RSS subrack is the same as that on the RBS subrack. The DIP switches
are used to set the subrack number.
8.2 DIP Switches on the AEUa Board
The AEUa board has ten DIP switches. The ten DIP switches are S1, S2, S3, S4, S5, S6, S7, S8,
S9, and S10.
8.3 DIP Switches on the AOUa Board
The AOUa board has two DIP switches which are both SW1. The two DIP switches controls
the mode setting of the two STM-1/OC-3 optical ports.
8.4 DIP Switches on the PEUa Board
The PEUa board has ten DIP switches. The ten DIP switches are S1, S2, S3, S4, S5, S6, S7, S8,
S9, and S10.
8.5 DIP Switch on the MDMC Board
The MDMC board provides one DIP switch. The DIP switch is S2.
8.6 DIP Switches on the PFCU Board
The PFCU board has one DIP switch. The DIP switch is SW1 and consists of four bits. The DIP
switch is used to set the address of the PFCU board.

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8 DIP Switches on RNC Components

8.1 DIP Switches on RNC Subracks

The DIP switch on the RSS subrack is the same as that on the RBS subrack. The DIP switches
are used to set the subrack number.

Location of the DIP switches

The DIP switches are located on the back of the RSS subrack and the RBS subrack, as shown
in 3.1 Components of the RNC Subrack.

Appearance of DIP Switch

Figure 8-1 shows the area of the DIP switch.
Figure 8-1 DIP switch

Description of DIP Switches

The DIP switch on the RNC subrack has eight bits. The higher the bit is, the more significant it
is. If the bit is set to ON, it indicates 0. If the bit is set to OFF, it indicates 1. Table 8-1 provides
the definitions of the bits.
Table 8-1 Bits of the DIP switch

8-2

Bit

Meaning

1, the least significant

bit

Subrack number setting bit

Subrack number setting bit

Subrack number setting bit

Subrack number setting bit

Subrack number setting bit

Parity check bit

Not used in the RNC and is usually set to 0

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Bit

Meaning

8, the most significant

bit

If bit 8 is set to 0, the SCUa board can be started only by the

loading on the OMUa board.

If bit 8 is set to 1, a loading request is sent to the OMUa board

before the SCUa board is started. If the OMUa board responds
within 30 s, the SCUa board is started by the loading on the OMUa
board. If the OMUa board fails to respond within 30 s, the SCUa
board is started by the loading on Flash.

For RNC, bit 8 is usually set to 1.

Setting of DIP switches

Table 8-2 shows the setting of the DIP switches for the RNC subracks. Subrack 0 is an RSS
subrack. Subracks 15 are RBS subracks.
Table 8-2 Setting of DIP switches for RNC subracks
Subrack
Number

Bit
1

Subrack 0

ON

ON

ON

ON

ON

ON

ON

OFF

Subrack 1

OFF

ON

ON

ON

ON

OFF

ON

OFF

Subrack 2

ON

OFF

ON

ON

ON

OFF

ON

OFF

Subrack 3

OFF

OFF

ON

ON

ON

ON

ON

OFF

Subrack 4

ON

ON

OFF

ON

ON

OFF

ON

OFF

Subrack 5

OFF

ON

OFF

ON

ON

ON

ON

OFF

8.2 DIP Switches on the AEUa Board

The AEUa board has ten DIP switches. The ten DIP switches are S1, S2, S3, S4, S5, S6, S7, S8,
S9, and S10.

Allocation of DIP Switches on PEUa Board

Figure 8-2 shows the DIP switches on the AEUa board.

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8 DIP Switches on RNC Components

Figure 8-2 DIP switches on the AEUa board

(1) Sub-board

(2) Bottom plate

CAUTION
As shown in Figure 8-2, the DIP switches are located on the obverse side of the sub-board which
faces the bottom plate and is installed on the bottom plate. Therefore, the DIP switches must be
set before the sub-board is installed on the bottom plate. The part which is marked with dotted
lines in Figure 8-2 cannot be seen directly.

Description of DIP Switches

DIP switches S1S8 are used to set the TX end and the RX end of the E1/T1/J1 cables 031 to
be grounded or not grounded. DIP switch S9 is used to set the FPGA loading mode. DIP switch
S10 is used to set the work modes such as E1 balanced mode, E1 unbalanced mode, T1 mode,
and J1 mode. For details, refer to Table 8-3.
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8 DIP Switches on RNC Components

Table 8-3 DIP switches on the AEUa board

DIP
Switc
h

Bit

Description

Status

Meaning

S1

18

RX ground switch of E1s/T1s/J1s

2431

ON

Setting
work mode
to E1
unbalanced
mode

OFF

Setting
work mode
to other
modes

ON

Setting
work mode
to E1
unbalanced
mode

OFF

Setting
work mode
to other
modes

ON

Setting
work mode
to E1
unbalanced
mode

OFF

Setting
work mode
to other
modes

ON

Setting
work mode
to E1
unbalanced
mode

OFF

Setting
work mode
to other
modes

ON

Setting
work mode
to E1
unbalanced
mode

S2

S3

S4

S5

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18

18

18

18

TX ground switch of E1s/T1s/J1s 24

31

RX ground switch of E1s/T1s/J1s

1623

TX ground switch of E1s/T1s/J1s 16

23

RX ground switch of E1s/T1s/J1s 0

7

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DIP
Switc
h

S6

S7

S8

S9

8-6

Bit

18

18

18

12

Description

TX ground switch of E1s/T1s/J1s 0

7

RX ground switch of E1s/T1s/J1s 8

15

TX ground switch of E1s/T1s/J1s 8

15

DIP switch for setting FPGA loading

mode. It consists of two bits.

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Status

Meaning

OFF

Setting
work mode
to other
modes

ON

Setting
work mode
to E1
unbalanced
mode

OFF

Setting
work mode
to other
modes

ON

Setting
work mode
to E1
unbalanced
mode

OFF

Setting
work mode
to other
modes

ON

Setting
work mode
to E1
unbalanced
mode

OFF

Setting
work mode
to other
modes

(ON, ON)

Setting
loading
mode to
JTAG
configurati
on

(OFF, OFF)

Setting
loading
mode to
CPU slave
parallel

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DIP
Switc
h

Bit

Description

Status

Meaning

configurati
on
S10

12

DIP switch for setting work mode. It

consists of two bits.

(ON, ON)

Setting
work mode
to E1
unbalanced
mode

(OFF, ON)

Setting
work mode
to E1
balanced
mode

(ON, OFF)

Setting
work mode
to T1 mode

(OFF, OFF)

Setting
work mode
to J1 mode

NOTE

If signals are transmitted in E1 unbalanced mode, the signals are transmitted through the 75-ohm coaxial
cable and the RX end of the cable is grounded, that is, the corresponding DIP switch is set to ON. If
signals are transmitted in other modes, the signals are transmitted through the 120-ohm twisted pair
cable and the RX end of the cable is not grounded, that is, the corresponding DIP switch is set to OFF.

By default, all the DIP switches are set for the transmission in E1 balanced mode and the loading mode
of CPU slave parallel configuration. That is, all bits of S1S9 are set to OFF. Bit 1 of S10 is set to OFF
and bit 2 of S10 is set to ON.

Ensure that the matching between the different types of DIP switches is correct.

8.3 DIP Switches on the AOUa Board

The AOUa board has two DIP switches which are both SW1. The two DIP switches controls
the mode setting of the two STM-1/OC-3 optical ports.

Allocation of DIP Switches on PEUa Board

Figure 8-3 shows the DIP switches on the AOUa board.

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Figure 8-3 DIP switches on the AOUa board

Description of DIP Switches

Table 8-4 describes the switches on the AOUa board.
Table 8-4 DIP switches on the AOUa board

8-8

DIP Switch

Bit

Status

Meaning

S1

12

(ON, ON)

Setting loading mode

to JTAG
configuration

(OFF, OFF)

Setting loading mode

to CPU slave parallel
configuration

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DIP Switch

Bit

Status

Meaning

ON

Setting work mode to

T1 mode

OFF

Setting work mode to

E1 mode

ON

Setting the mapped

path to AU3.

OFF

Setting the mapped

path to AU4.

ON

Setting the
information structure
to TU11.

OFF

Setting the
information structure
to TU12.

ON

SONET

OFF

SDH

Reserved

Reserved

NOTE

All the bits are set to OFF by default.

8.4 DIP Switches on the PEUa Board

The PEUa board has ten DIP switches. The ten DIP switches are S1, S2, S3, S4, S5, S6, S7, S8,
S9, and S10.

Allocation of DIP Switches on PEUa Board

Figure 8-4 shows the DIP switches on the PEUa board.

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8 DIP Switches on RNC Components

Figure 8-4 DIP switches on the PEUa board

(1) Sub-board

(2) Bottom plate

CAUTION
As shown in Figure 8-4, the DIP switches are located on the obverse side of the sub-board which
faces the bottom plate and is installed on the bottom plate. Therefore, the DIP switches must be
set before the sub-board is installed on the bottom plate. The part which is marked with dotted
lines in Figure 8-4 cannot be seen directly.

Description of DIP Switches

DIP switches S1S8 are used to set the TX end and the RX end of the E1/T1/J1 cables 031 to
be grounded or not grounded. DIP switch S9 is used to set the FPGA loading mode. DIP switch
S10 is used to set the work modes such as E1 balanced mode, E1 unbalanced mode, T1 mode,
and J1 mode. For details, refer to Table 8-5.
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Table 8-5 DIP switches on the PEUa board

DIP
Switc
h

Bit

Description

Status

Meaning

S1

18

RX ground switch of
E1s/T1s/J1s 2431

ON

Setting work
mode to E1
unbalanced
mode

OFF

Setting work
mode to other
modes

ON

Setting work
mode to E1
unbalanced
mode

OFF

Setting work
mode to other
modes

ON

Setting work
mode to E1
unbalanced
mode

OFF

Setting work
mode to other
modes

ON

Setting work
mode to E1
unbalanced
mode

OFF

Setting work
mode to other
modes

ON

Setting work
mode to E1
unbalanced
mode

OFF

Setting work
mode to other
modes

ON

Setting work
mode to E1
unbalanced
mode

S2

S3

S4

S5

S6

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18

18

18

18

18

TX ground switch of
E1s/T1s/J1s 2431

RX ground switch of
E1s/T1s/J1s 1623

TX ground switch of
E1s/T1s/J1s 1623

RX ground switch of
E1s/T1s/J1s 07

TX ground switch of
E1s/T1s/J1s 07

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DIP
Switc
h

S7

S8

S9

S10

8-12

Bit

18

18

12

12

Description

RX ground switch of
E1s/T1s/J1s 815

TX ground switch of
E1s/T1s/J1s 815

DIP switch for setting

FPGA loading mode. It
consists of two bits.

DIP switch for setting

work mode. It consists of
two bits.

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Status

Meaning

OFF

Setting work
mode to other
modes

ON

Setting work
mode to E1
unbalanced
mode

OFF

Setting work
mode to other
modes

ON

Setting work
mode to E1
unbalanced
mode

OFF

Setting work
mode to other
modes

(ON, ON)

Setting loading
mode to JTAG
configuration

(OFF, OFF)

Setting loading
mode to CPU
slave parallel
configuration

(ON, ON)

Setting work
mode to E1
unbalanced
mode

(OFF, ON)

Setting work
mode to E1
balanced mode

(ON, OFF)

Setting work
mode to T1 mode

(OFF, OFF)

Setting work
mode to J1 mode

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NOTE

If signals are transmitted in E1 unbalanced mode, the signals are transmitted through the 75-ohm coaxial
cable and the RX end of the cable is grounded, that is, the corresponding DIP switch is set to ON. If
signals are transmitted in other modes, the signals are transmitted through the 120-ohm twisted pair
cable and the RX end of the cable is not grounded, that is, the corresponding DIP switch is set to OFF.

By default, all the DIP switches are set for the transmission in E1 balanced mode and the loading mode
of CPU slave parallel configuration. That is, all bits of S1S9 are set to OFF. Bit 1 of S10 is set to OFF
and bit 2 of S10 is set to ON.

Ensure that the matching between the different types of DIP switches is correct.

8.5 DIP Switch on the MDMC Board

The MDMC board provides one DIP switch. The DIP switch is S2.
Figure 8-5 shows the DIP switch on the MDMC board.
Figure 8-5 DIP switch on the MDMC board

With four bits, the DIP switch S2 is used to set the address of the WDMB.
To set the address, pull out the WDMB as described in the Replacing an MDMC Board. Then,
set S2 as listed in Table 8-6.
Table 8-6 DIP switch on the WDMB
DIP Switch

Bit

Status

Meaning

S2

1, the most
significant bit

ON

ON

ON

4, the least
significant bit

ON

CAUTION
In the RNC, the address of the MDMC board is 0 by default. Therefore, the DIP switch on the
MDMC board must be set as described in Table 8-6.

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8.6 DIP Switches on the PFCU Board

The PFCU board has one DIP switch. The DIP switch is SW1 and consists of four bits. The DIP
switch is used to set the address of the PFCU board.
Figure 8-6 shows the DIP switch on the PFCU board.
Figure 8-6 DIP switch on the PFCU board

To set the address, pull out the fan box. Then, set the DIP switch as described in Table 8-7. For
how to pull out the fan box, refer to Replacing an RNC Fan Box. After the setting, the address
of the PFCU board is 1.
Table 8-7 DIP switch on the PFCU board

8-14

DIP Switch

Bit

Status

Meaning

SW1

1, the least significant bit

OFF

ON

ON

4, the most significant bit

ON

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