A lV, 2.4GHz Fully Integrated LNA Using 0.

18pm CMOS Technology

Lilo Zheiying, S.C.Rustngi, A%F.Li,Yong Linn

Signal Processing and VLSI Design Lab, Department of Electrical and Computer Engineering
National University of Singapore, Singapore 1 19260
* Institute of Microelectronics, Singapore 117685

Correspondence Author: Professor M.F. Li elelimf@us.edu.sg

ABSTRACT

values of the MIM capacitor RF models are observed to

A 11: ?.4GHz fully integi-ated CMOS Low Noise

Amplifier (LNA) including the 500 referenced input
output matching networks is implemented using 0.ISpin
technology within a chip area of4.1mm2. The amplifier
h k the noise figure (NF)of 3.8dB and a forward gain
of more tlian ZOdB. The details ofthe LNA analysis and
design procedure are presented in this paper.

scale with the capacitance value.

Noise Figure Optimization

For the two stages LNA structue, the input MOSFET
of the first stage is the main noise c o n t n h t o r [2] and its
size needs to be optimally chosen for noise
considerations. The input matching network is shown in
Fig 2(a) and is simplified into Fig 2(b) under the
assumption that C, is chosen small enough tc avoid the

1. INTRODUC.IION

The first stage of a wireless receiver is typically an

LNA, whose main function is to provide enough gain to
~ v e r c o m ethe noise of subsequent stages. Many LNA
designs are published sofarl most of them use off-chip

large amount input signal shunt to ground, thus the

diflerence from R, to Re, or from Lx to L,, is not
significant. This leads to the conclusion that the
optimum size of MI in Fig 2(b) will not vmy much

nework [3] or bolid wire inductor [GI to accomplish the

matching. In this paper, a fully integrated CMOS LNA

from that of MI in Fig 2(a).

without off-chip matching network is proposed. Section

2 provides the detail design procedures and the
measurement sesultq are shown in section 3

2. LNA DESI&
(a)

- A -

@)

--L
-

Fig 2 Input structwc

p*ucL
The noise factor of the simplified input structure of Fig

2(b) is shown in equation (I), its detail expression can

be found in [3], wherePD is the power dissipation of the

input stage; y i s the channel themial noise coefficient,

vrvr and & are the carrier saturation velocity and
electrical field respectively. We can also find W, the

cg

Fig 1 LNAGnd.
Dingmm

__lhe proposed LNA diagram is shown in Fig 1. We have

channel width of M I , as a function of p and P D as

shown in ( 2 ) . If we solve p as an expression of CV and

used extiacted RF models for all the components to

achieve a first silicon success . The main difficulty
arises from the limited number of spiral inductors for

PD as shown in (3) and substitute it into (I), the noise

factor can be exprzssed in (4) as a function of Wand PD.
The curves of NF versus Wunder some fixed PD are

which the extracted models are available. This puts a

premium on the careful choice of the inductor to be
used. The situation however eases out somewhat with
the help of MIM capacitors as the lumped component

shown in Fig 1. By using powerful mathematical

softwares, the complicated delivation of the detail

0-7803-7Sd9-X/03/$17.00~2003IEEE.

expression of (4) is avoided. Parametel- values used in

(4) c m be found in the Appendix.

1062

p = /;'(I+'

.P, 1

between the gate of MI and ground to give another

order of freedom of tuning Z, as shown in the
approximated expression of (6). Note that if C, is small
enough to be neglected, Z,,,
in (6) will shrink back to the
espression (5).

(3)

L
\F
. = I + - e P (II'. P, )
3>$*2
)r,J

(4)

It is clear from Fig 3 that for every given

PD there is a

corresponding optimum value of 'K which yields the

minimum noise figure. In this LNA design, PD is
specified as 4.51nW (the solid line) and the optimum
value of W is around 250prrr. The selection of W is a
trade-off between the available RF models and the
optimum noise figure, thus l,P' of 1 S O p is chosen for
which the extracted RF models were available. In this
I+' range, the noise figure does not deteriorate
significantly

(7)

Linearity consideration
One of the advantages of two stages amplifier is'that it
separates the optimization tasks of noise, linearity
perfomance and input, output matching while, for
single stags LNA; they need to be considered
simultaneously. In a cascade structure, !P3 of the last

Fig 3 NF vs. W

Pi 4 LNA input stage

Thc cascodc device MO "shields" MI from signal

variations at its drain and greatly reduces p121,thus the
LNA can'he treated approsimatek as a unilateral design

(pl+O)

[A]. In this way MO reduces the interaction of

the tuned output with the tuned iiiput that facilitates the
matching task. Chan!icl width of MO is simply chosen
the samr size as MI; 150pr1, to provide the 4.SmW
power dissipation ofthe input stage.

stage is the prominent factor of the total IP3 [l][2], thus

M2 contributes more to the LNA linearity than M1
IIP3 of M2 can be written as (7) [7], where B is the
normal field mobility degradation factor. (7) shows that
IIP3 of the second stage can be enhanced by increasing
Ji,, for this reason the gate of M2 is connected to J/,
through Ldl to give V x Jthe
~ maximum value. However.
it increases the power dissipation as well; channel width
of M2 needs to be reduced to compensate this problem.
Foitunately, ieducing the channel width of M2 will not
affect the lineaiity significantly, thus a small device
with relatively high J,;
is the way used hei-e to improve
linearity of the LNA [?]

Ontput mutching
Making output matching is more complicated than the

Input matching

input one because the output impedance is vel?

'The input matching netwoi-k is shown in Fig 4. L,, L,

and MI constiuct a source degeneration stage [SI,
without C
;, the input impedance is:

sensitive to the component values. L',, is the load

inductor of the first stage, however it affects the output
impedance significantly. As shown in the setup in Fig 5 ,
R, is the output 1-esistance looking into the drain of M2.

If the value of Ldl is chosen improperly, R, will become

negative at the desired resonant frequency and thus

In (5);L, is chosen to make the real part of Zit, to match

the signal source resistance and Lx selves the role of
canceling the imaginary part of Z,,,. However, that's not
alwnys true while' Ls and L, can not be tuned
continuously. In this case, capacitor C, is connected

introduces the instable factor: &+-I. We can get a

more intuitive view from the simulation result in Fig 6.
At the frequency of 2.40Hz, if Ld, is given a value of
4nH. R, is negative.' In auother two cases, when Ldl is
.

chosen InH or SnH, R, becomes positive.

1063

To fuither investigate how Ldl affects &, the small

signal analysis of Fig 5 is provided here. The circuit in
Fig 5 is simplified to the equivalent circuit in Fig 7.
Note that the effect of the input stage (including MO,

process or a different setup of component values,

maybe region A is a good option. Again, changing L d 1
will not change the input matching much due to the
isolation created by MO and its effect can he minimized
by finely tuning C, in the later optimization step.

MI: L,, L, and C,) is neglected for simplicity thanks to

the isolation provided by MO. The expression of R, is

As illustrated in Fig 9, after Ldl is decided, the output

impedance positions at point I . If L d 2 can he
continuously tuned, ideally L d z can he given a value that
delivers the output impedance ,Z
,, from point 1 to 3,
which is the intersection of the line of L d j and 50Q
circle. In this case, the shunt capacitor, CL, is not
necessary for output matching. However, the turns of
the spiral inductor are discrete thus La should he given
a slightly SMALLER value to make room for C, to.tune
the point 2 hack to 3. But a TOO SMALL Ld.' will
greatly enlarge CL.That causes a problem which makes
LQ becomes a sensitive component for output
impedance: the oscillation frequency shown in (9)
comes close to the resonant frequency (2.4GHz). This
problem was overlooked in this LNA design and its
effect will he shown in the experimental result later. CO,
the last component undecided, is used to compensate
the imaginaq part of the output impedance and isolate
the DC path between LNA and its load.

shown in (8):

.8

24

12

96

Freq (GHz)
Fig 5

Fig 7 h12 & U1

Fig 6Simuliltion result of Ra VS. Req

Fig 8 Ro vs Freq

1'; =Wro

p-(f/xfJp-(J/Lf
(8)
l l - i / / ~ ) ~ ~ +l-if/X
~-(//~)*~i//.~~

.%=r

x
(,*-a
b]
p

IMere .r;-Jzn~~,(c~,;+c,,+c,~,,c,)
f, -JbJ2

,r, I 1 j 2 n K and J, I 1/2m;,C,:

. Curve of R, versus

frequencv is illustrated in Fig 8. The effect of

is

&!A/

eliminated by ,6 in the frequency range we are

consideling since f? is much higher than 2.4GHz. The

. ~-

3. E~~~~~~~~~~~ R

mentioned before: the negative R, region. Thus Ldl

needs to he properly chosen to shift region B to the left
side or right side to drop the resonant frequency
(2.4GHz) into region A or C. If region A is chosen, Ldl
should he given a small value (around InH according to
Fig 6 i n this particular design) to ensurefi>2.4GHz, that

The micrograph of this LNA is shown in kig 10. This

IC is implemented in a 0.18pni six metal process. The

chip area is mainly occupied by the four spiral inductor
Ls, L,, L d 1 and L a , whose inductance are 13.2nH, 2.6nH,
8.3nH and 1.6nH respectively at 2.4GHz. Capacitances

\!,ill largely reduce the forward power gain. Thus region

C p fi) is chosen; which requires a relatively large

Ldl to ensure that R, is positive at 2.4GHz (2.4GHz >h).
'

Fig 10 LNA ndc-ph

Fig 9 Mlselection

frequency axes can he divided by fi and h into three

regions: A: B and C. B is :!le undesired region a s

of the three MIM capacitors C,, CL and CO are j O f F ,

1.9pF and 0.9pF. Channel lengths of all transistors are
0.18pni. S-parameten measurement results are shown in

Fig 11. Marker 1 is positioned' at 2.4GHz, the desired

Note that this is a case-hycase study, in a different

1064

resonant frequency. Input and output matching are quite

good: SI, is-16.8dB while S?.. is-l0.2dB. The forwad
gain (&I) is 23dB, and it has a value of more than 20dB
f~-oni2.2 to 3.4GHz. The reverse isolation @ I I I ) is less
than -5OdB at 2.4GHz. A problem occurs as we pay
attention on marker 3. There is an abnormal behavior
around 2.8GHz. This is the oscillation caused by C, and
Li12 that is explained .in section 2. Fig 12 shows that
noise figure ahnost reaches its lowest value, 3.8dB, at
2.4GHr. This measurement result differs from the
theoretical value of around 2.ldB in Fig 3, which
implies that, if we want a mol-e precise prediction, we
need to take into account the noise contribution from
the other two NMOS, MO and M3, and the four spiral
inductors whose quality factors are far f~-omideat. In
Fig 13, the two tones IP3 test (2.4 and 2.41GHz) shows
that the IIP3 of this LNA is about -9dBm. All the
meesurement results are listed in Table 1

EEi
*OB.!

5 8 dB/ *FF 10 db
2 q86.088 [ioa

IWdB

nr-

demonstrated in this paper together with its detail

analysis and design procedures. We ciin see that, the
,performance of the amplifier is sensitive to the
component values especially for the output stage design
to which we need to pay more attention.
Fmquency

2.4 GH2

SII

-16.8dB

1.0 v

-51.7dB

Power Dissiparion

13.0 nmW

S,i
SZI

(FirstSfnge)

4.5niR

Sa

-1O.ZdB

NF (a)

3.6 dB

IIP3

-9.1 dBm

Power supply

23.0 dB

Table 1 LNA p e r f o m m e summaly

ACKNOWLEDGMENT
The authors would like to thank the Institute of
Microelectronics of Singapore for pioviding the RF
component models.

REFERENCE
[I] Behzad Razavi, RF .hlcroe/ecti-oriics , Prentice
Hall PTR.
[2] Piljae Park, Cheon So0 Kim, and Hyun Kyu Yu
Linenrip, Noise optiniizntiori for Two Stage RF
CMOS LAY, Proceedings of TENCON 2001,
vo1.2, pp. 756758,2001
[3] Derek K. Shaeffer, Thomas H. Lee, A 1.5-1.: 1.5-

GHz CMOS Low Noise Amplifier , IEEE Journal of

Solid-State Circuits, Vol: 32, No. 5, MAY 1997.
[4] Reinhold Ludwig, Pave1 Bretchko, RF Circuir
Desigri , Prentice Hall.

[SI Thomas H. Lee, Tlie Design

o/ CMOS RadioFrequency Integrared Circuits , Cambridge, New

York: Cambridge Univ. Press, 1998.

[6] P. Leroux, 2 0.8-dB N F ESD-Protected PniW

CMOS LNA Oper,nririg at I.23GHz , IEEE Journal
of Solid-State Circuits, Vol. 37, No. 6, June 2002.
[7] Wei GUO, Tlie Noise mid Linearip Opfiniizntion
j o r A 1.9-GHz CMOS Low Noise Amnplifier ,IEEE
Asia-Pacific Conference, 2002.

APPENDIX
F
i
g 12 Noise Figulur

Fig 13 Two tone lest

Parameter values used in estimating the fixed power

noise figure versus the channel width of MI :

5. CONCLIISION

Reg
L,
yI

The two stages 0 . 1 8 p ~fully integrated CMOS LNA

with the input and output matching networks is

11065

50
2.6nH
2.5

6 01
lcf3]

5.0

&,

0.76E7

0.395

v,~,

0.8E5