New Stationary Frame Control Scheme for Three

Phase PWM Rectifiers Under Unbalanced Voltage

Dips Conditions
D. Roiu, R. Bojoi, L.R. Limongi, A. Tenconi
Politecnico di Torino, Dipartimento di Ingegneria Elettrica
C.so Duca degli Abruzzi, 24, 10129, Torino, Italy

AbstractA new stationary frame control scheme for three-phase

Pulse Width Modulation (PWM) rectifiers operating under
unbalanced voltage dips conditions is proposed in this paper. The
proposed control scheme regulates the instantaneous active
power at the converter poles to minimize the harmonics of the
input currents and the output voltage. The paper novelty is the
development of a new current-reference calculation implemented
directly in stationary reference frame. This allows using
Proportional Sinusoidal Signal Integrators (P-SSI) controllers
for simultaneous compensation of both positive and negative
current sequence components. No Phase Locked Loop (PLL)
strategies and coordinate transformations are needed. A
comparison with two other existing control techniques is also
performed. Experimental results are presented for a 20 kVA
AC/DC converter prototype to demonstrate the effectiveness of
the proposed control scheme. Fast dynamic performance with
small DC-link voltage ripple and input sinusoidal currents are
obtained with this control scheme even under severe voltage dips
operating conditions.
Keywords AC/DC converter, voltage dips, Proportional
Sinusoidal Signal Integrators, digital control.

I.
INTRODUCTION
When compared with thyristor or diode rectifiers, the PWM
AC/DC converter (Fig. 1) has some advantages, such as:
sinusoidal input current, smaller output filter capacitor,
controllable power factor and bi-directional power flow. The
system is sensitive to voltage dips and input impedance
unbalance. Voltage dips are considered the most severe
disturbances for the industrial equipment [1]. They may
frequently occur in three-phase power systems, due to
unbalanced power supply, unbalanced loads and various faults.
Under these conditions, it has been shown that even dc-link
voltage harmonics and odd AC input currents harmonics will
appear [2,3]. These effects happen due to the low order power
oscillations given by the presence of the negative sequence
component in the unbalanced voltage dips.
Different control schemes have been proposed in the
literature to improve the performance of PWM rectifiers under
unbalanced voltage supply conditions. Some interesting
applications of these control schemes are: the fault ride-through
capability of the variable speed wind power plants, Adjustable
Speed Drives (ASDs) using back-to-back converters and VSCHVDC transmissions (Voltage Source Converter-High Voltage
Direct Current) [4-9].

One of the most used control strategy to minimize the

input/output harmonics is to regulate the instantaneous active
power at a constant value.
In [10-13] the authors proposed control schemes in
synchronous reference frame or in stationary reference frame to
regulate the instantaneous active power supplied from the AC
input source pin for unbalanced input voltage. The drawback of
this strategy is the not constant instantaneous active power at
the converter poles pout even with a constant input active power
pin (Fig. 1) since the power related to the AC input filter is
neglected. For high-power applications, the impact of the
interface reactors must be taken into account to eliminate
ripples of the instantaneous power and DC-link voltage.
A control scheme that includes the impact of instantaneous
power of the AC inductors by regulating the instantaneous
active power at the converter poles has been developed in
[14,15]; this method is more effective in harmonics elimination
under unbalanced operating conditions when compared with
the methods proposed in [10-13]. However, this method has
two disadvantages: (1) the complexity of solving nonlinear
equations in real time and (2) the low bandwidth of the current
regulator due to sequential-component extraction block in
current loop feedback.
To solve these problems, a control scheme using dual
current regulators with oscillating reference signals in a hybrid
synchronous reference frame was proposed in [16,17].
pout

pin
ea
n

PCC

eb

ec

vb

vc

eabc

iL

va

iabc

Cd

RL

Control
Scheme

Figure 1. Block diagram of the PWM AC/DC Converter.

978-1-4244-2279-1/08/$25.00 2008 IEEE

In this way, the extraction of the current sequence

components has been eliminated. A simplified currentreference calculation is also proposed, in order to eliminate the
need of solving nonlinear equations in real time. Because of the
existence in the reference signals of an oscillating part, the
authors introduced a resonant gain in the current regulator. This
scheme requires four separate Proportional-Integral (PI) and
SSI current controllers (PI-SSI) implemented in Positive
Negative Synchronous Reference Frames (PNSRF). In
addition, feedforward and decoupling terms have been used,
resulting in a complex control scheme.
Notch filters for filtering the oscillating part existing in the
feedback and feedforward signals of current control loop were
used in [18]. A control scheme with stationary frame resonant
current controllers and a PI-SSI DC-link voltage controller
with good result in reducing of the DC-link voltage ripple was
proposed in [19]. However, this solution has problems under
voltage dips operation conditions since the current reference
generator generates a non-zero 3rd harmonic component in the
AC input current. This component is proportionally with the
voltage dip severity.
This paper proposes a new stationary frame control scheme
for three-phase PWM rectifiers under unbalanced voltage dips
conditions. The proposed control scheme regulates the
instantaneous active power at the converter poles (considering
the instantaneous power related to the AC inductors) for
minimizing of input/output harmonics. The novelty consists in
the development of a new current-reference calculation
implemented directly in stationary reference frame. This allows
using P-SSIs controllers for simultaneous compensation of
both positive and negative current sequence components. As
consequence, it results a simplified control scheme with no
need of PLL strategies and rotational transformations. Fast
dynamic performance with small DC-link voltage ripple and
input sinusoidal currents are obtaining with this control scheme
even under severe voltage dips operating conditions. A
comparison with two other control techniques is also
performed. Experimental results are presented for a 20 kVA
AC/DC converter prototype to demonstrate the effectiveness of
the proposed control scheme.
II.
VOLTAGE DIPS
Most of the voltage dips are caused by short-circuit faults;
many of them last only a few tens or hundreds of milliseconds
and are unbalanced (i.e., involve a negative-sequence
component [20]). When a fault occurs at some point in the
power system, the voltage drops until a protection trips to clear
the fault. During this interval, all loads connected to the same
bus as the faulted feeder will be subjected to a voltage dip.
Results from different power quality surveys generally
indicate that the most common voltage dips in three-phase
power systems are of types A, C, and D [20]. For type A
voltage dips, the three-phase voltages are balanced, while the
phase voltages are unbalanced for type C or D voltage dips
(Fig. 2).

Figure 2. Phase voltage phasors before (dotted) and during (solid)

dip of type C and D.

In this paper, the effects of type C unbalance on the

operation of a three-phase PWM AC/DC converter are
considered, although the conclusions can be extended for type
D dips as well. If the PWM rectifier is connected after a
distribution transformer with delta/wye connection, a type C
voltage dip may occur for two situations: (1) at a phase-tophase fault at the secondary side or (2) at a single-line-toground fault in the primary side (seen as phase-to-phase fault at
the secondary side).
III.

PWM AC/DC CONVERTER MODEL UNDER

UNBALANCED OPERATING CONDITIONS
The continuous-time dynamic model of the PWM AC/DC
converter (Fig. 1) can be represented by the following voltage
equation on the AC side:
e = v + L

di
dt

(1)

+ R i

where e , v , i are the vectors representing the AC inputsupply voltages, converter input pole voltages and AC input
currents in stationary reference frame (,), respectively.
It is known that an unbalanced three phase voltage system
without zero sequence can be represented as the sum of
positive and negative sequence components. The vectors
representing the AC input-supply voltages, converter input pole
voltages and AC input currents can be expressed as:
n
n
e = ep + e
= e jt edqp + e jt edq

(2)

n
n
i = ip + i
= e jt idqp + e jt idq

(3)

p
n
n
v = v
+ v
= e jt v dqp + e jt v dq

(4)

n
n
n
where edqp , edq
, i dqp , idq
, v dqp , vdq
are the vectors representing the
positive/negative sequence components of the source voltages,
input currents and converter input pole voltages in PNSRF.

The complex power at the converter poles is:

*
S out = (3 2) v i

)(

n
n
= (3 2) e jt v dqp + e jt vdq
e jt idqp + e jt idq

(5)

After expanding the terms and rearranging the real part of

(5), the instantaneous active power delivered at the converter
poles pout has three terms: DC average Poout , cosine Pcout
2 and
sine Psout
2 at twice the input frequency:
out
Re(S out ) = pout (t ) = Poout + Pcout
2 cos(2t ) + Ps 2 sin(2t ) (6)

IV. CONTROL STRATEGY

The goal of the proposed control strategy is to avoid
harmonics in the DC-link voltage and input AC currents even
under severe unbalanced voltage dip operating conditions. To
achieve this goal, four constrains must be satisfied [16]; these
conditions can be expressed in a set of four linear equations in
PNSRF:

Poin = Pload + Ploss = (3 2) edp idp + eqp iqp + edn idn + eqn iqn (17)

where:

Poout = (3 2 ) vdp idp + vqp iqp + vdn idn + vqn iqn

p n
p n
n p
n p
Pcout
2 = (3 2) vd id + vq iq + vd id + vq iq

(7)

p n
p n
n p
n p
Psout
2 = (3 2 ) v d iq vq id + v q id vd iq

)(

Re(Tout ) = qout (t )

+ Qcout
2

cos(2t )

+ Qsout
2

(10)

where:

p n
p n
n p
n
p
Qcout
2 = (3 2 ) v d iq + v q id vq id + v d iq

p n
p n
n
p
n
p
Qsout
2 = (3 2 ) v d id + v q iq + vd id + v q iq

(12)

(13)
(14)

In the same manner, the average input active power Poin

and the average input reactive power Qoin are obtained as:

(15)

(16)

Poin = (3 2 ) edp idp + eqp iqp + edn idn + eqn iqn

Qoin = (3 2 ) eqp idp edp i qp eqn idn + edn iqn

(20)

average input reactive power Qoin exchanged with the grid

(unity power factor is achieved for k pf = 0 ).
In the proposed control scheme a new current reference
calculation in stationary reference frame is developed. Thus,
(17-20) are transformed in stationary reference frame as:

Poin = Pload + Ploss = (3 2 ) ep ip + ep ip + en in + en i n

Qoin = k pf Poin = (3 2 ) ep ip ep i p e n in + en i n
Pcout
2 =

[(

)(

3
cos 2 t sin 2 t vp in + v p in + vn ip + v n ip
2

)]

(21)

(22)

(23)

(2 sin t cos t ) vp in v p in + vn ip vn ip = 0
Psout
2 =

where Pload is the active power requested by the DC load,

Ploss is the power loss and k pf is a coefficient that imposes the

sin(2t ) (11)

Qoout = (3 2 ) v qp idp vdp iqp v qn idn + v dn i qn

(19)

p n
p n
n
p
n
p
Psout
2 = 0 = (3 2 ) v d iq vq i d + v q id vd iq

After expanding the terms and rearranging the real part of

(10), the instantaneous reactive power delivered at the
converter poles qout has three terms: DC average term Qoout and
harmonic components of twice the input frequency
out
( Qcout
2 , Qs 2 ):
= Qoout

(9)

Thus, a complex power Tout can be defined as:

p n
p n
n
p
n
p
Pcout
2 = 0 = (3 2 ) v d id + vq iq + vd id + v q iq

v
that lag the pole voltages v by 90 electrical degrees [17].

3 *
v i
2
3
n
n
= je jt vdqp + je jt vdq
e jt idqp + e jt idq
2

(8)

The instantaneous reactive power at the converter poles

qout (t ) can be calculated on the basis of a set of voltages

Tout =

Qoin = k pf Poin = (3 2 ) eqp idp edp iqp eqn idn + edn iqn (18)

[(

)(

3
cos 2 t sin 2 t vp i n vp in + v n ip vn i p
(24)
2
p n
p
p n
n
p
n
+ (2 sin t cos t ) v i + v i + v i + v i = 0

)]

out
From (23,24) it results that Pcout
2 and Ps 2 become zero if the
next two conditions are simultaneously satisfied:

vp in + v p in + vn ip + v n i p = 0

(25)

vp in v p in + v n ip vn i p = 0

(26)

Therefore, the new current reference calculation algorithm

can be defined using (21,22), (25,26) in the following matrix
form:

 Poin Pload + Ploss ep

p
in
2 Qoin k pf Po e
=
=

v n
0
3 Pcout
2
out
n
0
v
Ps 2

ep

en

ep

en

v n

vp

e n ip

en ip

(27)
vp in
n
v p i

The current reference values are obtained from (27) as:

ep
ip
p
p
i 2 e
i n = 3 v n

n
vn
i

ep

en

ep

en

vp

e n

en
vp
v p

Pload + Ploss

k pf Poin

i = i + i = k 3 k1 (
p

(28)

3 den (30)

i * = i p + in = k 4 k 2 + (k1 + k 3 ) k pf 2 Poin 3 den (31)

where:

) (

) (

2
2
k1 = ep vp + v p + en v p v n vp vn en vp v n + v p vn (32)

2
2
k 2 = ep vp + v p en vp v n + v p vn + en vp vn v p v n (33)

k 3 = ep vp vn v p v n + ep vp v n + v p vn

en vn + v n

k 4 = ep vp v n + v p vn + e p v p v n vp vn

e n vn + v n

den = k1 e + k 2 e + k 3 e + k 4 e
p

)
)

PI dc
voltage
regulator

vdc

Poin*

Reference
current
generator

*
i

P-SSI
current
regulator

k pf

*
v

S abc

vabc

abc

PWM

i abc

abc

p
n
e
, e

(29)

k 2 + k 4 k pf 2 Poin

*
vdc

PNSCE

eabc

abc

Figure 3. Block diagram of the proposed control scheme.

*
p
n
i
= i
+ i
*

PNSCE

p
n
v
, v

(34)

(35)

(36)

The proposed current reference calculation (30-36) requires

Multiply and Accumulate (MAC) operations that are easily
computed with up-to-date 100150 MIPS fixed point DSPs.
V. PROPOSED CONTROL SCHEME
The block diagram of the proposed control scheme is
shown in Fig. 3. The sequence components of the utility
voltage and converter input pole voltage are obtained using the
Positive/Negative Sequence Component Extraction (PNSCE)
control block. The signals utilized by PNSCE are the measured
source voltages and the converter voltage reference.
There are two possibilities for implementing in stationary
reference frame the PNSCE block: (1) using the Delay Signal
Cancellation ( DSC ) method [21] ; the intrinsic delay time of

5 ms and the zero steady state error properties make this

calculation algorithm a good option for extracting the sequence
components and (2) using the Double Second Order
Generalized Integrator (DSOGI) [22]; this solution is
recommended for a clean current reference generation under
grid voltage harmonic distortion.
The DSOGI has been chosen for the proposed control
scheme to implement the PNSCE block. The proposed control
scheme (Fig. 3) consists of two cascaded control loops: an
outer dc-link voltage control loop and an inner AC input
current control loop. The inner AC input current regulating
loop has two P-SSI regulators (37) implemented in stationary
reference frame. The bandwidth of the current loop is high for
fast tracking of the current reference.
On the other hand, the dc-link voltage controller is usually
designed for optimum regulation and stability. A PI controller
(38) is employed for the DC-link voltage regulation. Its
bandwidth is about 20 times slower than the current controller
bandwidth. The output of the DC-link controller sets the
reference for the average input active power.
H P SSI (s ) = k pi +

2 k ii s
s 2 + 12

H PI (s ) = k pv +

k iv
s

(37)

(38)

A small variation (1 Hz) of the grid voltage frequency has

a minor impact on the P-SSI current regulation. If large
frequency variations ride-through is requested, a frequency
adaptive P-SSI controller may be used [23].
If necessary, the robustness of the current controller against
grid voltage harmonic distortion (mainly fifth and seventh in
three-phase systems) is achieved with a harmonic compensator.
It is easy to extend the capabilities of the scheme by adding
harmonic compensation features simply with more resonant
controllers in parallel to the main controller.
VI. EXPERIMENTAL RESULTS
The proposed control scheme has been compared with two
other control schemes by experimental tests on a 20 kVA
PWM rectifier prototype using a switching frequency of 10
kHz. The rectifier interface inductance, L is equal to 3 mH and
the total estimated source inductance, LS is about 100 H. The
DC-link reference voltage of the IGBT converter has been set

at 700 V and the DC-link capacitance is only 150 F, obtained

with a film capacitor.

TABLE I.

Parameter
Source phase rms voltage
Source inductance
Input resistance
Input boost inductor
DC-link capacitance
Rated DC-link voltage
Switching frequency
Sampling frequency
Fundamental frequency
Load resistance

All control schemes were implemented on the dSPACE

DS1103 development board. The parameters of the system are
given in Table I. The quantities measured from the system
were: the PWM rectifier currents, the PCC line-to-line voltages
and the DC-link voltage. The three control schemes used for
comparison are the following ones:
1) The first control scheme (Fig. 4) uses the current
reference generation via source voltage feedforward (39-42).
This control scheme regulates the Instantaneous Active Power
at the Input stage (IAPI) of the PWM rectifier [10-13].
ep
ip
p
p
i 2 e
=

i n 3 e n

n
en
i

ep

en
p

ep

e n

ep

e n

en
ep
ep

Pload + Ploss

k pf Poin
(39)

) ]

) ]

i* = ip + in = ep en + ep + ep k pf 2 Poin 3 den (40)

i * = i p + i n = e p en ep + ep k pf 2 Poin 3 den (41)

where:
(42)

den = (ep ) 2 + (ep ) 2 (en ) 2 (e n ) 2

2) Second control scheme (Fig. 5) uses the same reference

current generator like the IAPI control scheme, but a PI-SSI
controller is utilized in the DC-link voltage loop to nullify the
2nd harmonic ripple [19] (DC-PI-SSI).

PI dc
voltage
regulator

generator

P-SSI
current
regulator

400

k pf

vdc

300

S abc

vabc

PWM

abc

i abc

abc

p
n
e
, e

PNSCE

Value
230 V
100 H
0.2
3 mH
150 F
700 V
10 kHz
10 kHz
50 Hz
45

The experimental results of the PWM rectifier transient and

steady-state response are shown in Figs. 7,8. It should be noted
that the DC-link voltage in Fig. 8 has been filtered to
emphasize the low frequency harmonics. The transient
response (Fig. 7) shows a fast dynamic response (15 ms of
settling time) of the IAPI control scheme and the proposed
control scheme, meanwhile the DC-PI-SSI control scheme has
a major settling time. From the steady-state performance of all
tested solutions (Fig. 8 and Table II), it can be seen that the
proposed control scheme and the DC-PI-SSI control scheme
exhibit better performance in DC-link voltage ripple
elimination compared with IAPI control scheme. But the DCPI-SSI control scheme draws a distorted AC input current with
6% of the Total Harmonic Distortion (THD), which is five
times bigger when compared with the AC input current THD of
the proposed control scheme.

eabc

abc

Source phase voltages (V)

in* Reference
o
current

Abbr.
E
LS
R
L
Cd
Vdc
fsw
fs
f1
RL

All these control schemes have been implemented in

stationary reference frame using P-SSI current controllers. A
30% type C voltage dip [20] (Fig. 6) has been generated by
means of a 12 kVA programmable voltage source to test the
proposed control scheme and two existing solutions.

3) The proposed control scheme (Fig. 3).

*
dc

EXPERIMENTAL SETUP PARAMETERS

200
100
0
-100
-200
-300

Figure 4. Block diagram of the IAPI control scheme.

-400
-0.05

0.05

0.1

0.15

time (s)
*
vdc

PI-SSI dc
voltage
regulator

vdc

Poin*

Reference
current
generator

*
i

P-SSI
current
regulator

*
v

k pf

S abc

vabc

abc

PWM

i abc

abc

e , e

PNSCE

eabc

Figure 6. Experimental results. Source phase voltages eabc (V) under 30%
type C voltage dip transient.

abc

Figure 5. Block diagram of the DC-PI-SSI control scheme.

TABLE II.

STEADY-STATE OPERATION PERFORMANCE

Control scheme

DC-link voltage ripple

(peak to peak)

THD of input AC
current

IAPI
DC-PI-SSI
Proposed scheme

40 V
13 V
13 V

2%
6%
1.2 %

(a) IAPI

(a) IAPI

(b) DC-PI-SSI

(b) DC-PI-SSI

(c) Proposed scheme

(c) Proposed scheme

Figure 7. Experimental results. Transient response under 30% type C

voltage dip. Traces 1,2,B: converter input currents iabc (A); Trace 3: DC-link
voltage Vdc (V).

Figure 8. Experimental results. Steady-state response under 30% type C

voltage dip. Traces 1,2,B: converter input currents iabc (A); Trace D: DC-link
voltage Vdc (V).

This happens because in the DC-PI-SSI control scheme the

100 Hz resonant term of the DC-link voltage controller
produces a 2nd harmonic output proportionally with the voltage
dip severity. The reference current generator modulates the
DC-link voltage controller output with the fundamental
frequency generating a 3rd harmonic component in the current
reference.

The proposed control scheme exhibits the best performance

in terms of DC link voltage ripple elimination and THD of the
converter inputs currents when compared with the other two
discussed control schemes. The performance difference
becomes higher if the related power of the application is
increasing. That happens due to the impact of the neglected
instantaneous power related to the AC inductors.

[5]

(V)
abc

400

-400
0

0.02

0.04

0.06

0.08

0.1

0.02

0.04

0.06

0.08

0.1

e (V)

400
0

[7]

-400
400

ep

(V)

[6]

[8]

-400
0

0.02

0.04

0.06

0.08

0.1

en

(V)

400

[9]

100
-100
-400

0.02

0.04

0.06

0.08

0.1

time (s)

[10]

Figure 9. Experimental results. Extraction of the source voltage sequence

components under 30% type C voltage dip transient using DSOGI.
From top to bottom: (1) eabc (V); (2) e (V); (3) e p (V); (3) e n (V).
[11]

The extraction of the source voltage sequence components

under 30% type C voltage dip transient using DSOGI is shown
in Fig. 9.
VII. CONCLUSIONS
A new stationary frame control scheme for three-phase
PWM rectifiers operating under unbalanced voltage dips
conditions is proposed in this paper. The proposed control
scheme regulates the instantaneous active power at the
converter poles for minimizing of input/output harmonics. The
novelty consists in the development of a new current-reference
calculation that is directly implemented in stationary reference
frame. This allows using P-SSIs controllers for simultaneous
compensation of both positive and negative current sequence
components. As consequence, no PLL strategies and
coordinate transformations are needed. A comparison with two
different existing control techniques is also performed.
Experimental results are presented for a 20 kVA PWM rectifier
prototype. The experimental results demonstrate that the
proposed control scheme has fast dynamic performance and
yields small DC-link voltage ripple (with only 150 F of DClink film capacitor) and input sinusoidal currents even under
severe voltage dips operating conditions.
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