1

MOOKAMBIGAI COLLEGE OF ENGINEERING

SRINIVASA NAGAR KALAMAVUR
PUDUKOTTAI 622 502.

2013 2014

LAB MANUAL
EC2208 ELECTRONICS CIRCUITS LAB I

INDEX
S.NO DATE

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

NAME OF THE EXPERIMENT

PAGE STAFF
NO
SIGN

CIRCUIT DIAGRAM:

MODEL GRAPH

f1

f2

f (Hz)

EX.NO:

DATE:
FIXED BIAS AMPLIFIER CIRCUIT USING BJT

AIM:
To construct a fixed bias amplifier circuit using BJT and to determine
1. Waveforms at input and output without bias.
2. Determination of bias resistance to locate Q-point at center of load line.
3. Measurement of gain.
4. Plot the frequency response & Determination of Gain Bandwidth Product
APPARATUS REQUIRED:
S.No.
Component
1.
Transistor
2.
Resistor
Capacitor
3.
Regulated power supply
4.
AFO
5.
CRO
6.
Bread Board
7.
Connecting wires & Probes

Range
BC107
600 ,270k
1F
(0-30)V
(0-3)MHz
30 MHz
47F

Quantity
1
1,1
2
1
1
1
1
2

THEORY:
To use a transistor in any application, it is necessary to provide external DC voltages to
operate it in the active region. This process is known as Biasing. The biasing circuit should be
designed to fix the operating point at the centre of the active region. The circuit design should
provide a degree of temperature stability.
In this fixed bias amplifier a high resistance R B is connected between the base and
positive end of supply. The value of RB can be directly found by applying KVL to the input and
output loop. For this reason, this method is called fixed bias method. This fixed biasing circuit is
very simple and biasing conditions can easily be set and also the calculations are very simple.
But it provides very poor stabilization.
PROCEDURE
1. Connections are made as per the circuit diagram.
2. Connect AFO and CRO and set the input voltage as constant.
3. Connect the AFO to the input circuit and CRO to the output circuit . Note down the
input and output waveform with and without bias.
4. Change the frequency of the AFO and note down the corresponding output voltage.
5. Calculate gain=20 log (Vo / Vin)
6. A graph is plotted between frequency and gain.
7. Calculate the gain and gain bandwidth product.

MODEL GRAPH:

DESIGN:

TABULATION:
WITHOUT BIAS
Waveform
Input

Amplitude (in volts)

Time period (in secs)

Amplitude (in volts)

Time period (in secs)

Output

WITH BIAS
Waveform
Input
Output

FREQUENCY RESPONSE OF FIXED BIAS AMPLIFIER

Keep the input voltage constant (Vin) =
Frequency (in Hz)

Output Voltage (in volts)

Gain = 20 log (Vo / Vin) (in dB)

RESULT:
Thus, the Fixed bias amplifier was constructed and the frequency response curve is
plotted.
1. Bias resistance RB = ----------------------------2. Bandwidth = --------------------------------3. Gain band width product = --------------------.

10

CIRCUIT DIAGRAM:
WITH BYPASS CAPACITOR:

WITHOUT BYPASS CAPACITOR:

11

EX.NO:

DATE:
COMMON EMITTER AMPLIFIER USING VOLTAGE DIVIDER BIAS

AIM:
To design and construct BJT Common Emitter Amplifier using voltage divider bias (selfbias ) with and without bypassed resistor and to determine
1. Gain bandwidth product
2. Measurement of gain.
3. Plot the frequency response
APPARATUS REQUIRED:
S.NO

APPARATUS

RANGE

QUANTITY

1.

Transistor

BC107

2.

Capacitor

47 F

4.7 F

1k

5k

58k

12k

4.

Resistor

5.

AFO,CRO

6.

Power supply

7.

Bread board

8.

Connecting wires

1
+ 15V

1
1
As required

and probes
THEORY:
This type of biasing is otherwise called Emitter Biasing. The necessary biasing is
provided using 3 resistors: R1, R2 and Re. The resistors R1 and R2 act as a potential divider and
give a fixed voltage to the base. If the collector current increases due to change in temperature or
change in , the emitter current I e also increases and the voltage drop across Re increases,
reducing the voltage difference between the base and the emitter. Due to

12

MODEL GRAPH:

TABULATION:
WITH BYPASS CAPACITOR:
Keep the input voltage constant, Vin =
Frequency (in Hz)

Output Voltage (in volts)

Gain= 20 log(Vo/Vin) (in dB)

13

reduction in Vbe, base current Ib and hence collector current Ic also reduces. This reduction in
Vbe, base current Ib and hence collector current Ic also reduces. This reduction in the collector
current compensates for the original change in I c.
The stability factor S= (1+) * ((1/ (1+)). To have better stability, we must keep R b/Re
as small as possible. Hence the value of R1 R2 must be small. If the ratio Rb/Re is kept fixed, S
increases with .
DESIGN:

14

WITHOUT BYPASS CAPACITOR:

Keep the input voltage constant, Vin =
Frequency (in Hz)

Output Voltage (in volts)

Gain= 20 log(Vo/Vin) (in dB)

15

16

17

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Connect the AFO and CRO and set the input voltage as constant.
3. Connect the AFO to the input circuit and CRO to the output circuit and note down the input
and output waveforms with and without bypassed emitter capacitor.
4. Change the frequency of the AFO and note down the corresponding output voltage.
5. Calculate the gain of the amplifier..
6. Plot the frequency response curve and draw the upper and lower cut off frequencies.
7.Calculate gain, gain bandwidth product.

RESULT:
Thus the frequency response of common emitter amplifier using voltage divider bias was
plotted.
With bypass capacitor
1. Bandwidth = -------------------2. Gain Bandwidth product = -----------Without bypass capacitor
1. Bandwidth = -------------------2. Gain Bandwidth product = ------------

18

CIRCUIT DIAGRAM:

MODEL GRAPH:

f1

f2

f (Hz)

19

EX.NO:

DATE:
COMMON COLLECTOR AMPLIFIER USING SELF BIAS

AIM:
Design and construct BJT Common Collector Amplifier using voltage divider bias (selfbias).
1. Measurement of gain.
2. Plot the frequency response & Determination of Gain Bandwidth Product
APPARATUS REQUIRED:

S.No.
Component
1.
Transistor
2.
Resistor

3.
4.
5.
6.
7.
8.

Capacitor
Regulated power supply
AFO
CRO
Bread Board
Connecting wires & Probes

Range
BC107
10k
8k
6k
4.7F
(0-30)V
(0-3)MHz
30 MHz

Quantity
1
1
1
1
2
1
1
1
1
As required

THEORY:
The d.c biasing in common collector is provided by R1, R2 and RE .The load resistance
is capacitor coupled to the emitter terminal of the transistor.
When a signal is applied to the base of the transistor ,V B is increased and decreased
as the signal goes positive and negative, respectively. Considering V BE is constant the variation
in the VB appears at the emitter and emitter voltage VE will vary same as base voltage VB . Since
the emitter is output terminal, it can be noted that the output voltage from a common collector
circuit is the same as its input voltage. Hence the common collector circuit is also known as an
emitter follower.
PROCEDURE
1. Connections are made as per the circuit diagram.
2. Connect AFO and CRO and set the input voltage as constant.
3. Connect the AFO to the input circuit and CRO to the output circuit . Note down the
input and output waveform with and without bias.
4. Change the frequency of the AFO and note down the corresponding output voltage.
5. Calculate gain=20 log (Vo / Vin)
6. A graph is plotted between frequency and gain.
7. Calculate the gain and gain bandwidth product.

20

TABULATION:
Keep the input voltage constant, Vin =
Frequency (in Hz)

Output Voltage (in volts)

Gain= 20 log(Vo/Vin) (in dB)

21

DESIGN:

22

23

RESULT:
Thus, the Fixed bias amplifier was constructed and the frequency response curve is
plotted.
1. Bias resistance RB = ----------------------------2. Bandwidth = --------------------------------3. Gain band width product = --------------------.

24

CIRCUIT DIAGRAM:

MODEL GRAPH:

f1

f2

f (Hz)

25

EX.NO:

DATE:
DARLINGTON AMPLIFIER USING BJT

AIM:
To construct a BJT Darlington amplifier and to determine
1. Determination of input resistance.
2. Measurement of gain.
3. Plot the frequency response & Determination of Gain Bandwidth Product
APPARATUS REQUIRED:
S.No.
1.
2.

3.
4.
5.
6.
7.
8.

Component
Transistor
Resistor

Capacitor
Regulated power supply
AFO
CRO
Bread Board
Connecting wires & Probes

Range
BC107
11 k
6.2k
13k
0.1F
(0-30)V
(0-3)MHz
30MHz

Quantity
2
1
1
1
2
1
1
1
1
As required

THEORY:
In Darlington connection of transistors, emitter of the first transistor is directly
connected to the base of the second transistor .Because of direct coupling dc output current of
the first stage is (1+hfe )Ib1.If Darlington connection for n transitor is considered, then due to
direct coupling the dc output current foe last stage is (1+hfe )

times

Ib1 .Due to very large

amplification factor even two stage Darlington connection has large output current and output
stage may have to be a power stage. As the power amplifiers are not used in the amplifier circuits
it is not possible to use more than two transistors in the Darlington connection.
In Darlington transistor connection, the leakage current of the first transistor is amplified
by the second transistor and overall leakage current may be high, Which is not desired.

26

FREQUENCY RESPONSE OF DARLINGTON AMPLIFIER

Keep the input voltage constant (Vin) =
Frequency (in Hz)

Output Voltage (in volts)

Gain = 20 log (Vo / Vin) (in dB)

27

PROCEDURE
1. Connect the circuit as per the circuit diagram.
2. Set Vi =2V, using the signal generator.
3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1M Hz in regular steps of
10 and note down the corresponding output voltage.
4. Plot the graph; Gain (dB) vs Frequency(Hz).
5. Find the input and output impedance.
6. Calculate the bandwidth from the graph.
7. Note down the phase angle, bandwidth, input and output impedance.

PROCEDURE TO FIND INPUT & OUTPUT IMPEDANCE:

1. Switch off the power supply.

2. Connect a decade resistance box (DRB) between input voltage source and the base of the
transistor ( series connection ).
3. Connect ac voltmeter (0-100mV) across the biasing resistor R2.
4. Vary the value of DRB such that the ac voltmeter reads the voltage half of the input signal.
5. Note down the resistance of the DRB which is the input impedance.
6. The same procedure is repeated on the output side to find the output impedance.

28

CIRCUIT TO FIND INPUT IMPEDANCE:

29

RESULT:

Thus, the Darlington amplifier using BJT was constructed and the frequency response
curve was plotted.
1. Bandwidth = ----------------------------2. Gain Bandwidth Product = ------------------------------3.Input resistance = -------------------

30

CIRCUIT DIAGRAM

MODEL GRAPH:

f1

f2

f (Hz)

31

EX.NO:

DATE:

SOURCE FOLLOWER WITH BOOT STRAPPED GATE RESISTANCE

AIM:
To construct a source follower with boot strapped gate resistance and to determine
1. Determination of input and output resistance with and without bootstrapping.
2. Measurement of gain.
3. Plot the frequency response & Determination of Gain Bandwidth Product
APPARATUS REQUIRED:
S.No.
Component
1.
Transistor
2.
Resistor
3.
4.
5.
6.
7.
8.

Capacitor
Regulated power supply
AFO
CRO
Bread Board
Connecting wires &
Probes

Range
BFW10
100k
1k
1F
(0-30)V
(0-3)MHz
30 MHz

Quantity
1
1
2
2
1
1
1
1

47F

THEORY:
Source follower is similar to the emitter follower (the output source voltage follow the
gate input voltage), the circuit has a voltage gain of less than unity, no phase reversal, high input
impedance, low output impedance. Here the Bootstrapping is used to increase the input
resistance by connecting a resistance in between gate and source terminals. The resister R A is
required to develop the necessary bias for the gate.
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. The waveforms at the input and output are observed for cascade operations by
varying the input frequency.
3. The biasing resistances needed to locate the Q-point are determined.
4. Set the input voltage as 1V and by varying the frequency, note the output voltage.
5. Calculate gain=20 log (Vo / Vin.)
6. A graph is plotted between frequency and gain.

32

TABULATION:
Keep the input voltage constant (Vin) =
Frequency (in Hz)

Output Voltage (in volts)

Gain = 20 log (Vo / Vin) (in dB)

33

PROCEDURE TO FIND INPUT & OUTPUT IMPEDANCE:

1. Switch off the power supply.

2. Connect a decade resistance box (DRB) between input voltage source and the base of the
transistor ( series connection ).
3. Connect ac voltmeter (0-100mV) across the biasing resistor R2.
4. Vary the value of DRB such that the ac voltmeter reads the voltage half of the input signal.
5. Note down the resistance of the DRB which is the input impedance.
6. The same procedure is repeated on the output side to find the output impedance.

34

CIRCUIT DIAGRAM TO FIND INPUT IMPEDANCE:

35

RESULT:
Thus, the source follower with bootstrapped gate resistance was constructed and the
frequency response curve is plotted.
1. Bandwidth = ----------------------------2. Gain Bandwidth Product = ------------------------------WITH BOOTSTRAPPING
1. Input impedance = ------------------2. Output impedance = ------------------------WITHOUT BOOTSTRAPPING
1. Input impedance = ------------------2. Output impedance = -------------------------

36

CIRCUIT DIAGRAM:
DIFFERENTIAL MODE:

COMMON MODE:

37

EX.NO:

DATE:
DIFFERENTIAL AMPLIFIER USING BJT

AIM:
To construct and test the differential amplifier using BJT and measure CMRR
APPARATUS REQUIRED:
S.NO
1.
2.
3.
4.
5.
6.
7.

APPARATUS
Transistor
Resistor
AFO
CRO
Power supply
Bread Board
Connecting
Wires.

RANGE
SL100
10k
(0-30)V
-

QUANTITY
1
5
1
1
1
1
As required

THEORY:
The differential amplifier is a basic stage of an integrated operational amplifier. It is used
to amplify the difference between 2 signals. It has excellent stability, high versatility and
immunity to noise. In a practical differential amplifier, the output depends not only upon the
difference of the 2 signals but also depends upon the common mode signal.
Transistor Q1 and Q2 have matched characteristics. The values of R C1 and RC2 are equal.
Re1 and Re2 are also equal and this differential amplifier is called emitter coupled differential
amplifier. The output is taken between the two output terminals.
For the differential mode operation the input is taken from two different sources and the common
mode operation the applied signals are taken from the same source
Common Mode Rejection Ratio (CMRR) is an important parameter of the differential
amplifier. CMRR is defined as the ratio of the differential mode gain, Ad to the common mode
gain, Ac.
CMRR = Ad / Ac
In ideal cases, the value of CMRR is very high.
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. The base terminals of the transistor are grounded the output v1 and v2 are measured with
respect to ground.
3. Vs1 is adjusted to 40mV at signal frequency of 1 KHz and base of Q2 is
grounded
the output voltage is measured and difference mode gain is measured.
Ad =V1 V2/ Vin
Vs1 and Vs2 are made to be the same value and output voltages are measured and common mode
signal is called CMRR= Ad / Ac

38

MODEL GRAPH:

39

TABULATION:
Amplitude in volts

Time in ms

Input
signal

DIFFERENTIAL MODE:
Amplitude in volts

Time in ms

Amplitude in volts

Time in ms

V01
V02
COMMON MODE:

V01
V02

40

CALCULATION:

41

RESULT:
Thus the CMRR of the differential amplifier was measured.
CMRR = ---------CMRR in dB = ---------------------.

42

CIRCUIT DIAGRAM:

MODEL GRAPH:

f1

f2

f (Hz)

43

EX.NO:

DATE:
CLASS A POWER AMPLIFIER

AIM:
To construct a Class A power amplifier and to
1. Observe the output voltage and to determine the output voltage
2. Compute maximum output power and efficiency.
APPARATUS REQUIRED:
S.No.
1.
2.
3.
4.
5.
6.
7.
8.
9.

Component
Transistor
Resistor
Capacitor
Ammeter
Regulated power supply
AFO
CRO
Bread Board
Connecting wires & Probes

Range
SL100
1K ,2k
0.01F, 10F
0-10mA
(0-30)V
(0-3)MHz
30MHz

Quantity
1
1,1
1,1
1
1
1
1
1
As required

THEORY:
The power amplifier is said to be Class A amplifier if the Q point and the input signal
are selected such that the output signal is obtained for a full input signal cycle. For all values of
input signal, the transistor remains in the active region and never enters into cut-off or saturation
region. When an a.c signal is applied, the collector voltage varies sinusoidally hence the collector
current also varies sinusoidally.The collector current flows for 360 0 (full cycle) of the input
signal. i e the angle of the collector current flow is 3600 .

PROCEDURE
1. Connect the circuit as per the circuit diagram.
2. Set Vi =20 mv, using the signal generator.
3. Setting the input voltage constant, vary the frequency from 10 Hz to 1M Hz in regular steps
and note down the corresponding output voltage.
4. Plot the graph; Gain (dB) vs Frequency (Hz).
5. Calculate maximum output power and efficiency

44

INPUT SIGNAL

OUTPUT SIGNAL

TABULATION:
Waveform
Input
Output

Amplitude (in volts)

Time period (in secs)

45

FREQUENCY RESPONSE
Keep the input voltage constant (Vin) =
Frequency (in Hz)

Output Voltage (in volts)

Gain = 20 log (Vo / Vin) (in dB)

46

47

RESULT:
Thus, the class A amplifier was constructed and the frequency response curve was
plotted.
1. Bandwidth = ----------------------------2. Gain Bandwidth Product = ------------------------------3. Efficiency - -----------------

48

CIRCUIT DIAGRAM

MODIFICATION OF CIRCUIT TO ELIMINATE CROSS OVER DISTORTION

49

EX.NO:

DATE:
CLASS B COMPLEMENTARY SYMMETRY AMPLIFIER

AIM:
To construct a class B complementary symmetry amplifier and to
1. observe output waveform with and without cross over distortion
2. Calculate maximum output power and efficiency
APPARATUS REQUIRED:
S.No.

Component

1.

Transistor

2.
3.
4.
5.
6.
7.

Resistor
Capacitor
Regulated power supply
AFO
CRO
Bread Board

8.

Connecting wires & Probes

Range
2N3906
2N3904
10K ,1k
10F,22 F
(0-30)V
(0-3)MHz
30MHz

Quantity
1
1
1,1
1,1
1
1
1
1
As required

THEORY:
A power amplifier is said to be Class B amplifier if the Q-point and the input signal are
selected such that the output signal is obtained only for one half cycle for a full input cycle. The
Q-point is selected on the X-axis. Hence, the transistor remains in the active region only for the
positive half of the input signal.
There are two types of Class B power amplifiers: Push Pull amplifier and complementary
symmetry amplifier. In the complementary symmetry amplifier, one n-p-n and another p-n-p
transistor is used. The matched pair of transistor are used in the common collector configuration.
In the positive half cycle of the input signal, the n-p-n transistor is driven into active region and
starts conducting and in negative half cycle, the p-n-p transistor is driven into conduction.
However there is a period between the crossing of the half cycles of the input signals, for which
none of the transistor is active and output, is zero
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Connect the function generator to input circuit and CRO to the output circuit.
3. Note down the input and output readings
4. Change the frequency value and note down the corresponding output voltage
5. Plot the graph for obtained readings

50

MODEL GRAPH

51

TABULATION:
Waveform

Input

Output
(with cross over
distortion)
Output
(without cross over
distortion)

Amplitude (in volts)

Time period (in secs)

52

CALCULATION:

53

RESULT:
Thus, the Darlington amplifier using BJT was constructed and the frequency response
curve was plotted.
1. Bandwidth = ----------------------------2. Gain Bandwidth Product = -------------------------------

54

CIRCUIT DIAGRAM:
WITH FILTER:

WITHOUT FILTER:

MODEL GRAPH:

55

EX.NO:

DATE:
HALF WAVE RECTIFIER

AIM:
To construct a half wave rectifier and to
1.Measure DC voltage under load &ripple factor, Comparison with calculated values.
2. Plot the Load regulation characteristics using Zener diode.
APPARATUS REQUIRED:
S.No
1.
2.
3.
4.
5.
6.
7.
8.
9.

Apparatus
Diode
Zener Diode
Transformer
Capacitor
Ammeter
Voltmeter
DRB
Bread Board
Connecting Wires

Range
IN4007
Z 5.1v
6-0-6 v
100F
(0-500)mA
(0-30)v
-

Quantity
1
1
1
1
1
1
1
1
As required

THEORY:
A rectifier is a circuit, which uses one or more diodes to convert A.C voltage into D.C
voltage. In this rectifier during the positive half cycle of the A.C input voltage, the diode is
forward biased and conducts for all voltages greater than the offset voltage of the semiconductor
material used. The voltage produced across the load resistor has same shape as that of the
positive input half cycle of A.C input voltage.
During the negative half cycle, the diode is reverse biased and it does not conduct. So
there is no current flow or voltage drop across load resistor. The net result is that only the
positive half cycle of the input voltage appears at the output.
PROCEDURE:
1.The connections are made as per the circuit diagram.
2.The primary side of the transformer is given as input of the rectifier.
3.By connecting CRO probe terminal at the end of the resistor in the rectifier circuit.
4.Ripple free output is obtained by connecting capacitor and rectifier.
5.A graph is plotted with filter and without filter.

56

MODEL GRAPH:

57

TABULATION:

Load in

S.No

Output voltage(v) Current (mA)

CALCULATION:

Waveform
Input
Output
(with filter)
Output
(without filter)

Amplitude (in volts)

Time period (in secs)

58

59

RESULT:
Thus the half wave rectifier was constructed and its input and output waveforms are
drawn. The ripple factor of capacitive filter is calculated as
Theoretical Ripple factor = -----------Practical Ripple factor = --------------Regulation = ------------------

60

CIRCUIT DIAGRAM:

WITH FILTER:

WITHOUT FILTER:

61

EX.NO:

DATE:
FULL WAVE RECTIFIER

AIM:
To construct a full wave rectifier and to
1.Measure DC voltage under load &ripple factor, Comparison with calculated values.
2. Plot the Load regulation characteristics.
APPARATUS REQUIRED:
S.No
1.
2.
3.
4.
5.
6.
7.
8.

Apparatus
Diode
Transformer
Capacitor
Ammeter
Voltmeter
DRB
Bread Board
Connecting Wires

Range
IN4007
6-0-6 v
100F
(0-500)mA
(0-30)v
-

Quantity
1
1
1
1
1
1
1
As required

THEORY:
The full wave rectifier conducts for both the positive and negative half cycles of the input
ac supply. In order to rectify both the half cycles of the ac input, two diodes are used in this
circuit. The diodes feed a common load RL with the help of a centre tapped transformer. The ac
voltage is applied through a suitable power transformer with proper turns ratio. The rectifiers
dc output is obtained across the load.
The dc load current for the full wave rectifier is twice that of the half wave rectifier. The
lowest ripple factor is twice that of the full wave rectifier. The efficiency of full wave
rectification is twice that of half wave rectification. The ripple factor also for the full wave
rectifier is less compared to the half wave rectifier.
PROCEDURE:
1.The connections are made as per the circuit diagram.
2.The primary side of the transformer is given as input of the rectifier.
3.By connecting CRO probe terminal at the end of the resistor in the rectifier circuit.
4.Ripple free output is obtained by connecting capacitor and rectifier.
5.A graph is plotted with filter and without filter.
6.Note the regulation by changing the load resistance and note down the voltage to
corresponding ammeter value.

62

MODEL GRAPH:

63

TABULATION:

S.No

Load in

Waveform
Input
Output
(with filter)
Output
(without filter)

Output voltage(v)

Amplitude (in volts)

Current (mA)

Time period (in secs)

64

CALCULATION:

65

RESULT:
Thus the full wave rectifier was constructed and its input and output waveforms are
drawn. The ripple factor of capacitive filter is calculated as
Theoretical Ripple factor = -----------Practical Ripple factor = --------------Regulation = ------------------

66

67

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