USING ALLEGRO PCB SI TO ANALYZE A BOARDS

POWER DELIVERY SYSTEM FROM POWER SOURCE TO

DIE PAD.

Juergen Flamm, Cadence Design Systems

Todays high speed circuits are challenging in almost every design aspect. One of
these challenges is to provide the needed clean power signals to the devices inside
their packages while they are mounted on a printed circuit board. This paper will
illustrate how you may utilize Allegro PCB PI (SQPI) and Allegro PCB SI
Simultaneous Switching Noise (SSN) to analyze a boards power
delivery system, starting with the power source (voltage regulator module/power
supply) and ending inside the package at the dies power and ground pads.
In the following example we will use a completed design to show how Allegro PCB PI (SQPI) and Allegro PCB SI SSN may be used to
analyze the power delivery system of an existing board. It should be highlighted that the tools and techniques utilized and described
as follows, should be proactively applied to derive rules for designing a boards power delivery system such, that post layout
verification simply becomes a checking function.
HOW TO GET INSIGHT INTO A POWER DELIVERY SYSTEM ON A COMPLETED BOARD
The following three steps are suggested in order to analyze the power delivery path from the power source to a dies power and
ground pads inside its package.
ALLEGRO PCB PI (SQPI): Utilize Allegro PCB PI in the first step to determine the source impedance present at the power and
ground supply points of a board in the area where a device is connected to power and ground. Knowing the source impedance as a

function of frequency, we can, along with knowing the switching current drawn by the device at various frequencies, determine the
power and ground bounce levels seen at the supply points of the device. This will be done utilizing frequency domain analysis.
SSN: Utilize SSN in the second step to determine the power and ground bounce levels present at a dies power and ground pads.
The power and ground bounce levels are determined by the voltage drop created by the current flowing in the interconnecting
structures. We therefore have to include in the simulation the parasitic elements of the power and ground nets associated with
interconnecting the power and ground planes and the respective power and ground die pads (board traces and vias as well as
package pins, traces, vias and bond wires). This will be done utilizing time domain analysis.
Combining the results of Allegro PCB PI (SQPI) and SSN: Combining the results of the two first steps will provide an assessment
of the situation and if problems are discovered, will allow the development and implementation of appropriate corrective measures
(I/O buffer redesign or package redesign or board redesign or different capacitor selection or TBD or any combination of the above).

EXAMPLE FOR ANALYZING THE POWER DELIVERY SYSTEM

Step 1 using Allegro PCB PI
The following assumptions are made:
The reader is familiar with the basic operation of the Allegro PCB SI and Allegro PCB PI (SQPI) tools.
The Allegro PCB Editor board file is available.
The component models needed for simulation are available.
We open the board file in Allegro PCB SI and prepare the database for simulation by using the Setup Advisor
from within Allegro PCB SI in the known fashion.

After this step is complete, we open power integrity and complete all steps of the Allegro PCB PI (SQPI) Setup Wizard needed to
prepare the design for power integrity simulations. In the last step, the library setup, we select one capacitor from the standard
libraries provided with the tool installation. This is necessary for the setup wizard to complete successfully, as the capacitors listed
under the board folder are not ready to be used yet. We will prepare them for simulation in the following steps.

In the Power Integrity Design & Analysis window we select Report. Besides other information about the board, this will give us the
information about the capacitor device types and the reference designators used. This information is needed in the next step, where
we assign the required models to the capacitors in the board.

We ok the Power Integrity Design & Analysis window to close it for now and open the Signal Model Assignment window. Here we
change the model assignment for the targeted capacitor types used for power decoupling from ESpiceDevice to the appropriate
dielectric type, size and value ESpiceDevice:Capacitor as required for Allegro PCB PI simulations (use Find Model ).
The previously generated report will help to identify the necessary capacitor types.

We can now open Power Integrity, go to the Cap. Library and select the appropriate capacitor types in the board folder. Dont forget to
deselect the capacitor we had selected in a previous step. It is no longer needed. Ok the Power Integrity Capacitor Library Setup
window to close it. We should now see the list of capacitor types used in the board in the Power Integrity Design & Analysis window.

Note: If we set the multipliers in the Multiplier column to zero, the Number to Create column will show the number of capacitors of
each type used in the board as a negative and red number.

If desired, we could now use the features provided by the tool to edit the capacitor models as needed. No adjustments are made in
this example. The default models are used.
The board shown in the following Picture 1 was prepared as briefly outlined above.

Figure1: Board file with outline

The outlines of the 3.3V plane and Ground plane segments are shown in Figure 1. In the board design, a local regulator provides the
3.3 Volt power. The VRM was placed where the local regulator feeds the 3.3V/Gnd plane pair. The noise source was placed in the
center of the load device (U1) and is associated with the selected plane pair.

The switching current for the noise source will first be estimated using a lumped model and the following assumptions:

In the system application, each device pin is driving a capacitive load of approximately C=15pF. Switching time is about DeltaT=1nsec
with a voltage change of DeltaV=3.3V. For 64 simultaneously switching pins, we can calculate the following current estimate:

Iswitch = 64 x (C x DeltaV)/DeltaT = 3.2A

This switching current is added to the estimated device internally required switching current (core current) of about 0.8A to yield 4.0A.

Note: This is just one of several ways of estimating the switching load current. Please see step 2 ( SSN) for an example of a
distributed model approach to derive switching current. If you have a better way, please use it instead.

A multimode simulation was run, which yielded the results shown in Figure 2.

Figure2: Source impedance as a function of frequency and grid location.

The switching frequency for this application is 100Mhz. A vertical marker is placed accordingly in Figure2. The example grid location
indicated in Figure1 corresponds to the source impedance curve highlighted in Figure2. We observe that the source impedance,
specifically at 100MHz, for this grid location is about 200mOhms. Further examination uncovers that all grid locations, where the
power pins of U1 are connected to the plane, exhibit similar source impedance levels. This is noticeably higher than the required
target impedance needed to meet the voltage ripple requirements. The ripple tolerance is assumed to be 5% of 3.3V, which at 4A of
switching current leads to the target impedance of 41.25mOhm.

Based on approximately 200mOhms of source impedance at 100MHz and the estimated 4A of switching current, we would expect
around 800mV of supply ripple.

This quickly achieved result correlates well with the time domain measurements taken on the board in the lab. The result clearly
highlights the value of the Allegro PCB PI tool for post layout analysis and even more so when
used as a design tool to determine layout rules and constraints in the pre-layout phase of a board.

Additionally it should be highlighted that if this bus carried data patterns such that simultaneous switching would occur around 10MHz,
one would expect to observe a similarly high level of ripple due to the source impedance exhibiting a high value around this frequency
region as well.

Now that we have an idea of the magnitude of the power delivery systems characteristic source impedance at the location of U1, the
next step would be to examine what the path from the power and ground planes to the power and ground die pads inside the package
of U1 will contribute to power and ground bounce.

Step 2 using SSN

Next we assess the effects of the parasitic elements associated with the interconnections between the power/ground planes and the
dies power/ground pads inside the package of U1.The parasitic lumped elements of the power and ground connections inside the
package of U1 are defined as pin parasitic R, C, L values in the device model for each pin as shown in Figure 3 below. A large
package model could be used instead, which would also allow coupling between nets.

Figure 3: Device model pin parasitics

The device model is prepared such that the appropriate 3.3V power pins are assigned to the power bus pci_ad_pwr and the
appropriate ground pins are assigned to the ground bus pci_ad_gnd. All pins associated with the 64 bits of the nets PCI_AD0063
are assigned to the above power and ground busses (see Figures 4, 5 and 6 below).

Figure 4: Power bus assignment to package power pins

Figure 5: Ground bus assignment to package ground pins

Figure 6: Net assignment to power bus and ground bus

From Allegro PCB SI we open probe and select net PCI_AD00 with pin U1-N2 as the active driver.

We open Waveform, select SSN, select the frequency in Preferences to 100MHz and choose Create Waveforms. The simulation
starts switching all 64 drivers simultaneously. As intended by SSN simulations with all associated drivers sharing the same power and
ground buses, the voltage waveforms generated by the switching currents flowing in the power and ground nodes are generated and
are displayed in Figure 7.

Net PCI_AD00 can also be extracted into Allegro PCB SI 210 (Signal Explorer), where we can add a current probe to the topology.
This will allow us to obtain a reading of the drivers output current wave form and the peak output switching current.

We may obtain a measure of the representative nets (PCI_AD00) switching current spectral distribution by utilizing the EMI single net
simulation capability of Allegro PCB SI. We have to choose the appropriate settings within the preferences menu
for EMI (Compute current distribution in the General tab of the Advanced Preferences) and run a simulation. Knowing the spectral
distribution of the switching current is very helpful when deciding on an appropriate frequency domain characteristic of the target
impedance.

Example results are displayed in the following Figures:

Figure 8 shows the topology of the extracted net PCI_AD00.

Figure 9 shows the switching current waveform of net PCI_AD00.
Figure 10 shows the spectral distribution of the switching current of net PCI_AD00.
Figure 11 shows the switching voltage waveform of the driver on pin N2 of U1.

The drivers switching times are confirmed to be around 1nsec, as assumed in step 1.
The peak current value is about 25mA, which amounts to roughly 1.6A for 64 bits.
To compare this with the estimated switching current used for Step 1, we have to account for the off board loads to be driven as well.
A lengthened transmission line model of TL1 in Figure8 was used to emulate the off board traces and loads. For additional 5 inches of
load trace, the peak current increases to roughly 50mA, resulting in a total value of 3.2A. If we now add the 0.8A of estimated U1
internal switching current we arrive at 4A, the switching current used in step1.

Figure 7: Power and ground bounce waveforms

Looking at the magnitude of the waveform excursions in Figure 6 and knowing that due to the not included off board loads the current
levels are higher than in the simulation leading to the results in Figure 6, we may conclude that the power quality at the die pads is
insufficient. We will soon find out that the parasitic elements of the package are dominating in this case.
Instead of using the lumped element package model, we could explore the possibility of using the actual package file and create a
system design link between the board and U1, which would lead to an even better model. However, the capabilities and value of the
tool for design and analysis work should be apparent.

Note: For the extraction of the boards parasitic elements (pwr/gnd vias and traces), acting between the power/ground plane pair and
the package power/ground pins to be functional you need version 14-2-57CZ or later of the 14.2 release software.

Figure 8: Net PCI_AD00 topology with current probe

Figure 9: Driver output current waveform

Figure 10: Driver output current spectral distribution

Figure 11: Driver output voltage waveform

Combining the results of Allegro PCB PI (SQPI) and SSN

It now is a relatively easy task to combine the results of step1 and step2 and draw the necessary conclusions to what would have to
be the next step to correct any potentially discovered problems.

In an attempt to combine step 1 and step2, we will first approximate the plane pairs source impedance for the grids of interest. This is
the area where U1 is connected to power and ground. We then add the equivalent parasitic elements to the associated power and
ground pins of the device model and repeat SSN simulations.

In a first order impedance approximation, we will neglect the impedance peak around 10Mhz (see Figure 2), as we are only analyzing
the power signal content at the 100MHz fundamental frequency and the higher harmonics. For simplicity we may assume a first order
model comprised of a resistor in series with an inductor.

For the equivalent resistor we can assume a value of

R = 40 mOhm.

As the impedance above approximately 20MHz exhibits almost pure inductive behavior (linearly increases with frequency), we may
calculate the equivalent inductors value to

L = 200mOhm/(2*3.14*100Mhz) = 0.32nH.

An easy way of adding the above plane model parameters is to simply include half of the value of R (20mOhm) and half of the value
of L (0.16nH) in the pin parasitic values of all associated power and ground pins of the device model. As mentioned earlier, another
way to include the plane pairs approximated source impedance for simulation would be to generate a separate large package model,
which would include the parasitic elements of the plane pairs source impedance model.

One could go as far as to think about adding capability to the tool to synthesize a model from the simulation data, or ideally combine
the plane models netlist with the netlist created for SSN.

In this case we update the device model as mentioned first and repeat the simulation. The results are shown in Figure 12 below.
Almost no differences can be observed in the resulting power, ground and signal waveforms. This leads us to the conclusion that the
parasitic elements of the package are dominating in this case and corrective actions should be directed towards improving the
package power distribution schema.

Figure 12: SSN with and without plane model parasitic elements

To evaluate the impact of power and ground bounce on a signals waveform quality and timing characteristic, we can conduct a
baseline reflection simulation and run a SSN simulation for comparison.

The results of an example simulation are given below. Figure 13 shows driver (dotted black) and receiver (dotted green) waveforms
for a reflection simulation run, where power and ground bounce effects are not taken into consideration.

The driver and receiver waveforms (solid black and solid green lines) look different when power (solid red waveform) and ground
(solid blue waveform) bounce effects are included in the SSN simulation. As mentioned before, here we may not only study the power
and ground bounce effects themselves, but also their influence on signal integrity and signal timing, which is crucial in applications
with critical timing requirements.

Figure 13: Comparison between reflection simulation (dotted lines) and SSN simulation (solid lines).

SUMMARY

We briefly demonstrated how Allegro PCB SI may be utilized to assist in performing post layout analysis of a
power distribution system in a circuit board. We used a three-step approach, where a plane structures source impedance was
evaluated in the frequency domain using Allegro PCB PI (SQPI) and the effects of the interconnect between the power and ground
plane structures and a dies power and ground pads were evaluated in the time domain using Allegro PCB SI SSN with incorporated
results from the Allegro PCB PI simulation.

We briefly touched on how to use Allegro PCB SI to analyze a waveforms signal integrity and timing behavior taking power and
ground bounce effects into consideration.

Finally, it should be highlighted that the presented approach, simulation and modeling features of the Allegro PCB SI family of tools
are ideally used for pre layout solution space analysis in order to derive design rules for the board design and layout. This proactive
design approach will assure that post layout verification simply becomes a trouble free checking operation.

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