NuMicro Nano100 (B) Series Product Brief en V1.00

NuMicro Nano100 (B) Series Product Brief
NuMicro Family
Nano100 Series Product Brief
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com
NUMICRO NANO100 TECHNICAL REFERENCE MANUAL
The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Table of Contents
LIST OF FIGURES ........................................................................................................................... 4
LIST OF TABLES ............................................................................................................................. 5
1
GENERAL DESCRIPTION ..................................................................................................... 6
2
FEATURES ............................................................................................................................. 8
2.1
Nano100 Features Base Line ................................................................................... 8
2.2
Nano110 Features LCD Line .................................................................................. 14
2.3
Nano120 Features USB Connectivity Line ............................................................. 20
2.4
Nano130 Features Advanced Line.......................................................................... 26
PARTS INFORMATION LIST AND PIN CONFIGURATION ................................................ 32

3.1
NuMicro Nano100 Series Selection Code ............................................................... 32
3.2
NuMicro Nano100 Products Selection Guide .......................................................... 33
3.3
3.2.1
NuMicro Nano100 Base Line Selection Guide............................................................. 33
3.2.2
NuMicro Nano110 LCD Line Selection Guide.............................................................. 33
3.2.3
NuMicro Nano120 USB Connectivity Line Selection Guide ......................................... 33
3.2.4
NuMicro Nano130 Advanced Line Selection Guide ..................................................... 33
Pin Configuration ........................................................................................................ 34

3.3.1
NuMicro Nano100 Pin Diagrams ................................................................................. 34
3.3.2
3.3.3
3.3.4
BLOCK DIAGRAM ................................................................................................................ 44

4.1
Nano100 Block Diagram ............................................................................................ 44
4.2
4.3
4.4
APPLICATION CIRCUIT ....................................................................................................... 48

5.1
LCD Charge Pump ..................................................................................................... 48
5.1.1
5.1.2
5.2
ADC Application Circuit .............................................................................................. 49

5.2.1
5.3
6
7
Voltage Reference Source ............................................................................................. 49
DAC Application Circuit .............................................................................................. 51

5.3.1
5.4
C-type 1/3 Bias ............................................................................................................... 48

C-type 1/2 Bias ............................................................................................................... 48
Voltage Reference Source ............................................................................................. 51
Whole Chip Application Circuit ................................................................................... 53
POWER COMSUMPTION .................................................................................................... 54

ELECTRICAL CHARACTERISTIC ....................................................................................... 55
7.1
Absolute Maximum Ratings ....................................................................................... 55
7.2
Nano100/Nano110/Nano120/Nano130 DC Electrical Characteristics ....................... 56
7.3
AC Electrical Characteristics ...................................................................................... 61

7.3.1
Oct 11, 2012
External Input Clock ....................................................................................................... 61
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7.3.2
7.3.3
7.3.4
7.3.5
7.4
Analog Characteristics ............................................................................................... 63

7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
External 4~24 MHz XTAL Oscillator ............................................................................... 61

External 32.768 kHz Crystal ........................................................................................... 62
Internal 12 MHz Oscillator .............................................................................................. 62
Internal 10 kHz Oscillator ............................................................................................... 62
12-bit ADC ...................................................................................................................... 63

Brown-out Detector......................................................................................................... 63
Power-on Reset .............................................................................................................. 64
Temperature Sensor....................................................................................................... 64
12-bit DAC ...................................................................................................................... 64
LCD ................................................................................................................................ 65
Touch Key (TK) .............................................................................................................. 65
Internal Voltage Reference ............................................................................................. 66
USB PHY Specifications................................................................................................. 66
PACKAGE DIMENSIONS ..................................................................................................... 68

8.1
128L LQFP (14x14x1.4 mm footprint 2.0 mm) ........................................................... 68
8.2
64L LQFP (7x7x1.4 mm footprint 2.0 mm) ................................................................. 69
8.3
48L LQFP (7x7x1.4 mm footprint 2.0 mm) ................................................................. 71
REVISION HISTORY ............................................................................................................ 72
Oct 11, 2012
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List of Figures
Figure 3-1 NuMicro
TM
Nano100 Series Selection Code ................................................................ 32
Figure 3-2 NuMicro
TM
Nano100 LQFP 128-pin Diagram ............................................................... 34
Figure 3-3 NuMicro
TM
Nano100 LQFP 64-pin Diagram ................................................................. 35
Figure 3-4 NuMicro
TM
Figure 3-5 NuMicro
TM
Figure 3-6 NuMicro
TM
Figure 3-7 NuMicro
TM
Figure 3-8 NuMicro
TM
Figure 3-9 NuMicro
TM
Figure 3-10 NuMicro
TM
Nano130 LQFP 128-pin Diagram ............................................................. 42
Figure 3-11 NuMicro
TM
Figure 4-1 NuMicro
TM
Nano100 Block Diagram ............................................................................. 44
Figure 4-2 NuMicro
TM
Figure 4-3 NuMicro
TM
Figure 4-4 NuMicro
TM
Figure 9-1 Typical Crystal Application Circuit ................................................................................ 61
Oct 11, 2012
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LIST OF TABLES
Table 1-1 Connectivity Support Table .............................................................................................. 7
Table 3-1 Nano100 Base Line Selection Table ............................................................................. 33
Table 3-2 Nano110 LCD Line Selection Table .............................................................................. 33
Table 3-3 Nano120 USB Connectivity Line Selection Table ......................................................... 33
Table 3-4 Nano130 Advanced Line Selection Table ..................................................................... 33
Oct 11, 2012
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GENERAL DESCRIPTION
The Nano100 series ultra-low power 32-bit microcontroller is embedded with ARM Cortex-M0
core operated at a wide voltage range from 1.8V to 3.6V and runs up to 42 MHz frequency with
32K/64K/128K bytes embedded Flash and 8K/16K-byte embedded SRAM. Integrating LCD 4x40
or 6x38 (COM/Segment), USB 2.0 full-speed function, RTC, 12-bit SAR ADC, 12-bit DAC,
Capacitive Touch-Key and provides high performance connectivity peripheral interfaces such as
UART, SPI, I2C, I2S, GPIOs, EBI (External Bus Interface) for external memory-mapped device
access and ISO-7816-3 for Smart card, the Nano100 series supports Brown-out Detector, Powerdown mode with RAM retention and fast wake-up via many peripheral interfaces.
The Nano100 series provides low power voltage, low power consumption, low standby current,
high integration peripherals, high-efficiency operation, fast wake-up function and the lowest cost
32-bit microcontrollers. The Nano100 series is suitable for a wide range of battery device
applications such as:
Portable Data Collector
Portable Medical Monitor
Portable RFID Reader
Portable Barcode Scanner
Security Alarm System
System Supervisors
Power Metering
USB Accessories
Smart Card Reader
Wireless Game Control Device
IPTV Remote Smart Keyboard
Wireless Sensors Node Device (WSN)
Wireless RF4CE Remote Control
Wireless Audio
Wireless Automatic Meter Reader (AMR)
Electronic Toll Collection (ETC)
The Nano100 Base line, an ultra-low power 32-bit microcontroller with the embedded ARM
Cortex-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42 MHz
frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It
integrates RTC, 12- channels 12-bit SAR ADC, 2-channels 12-bit DAC, 16-channels Capacitive
Touch-Key and provides high performance connectivity peripheral interfaces such as 2xUART,
3xSPI, 2xI2C, I2S, GPIOs, EBI (External Bus Interface) for external memory-mapped device
access and 3xISO-7816-3 for Smart card. The Nano100 Base line supports Brown-out Detector,
Power-down mode with RAM retention and fast wake-up via many peripheral interfaces.
The Nano110 LCD line, an ultra-low power 32-bit microcontroller with the embedded ARM
integrates LCD 4x40 or 6x38 (COM/Segment). RTC, 12-channels 12-bit SAR ADC, 2-channels
12-bit DAC, 16-channels Capacitive Touch-Key and provides high performance connectivity
peripheral interfaces such as 2xUART, 2xSPI, 2xI2C, I2S, GPIOs, EBI (External Bus Interface) for
external memory-mapped device access and 3xISO-7816-3 for Smart card. The Nano110 LCD
line supports Brown-out Detector, Power-down mode with RAM retention and fast wake-up via
Oct 11, 2012
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Revision V1.00
many peripheral interfaces.

The Nano120 USB Connectivity line, an ultra-low power 32-bit microcontroller with the embedded
ARM Cortex-M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 42
MHz frequency with 32K/64K/128K bytes embedded flash and 8K/16K bytes embedded SRAM. It
integrates USB 2.0 full-speed device function, RTC, 12-channels12-bit SAR ADC, 2-channels 12bit DAC, 16-channels Capacitive Touch-Key and provides high performance connectivity
peripheral interfaces such as 2xUART, 3xSPI, 2xI2C, I2S, GPIOs, EBI (External Bus Interface) for
external memory-mapped device access and 3xISO-7816-3 for Smart card. The Nano120 USB
Connectivity line supports Brown-out Detector, Power-down mode with RAM retention and fast
wake-up via many peripheral interfaces.
The Nano130 Advanced line, an ultra-low power 32-bit microcontroller with the embedded ARM
integrated LCD 4x40 or 6x38 (COM/Segment), USB 2.0 full-speed device function, RTC, 8channels 12-bit SAR ADC, 2-channels 12-bit DAC, Capacitive Touch-Key and provides high
performance connectivity peripheral interfaces such as 2xUART, 2xSPI, 2xI2C, I2S, GPIOs, EBI
(External Bus Interface) for external memory-mapped device access and 3xISO-7816-3 for Smart
card. The Nano130 Advanced line supports Brown-out Detector, Power-down mode with RAM
retention and fast wake-up via many peripheral interfaces.
Product Line
UART
SPI I2C I2S USB LCD ADC DAC TK RTC EBI
Nano100
Nano110
Nano120
Nano130
SC
Timer
Oct 11, 2012
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Table 1-1 Connectivity Support Table
Revision V1.00
FEATURES
The equipped features are dependent on the product line and their sub products.
2.1
Nano100 Features Base Line
Core
ARM Cortex-M0 core running up to 42 MHz
One 24-bit system timer
Supports Low Power Sleep mode
Single-cycle 32-bit hardware multiplier
NVIC for the 32 interrupt inputs, each with 4-levels of priority
Serial Wire Debug supports with 2 watchpoints/4 breakpoints
Brown-out
Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation
Flash EPROM Memory
Runs up to 42 MHz with zero wait state for discontinuous address read access
64K/32K/123K bytes application program memory (APROM)
4 KB in system programming (ISP) loader program memory (LDROM)
Programmable data flash start address and memory size with 512 bytes page
erase unit
In System Program (ISP)/In Application Program (IAP) to update on-chip Flash

EPROM
SRAM Memory
16K/8K bytes embedded SRAM
Supports DMA mode
DMA: Supports 8 channels: one VDMA channel, 6 PDMA channels and one CRC
channel
Oct 11, 2012
VDMA
Memory-to-memory transfer
Supports block transfer with stride
Supports word/half-word/byte boundary address
Supports address direction: increment and decrement
PDMA
Peripheral-to-memory,
transfer
Supports word boundary address
Supports word alignment transfer length in memory-to-memory mode
Supports word/half-word/byte alignment transfer length in peripheral-tomemory and memory-to-peripheral mode
Supports word/half-word/byte transfer data width from/to peripheral
memory-to-peripheral,
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and
memory-to-memory
Revision V1.00
CRC
Oct 11, 2012
16
12
CRC-CCITT: X
CRC-8: X + X + X + 1
CRC-16: X
CRC-32: X + X
4
2
X +X +X+1
+X
+X +1
16
32
+X
15
+X +1
26
+X
23
+X
22
+X
16
+X
12
+X
11
+X
10
+X +X +X +
Flexible selection for different applications
Built-in 12MHz OSC, can be trimmed to 0.25% deviation within all temperature
range when turning on auto-trim function (system must have external 32.768
kHz crystal input) otherwise 12MHz OSC has 1 % deviation within all
temperarure range.
Low power 10 kHz OSC for watchdog and low power system operation
Supports one PLL, up to 120 MHz, for high performance system operation and
USB application (48 MHz).
External 4~24 MHz crystal input for precise timing operation
External 32.768 kHz crystal input for RTC function and low power system
operation
GPIO
Three I/O modes:
Push-Pull output
Open-Drain output
Input only with high impendence
All inputs with Schmitt trigger
I/O pin configured as interrupt source with edge/level setting
Supports High Driver and High Sink I/O mode
Supports input 5V tolerance, except PA.0 ~ PA.7, PD.0 ~ PD.1 and PC.6 ~ PC.7
Timer
Supports 4 sets of 32-bit timers, each with 24-bit up-counting timer and one 8-bit
pre-scale counter
Independent Clock Source for each timer
Provides one-shot and periodic, and continuous operation modes
Internal trigger event to ADC, DAC module
Supports PDMA mode
Wake system up from Power-down mode
Watchdog Timer
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Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and

CRC-32
Clock Control
Supports address direction: increment, fixed, and wrap around
Oct 11, 2012
Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock)
Selectable time-out period from 1.6 ms ~ 26 sec (depending on clock source)
Interrupt or reset selectable when watchdog time-out
Window Watchdog Timer(WWDT)
6-bit down counter and 6-bit compare value to make the window period flexible
Selectable WWDT clock pre-scale counter to make WWDT time-out interval

variable.
RTC
Supports software compensation by setting frequency compensate register

(FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day,
month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Supports 80 bytes spare registers and a snoop pin to clear the content of these
spare registers
PWM/Capture
Supports 2 PWM modules, each has two 16-bit PWM generators
Provides eight PWM outputs or four complementary paired PWM outputs
Each PWM generator equipped with one clock divider, one 8-bit prescaler, two
clock selectors, and one Dead-zone generator for complementary paired PWM
(Shared with PWM timers) with eight 16-bit digital capture timers provides eight
rising/ falling/both capture inputs.
Supports One-shot and Continuous mode
Supports Capture interrupt
UART
Up to two 16-byte FIFO UART controllers
UART ports with flow control (TX, RX, CTSn and RTSn)
Supports IrDA (SIR) function
Supports LIN function
Supports RS-485 9 bit mode and direction control.
Programmable baud rate generator
Supports PDMA mode

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Oct 11, 2012
Up to three sets of SPI controller
Master up to 32 MHz, and Slave up to 16 MHz
Supports SPI/MICROWIRE Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 4 to 32 bits
MSB or LSB first data transfer
RX and TX on both rising or falling edge of serial clock independently
Two slave/device select lines when SPI controller is used as the master, and 1
slave/device select line when SPI controller is used as the slave
Supports byte suspend mode in 32-bit transmission
Supports two channel PDMA requests, one for transmit and another for receive
Supports three wire mode, no slave select signal, bi-direction interface
I2C
Up to two sets of I2C device
Master/Slave up to 1 Mbit/s
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of

serial data on the bus
Serial clock synchronization allows devices with different bit rates to

communicate via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and

resume serial transfer
Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs
up and timer-out counter overflows
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
I2S
Interface with external audio CODEC
Operated as either Master or Slave mode
Capable of handling 8, 16, 24 and 32 bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8 word FIFO data buffers: one for transmitting and the other for
receiving
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SPI
Oct 11, 2012
Generates interrupt requests when buffer levels cross a programmable

boundary
Supports two PDMA requests: one for transmitting and the other for receiving
ADC
12-bit SAR ADC up to 2Msps conversion rate
Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~ PD.3)
Six internal channels from DAC0, DAC1, internal reference voltage (Int_VREF),
Temperature sensor, AVDD, and AVSS.
Supports three reference voltage sources from VREF pin, internal reference
voltage (Int_VREF), and AVDD.
Supports Single Scan, Single Cycle Scan, and Continuous Scan mode
Each channel with individual result register
Only scan on enabled channels
Threshold voltage detection (comparator function)
Conversion started by software programming or external input
Supports PDMA mode
Supports up to four timer time-out events (TRM0_CH0, TMR0_CH1, TMR1_CH0

and TMR1_CH1) to enable ADC
DAC
12-bit monotonic output with 400K conversion rate
Synchronized update capability for two DACs (group function)
Supports up to four timer time-out events (TMR0_CH0, TMR0_CH1,

TMR1_CH0, TMR1_CH1), software or PDMA to trigger DAC to conversion
Touch Key(TK)
Supports programmable counter depth (16-bit, 14-bit, 12-bit and 10-bit) for
sensitivity adjustment
Supports programmable charge current for sensitivity adjustment
Supports programmable Clock Source frequency for sensitivity adjustment
Supports up to 16 touch-keys scanning
Supports external reference capacitor for different sensing environment

adjustment
SmartCard (SC)
Compliant to ISO-7816-3 T=0, T=1
Supports up to three ISO-7816-3 ports
Separates receive/transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level

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Revision V1.00
Programmable guard time selection (11 ETU ~ 266 ETU)
A 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and
waiting times processing
Supports auto inverse convention function
Supports stop clock level and clock stop (clock keep) function
Supports transmitter and receiver error retry and error limit function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detect the card is removal
Supports UART mode
EBI (External bus interface) support
Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode
Supports 8bit/16bit data width
Supports byte write in 16-bit Data Width mode
One built-in temperature sensor with 1 resolution
96-bit unique ID
128-bit unique customer ID
Operating Temperature: -40~85
Packages:
All Green package (RoHS)
LQFP 128-pin(14x14) / 64-pin(7x7) / 48-pin(7x7)
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Oct 11, 2012
Revision V1.00
2.2
Nano110 Features LCD Line
Core
Brown-out
Flash EPROM Memory
Runs up to 42 MHz with zero wait state for discontinuous address read access.
4 KB In System Programming (ISP) loader program memory (LDROM)
erase unit
In System Program (ISP)/In Application Program (IAP) to update on chip Flash

EPROM
SRAM Memory
Supports DMA mode
DMA : Supports 8 channels: one VDMA channel,6 PDMA channels, and one CRC
channel
Oct 11, 2012
VDMA
PDMA
Peripheral-to-memory, memory-to-peripheral, and memory-to-memory

transfer
CRC
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Revision V1.00
CRC-8: X + X + X + 1
CRC-16: X
CRC-32: X + X
4
2
X +X +X+1
+X
+X +1
16
32
+X
15
+X +1
26
+X
23
+X
22
+X
16
+X
12
+X
11
+X
10
+X +X +X +
temperarure range.
operation
GPIO
Three I/O modes:
Push-Pull output
Open-Drain output
Supports input 5V tolerance, except PA.0 ~ PA.7, PD.0 ~ PD.1 and PC.6 ~
PC.7)
Timer
Supports 4 sets of 32-bit timers, each with 24-bit up-timer and one 8-bit prescale counter
Provides one-shot and periodic, and continuous operation modes
Supports PDMA mode
Watchdog Timer
Oct 11, 2012
12
CRC-CCITT: X
Clock Source from LIRC (Internal 10 kHz Low Speed Oscillator Clock)
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Revision V1.00
16
Clock Control

CRC-32
Interrupt or reset selectable when watchdog time-out

variable.
RTC

(FCR)
month, year)
1/16, 1/8, 1/4, 1/2 and 1 second
spare registers
PWM/Capture
Supports 2 PWM modules, each has two 16-bit PWM generators
clock selectors, and one Dead-zone generator for complementary paired PWM
UART
Supports RS-485 9 bit mode and direction control (Low Density Only)
Supports PDMA mode
SPI
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Revision V1.00
Oct 11, 2012
Two slave/device select lines when SPI controller is as the master, and 1
slave/device select line when SPI controller is as the slave
Supports three wire mode, no slave select signal, bi-direction interface
I2C
Master/Slave up to 1Mbit/s
Bidirectional data transfer between masters and slaves

Serial clock synchronization allowing devices with different bit rates to


Built-in 14-bit time-out counter requestING the I2C interrupt if the I2C bus hangs
Programmable clocks allow versatile rate control
Supports multiple address recognition (four slave address with mask option)
I2S
receiving

boundary
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Revision V1.00
Oct 11, 2012
ADC
Temperature sensor, AVDD, and AVSS
Single scan/single cycle scan/continuous scan
Conversion start by software programming or external input
Supports PDMA mode

TMR1_CH0, and TMR1_CH1) to enable ADC
DAC

TMR1_CH0, TMR1_CH1), software or PDMA to trigger DAC to conversion
Touch Key(TK)
Supports programmable counter depth(16-bit, 14-bit, 12-bit and 10-bit) for


adjustment
SmartCard (SC)
Separates receive / transmit 4 bytes entry FIFO for data payloads
A 24-bit and two 8-bit time-out counter for Answer to Request (ATR) and waiting
times processing
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Revision V1.00
Supports UART mode
LCD
LCD driver for up to 4 COM x 40 SEG or 6 COM x 38 SEG
Supports Static,1/2 bias and 1/3 bias voltage
Four display modes; Static, 1/2 duty, 1/3 duty,1/4 duty, 1/5 duty and 1/6 duty.
Selectable LCD frequency by frequency divider
Configurable frame frequency
Internal Charge pump, adjustable contrast adjustment
Configurable Charge pump frequency
Blinking capability
Supports R-type/C-type method
LCD frame interrupt
96-bit unique ID
Packages:
Oct 11, 2012
LQFP 128-pin(14x14) / 64-pin(7x7)
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Revision V1.00
2.3
Nano120 Features USB Connectivity Line
Core
Brown-out
Flash EPROM Memory
4KB in system programming (ISP) loader program memory (LDROM)
erase unit

EPROM
SRAM Memory
Supports PDMA mode
DMA: Support 8 channels: one VDMA channel, 6 PDMA channels, and one CRC
channel
Oct 11, 2012
VDMA
PDMA
transfer
Supports address: increment, fixed, and wrap around
and
memory-to-memory
CRC
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Revision V1.00
Oct 11, 2012
12
CRC-CCITT: X
CRC-8: X + X + X + 1
CRC-16: X
CRC-32: X + X
4
2
X +X +X+1
+X
+X +1
16
32
+X
15
+X +1
26
+X
23
+X
22
+X
16
+X
12
+X
11
+X
10
+X +X +X +
temperarure range
Low power 10 kHz OSC for watchdog and low power system operatin
operation
GPIO
Three I/O modes:
Push-Pull output
Open-Drain output
I/O pin can be configured as interrupt source with edge/level setting
High driver and high sink IO mode support
Supports input 5V tolerance (except ADC and DAC shared pins)
Timer
Supports 4 sets of 32-bit timers, each with 24-bit up-timer and one 8-bit prescale counter
Provides one-shot,periodic, and continuous operation modes
Supports PDMA mode
Watchdog Timer
Clock Source from LIRC. (Internal 10 kHz Low Speed Oscillator Clock)

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Revision V1.00
16
Clock Control

CRC-32
Interrupt or reset selectable on watchdog time-out

variable.
RTC

(FCR)
month, year)
1/16, 1/8, 1/4, 1/2 and 1 second
Wake system up from Power-down or Idle mode
Support 80 bytes spare registers and a snoop pin to clear the content of these
spare registers
PWM/Capture
Supports 2 PWM module, each has two 16-bit PWM generators
Provide eight PWM outputs or four complementary paired PWM outputs
clock selectors, and one Dead-Zone generator for complementary paired PWM
Supports one shot and continuous mode
UART
Supports RS-485 9 bit mode and direction control. (Low Density Only)
Supports PDMA mode
SPI
Oct 11, 2012

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Revision V1.00
Oct 11, 2012
Two slave/device select lines when SPI controller is as the master, and 1
slave/device select line when SPI controller is as the slave
Supports three wire, no slave select signal, bi-direction interface
I2C



Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs
Programmable clocks allow versatile rate control
I2S
receiving

boundary
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Revision V1.00
Oct 11, 2012
ADC
Up to 12-ch single-ended input from external pin (PA.0 ~ PA.7 and PD.0 ~
PD.3).
voltage (Int_VREF), and AVDD
Supports single scan, single cycle scan, and continuous scan modes
Supports PDMA mode

TMR1_CH0, TMR1_CH1) to enable ADC
DAC
Supports up to four timer time-out event (TMR0_CH0, TMR0_CH1, TMR1_CH0,

and TMR1_CH1), software or PDMA to trigger DAC to conversion
Touch Key(TK)


adjustment
SmartCard (SC)
Separates receive / transmit 4 bytes entry FIFO for data payloads
times processing
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Revision V1.00
Supports UART mode
USB 2.0 Full-Speed Device
One set of USB 2.0 FS Device 12Mbps
On-chip USB Transceiver
Provides 1 interrupt source with 4 interrupt events
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provides 8 programmable endpoints
Includes 512 Bytes internal SRAM as USB buffer
Provides remote wake-up capability
EBI (External bus interface) support

Supports byte write in 16-bit Data Width mode
96-bit unique ID
Packages:
Oct 11, 2012
LQFP 128-pin(14x14) / 64-pin(7x7) / 48-pin(7x7)
Page 25 of 72
Revision V1.00
2.4
Nano130 Features Advanced Line
Core
Brown-out
Flash EPROM Memory
4KB in system programming (ISP) loader program memory (LDROM)
erase unit

EPROM
SRAM Memory
Supports DMA mode
DMA : Supports 8 channels: one VDMA channel,6 PDMA channels, and one CRC
channnel
VDMA
PDMA
and
memory-to-memory
transfer
CRC

CRC-32
Oct 11, 2012
Page 26 of 72
Revision V1.00
16
12
CRC-CCITT: X
CRC-8: X + X + X + 1
CRC-16: X
CRC-32: X
+X
+X +1
16
+X
15
+X +1
32
+X
26
+X
23
+X
22
+X
16
+X
12
+X
11
+X
10
+X +X +X +
X +X +X+1
Clock Control
temperarure range.
operation
GPIO
Push-Pull output
Open-Drain output
Supports input 5V tolerance (except ADC and DAC shared pins)
Timer
Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale
counter
Oct 11, 2012
Provides One-shot, Periodic Operation, and continuous modes
Supports internal trigger event to ADC, DAC and PDMA
Watchdog Timer
Clock Source is from LIRC. (Internal 10 kHz Low Speed Oscillator Clock)
Selectable time-out period from 1.6ms ~ 26sec (depends on clock source)
Interrupt or reset selectable on watchdog time-out
WDT can wake system up from Power-down mode

Page 27 of 72
Revision V1.00
Three I/O modes:

variable.
RTC

(FCR)
month, year)
1/16, 1/8, 1/4, 1/2 and 1 second
spare registers
PWM/Capture
Supports 2 PWM module, each with two 16-bit PWM generators
clock selectors, and one Dead-Zone generator for complementary paired PWM
Oct 11, 2012
UART
Supports RS-485 9 bit mode and direction control (Low Density Only)
Supports PDMA mode
SPI
Up to 3 sets of SPI controller

Page 28 of 72
Revision V1.00
Two slave/device select lines when used as the master, and 1 slave/device
select line when used as the slave
Supports two channel PDMA request, one for transmit and another for receive
Supports three wire, no slave select signal, bi-direction interface
I2C


Serial clock synchronization can be used as a handshake mechanism to

suspend and resume serial transfer
Built-in 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs
Programmable clocks allowing for versatile rate control
I2S
Operate as either Master or Slave mode
receiving

boundary
ADC
Oct 11, 2012
Page 29 of 72
Revision V1.00
voltage (Int_VREF), and AVDD
Single scan/single cycle scan/continuous scan
Scan on enabled channels
Supports PDMA mode
Supports up to four timer time-out events (TMR0_CH0, TMR0_CH1,TMR1_CH0,

TMR1_CH1) to enable ADC
DAC

TMR1_CH0, and TMR1_CH1), software or PDMA to trigger DAC to conversion
Touch Key(TK)


adjustment
SmartCard (SC)
Separates receive/transmit 4 bytes entry FIFO for data payloads
times processing
Oct 11, 2012

Page 30 of 72
Revision V1.00
Supports hardware auto deactivation sequence when detecting the card is

removed
LCD
LCD driver for up to 4 COM x 40 SEG or 6 COM x 38 SEG
Supports Static,1/2 bias and 1/3 bias voltage
Four display modes: Static, 1/2 duty, 1/3 duty, 1/4 duty, 1/5 duty and 1/6 duty.
Selectable LCD frequency by frequency divider
Configurable frame frequency
Internal Charge pump, adjustable contrast adjustment
Configurable Charge pump frequency
Blinking capability
Supports R-type/C-type method
LCD frame interrupt
USB 2.0 Full-speed Device
One set of USB 2.0 FS Device 12Mbps
On-chip USB Transceiver
Provides 1 interrupt source with 4 interrupt events
Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
Auto suspend function when no bus signaling for 3 ms
Provides 8 programmable endpoints
Includes 512 Bytes internal SRAM as USB buffer
Provides remote wake-up capability
EBI (External bus interface)
Supports byte write in 16-bit data width mode

96-bit unique ID

Packages:
Oct 11, 2012
Support UART mode
LQFP 128-pin(14x14) / 64-pin (7x7)
Page 31 of 72
Revision V1.00
3
3.1
PARTS INFORMATION LIST AND PIN CONFIGURATION

NuMicro Nano100 Series Selection Code
Figure 3-1 NuMicro
Oct 11, 2012
TM
Nano100 Series Selection Code
Page 32 of 72
Revision V1.00
3.2
NuMicro Nano100 Products Selection Guide
3.2.1
NuMicro Nano100 Base Line Selection Guide

Flash
SRAM
NANO100LC2BN
32K
8K
Data Flash
Shared AP
ROM
Configurable
I2S
PWM
12-bit
ADC
RTC
EBI
IRC
10KHz
12MHz
V
NANO100LD2BN
64K
8K
NANO100LD3BN
64K
NANO100LE3BN
4x32-bit
4x32-bit
up to 52
4x32-bit
4K
up to 52
4x32-bit
Configurable
4K
up to 86
4x32-bit
Connectivity
LDROM
ISP Flash
I/O
Timer
4K
up to 38
Configurable
4K
16K
Configurable
128K
16K
NANO100SC2BN
32K
NANO100SD2BN
64K
NANO100SD3BN
Part No.
PDMA
LCD
12-bit
DAC
Smart
Card
Touch
Key
ISP
ICP
Package
LQFP48
LQFP48
LQFP48
LQFP48
LQFP64
LQFP64
LQFP64
LQFP64
12
16
LQFP128
UART
SPI
I2C
USB
4x32-bit
up to 38
4x32-bit
4K
up to 38
4x32-bit
Configurable
4K
up to 38
4x32-bit
8K
Configurable
4K
up to 52
8K
Configurable
4K
up to 52
64K
16K
Configurable
4K
NANO100SE3BN
128K
16K
Configurable
NANO100KC2BN
32K
8K
NANO100KD2BN
64K
8K
Configurable
4K
up to 86
4x32-bit
12
16
LQFP128
NANO100KD3BN
64K
16K
Configurable
4K
up to 86
4x32-bit
12
16
LQFP128
NANO100KE3BN
128K
16K
Configurable
4K
up to 86
4x32-bit
12
16
LQFP128
PDMA
LCD
12-bit
DAC
Smart
Card
Touch
Key
ISP
ICP
Package
4x31, 6x29
LQFP64
Table 3-1 Nano100 Base Line Selection Table
3.2.2
NuMicro Nano110 LCD Line Selection Guide

Flash
SRAM
NANO110SC2BN
32K
8K
Data Flash
Shared AP
ROM
Configurable
NANO110SD2BN
64K
8K
NANO110SD3BN
64K
16K
NANO110SE3BN
128K
NANO110KC2BN
32K
Part No.
NANO110KD2BN
LDROM
ISP Flash
I/O
Timer
4K
up to 51
Configurable
4K
Configurable
4K
16K
Configurable
8K
I2S
PWM
12-bit
ADC
RTC
EBI
IRC
10KHz
12MHz
V
4x31, 6x29
LQFP64
4x31, 6x29
LQFP64
4x31, 6x29
LQFP64
12
4x40, 6x38
16
LQFP128
Connectivity
UART
SPI
I2C
USB
4x32-bit
up to 51
4x32-bit
up to 51
4x32-bit
4K
up to 51
4x32-bit
Configurable
4K
up to 86
4x32-bit
64K
8K
Configurable
4K
up to 86
4x32-bit
12
4x40, 6x38
16
LQFP128
NANO110KD3BN
64K
16K
Configurable
4K
up to 86
4x32-bit
12
4x40, 6x38
16
LQFP128
NANO110KE3BN
128K
16K
Configurable
4K
up to 86
4x32-bit
12
4x40, 6x38
16
LQFP128
PDMA
LCD
12-bit
DAC
Smart
Card
Touch
Key
ISP
ICP
Package
LQFP48
Table 3-2 Nano110 LCD Line Selection Table
3.2.3
NuMicro Nano120 USB Connectivity Line Selection Guide
64K
8K
Configurable
4K
up to 34
4x32-bit
LQFP48
64K
16K
Configurable
4K
up to 34
4x32-bit
LQFP48
NANO120LE3BN
128K
16K
Configurable
4K
up to 34
4x32-bit
LQFP48
NANO120SC2BN
32K
8K
Configurable
4K
up to 48
4x32-bit
LQFP64
NANO120SD2BN
64K
8K
Configurable
4K
up to 48
4x32-bit
LQFP64
NANO120SD3BN
64K
16K
Configurable
4K
up to 48
4x32-bit
NANO120SE3BN
128K
16K
Configurable
4K
up to 48
4x32-bit
LQFP64
NANO120KC2BN
32K
8K
Configurable
4K
up to 86
4x32-bit
LQFP128
Flash
NANO120LC2BN
32K
NANO120LD2BN
NANO120LD3BN
NANO120KD2BN
SRAM
LDROM
ISP Flash
I/O
4K
up to 34
I2S
PWM
12-bit
ADC
RTC
EBI
IRC
10KHz
12MHz
V
Connectivity
Timer
UART
SPI
I2C
USB
4x32-bit
LQFP64
64K
8K
Configurable
4K
up to 86
4x32-bit
16
LQFP128
NANO120KD3BN
64K
16K
Configurable
4K
up to 86
4x32-bit
16
LQFP128
NANO120KE3BN
128K
16K
Configurable
4K
up to 86
4x32-bit
16
LQFP128
Table 3-3 Nano120 USB Connectivity Line Selection Table
3.2.4
NuMicro Nano130 Advanced Line Selection Guide
NANO130SC2BN
32K
8K
Data Flash
Shared AP
ROM
Configurable
NANO130SD2BN
64K
8K
Configurable
4K
up to 47
4x32-bit
4x31, 6x29
NANO130SD3BN
64K
16K
Configurable
4K
up to 47
4x32-bit
4x31, 6x29
NANO130SE3BN
128K
16K
Configurable
4K
up to 47
4x32-bit
4x31, 6x29
LQFP64
NANO130KC2BN
32K
8K
Configurable
4K
up to 86
4x32-bit
4x40, 6x38
16
LQFP128
NANO130KD2BN
64K
8K
Configurable
4K
up to 86
4x32-bit
4x40, 6x38
16
LQFP128
NANO130KD3BN
64K
16K
Configurable
4K
up to 86
4x32-bit
4x40, 6x38
16
LQFP128
NANO130KE3BN
128K
16K
Configurable
4K
up to 86
4x32-bit
4x40, 6x38
16
LQFP128
Part No.
Flash
SRAM
I2S
PWM
12-bit
ADC
RTC
EBI
IRC
10KHz
12MHz
V
Connectivity
LDROM
ISP Flash
I/O
4K
up to 47
Timer
UART
SPI
I2C
USB
4x32-bit
PDMA
LCD
12-bit
DAC
Smart
Card
Touch
Key
ISP
ICP
Package
4x31, 6x29
LQFP64
LQFP64
LQFP64
Table 3-4 Nano130 Advanced Line Selection Table

Oct 11, 2012
Page 33 of 72
Revision V1.00
8K
Data Flash
Shared AP
ROM
Configurable
Part No.
Pin Configuration
ICE_DAT/PF.0
PA.12
PA.13
PA.14
PA.15
PC.8
PC.9
PC.10
80
79
78
77
76
75
74
73
PE.4
ICE_CLK/PF.1
81
PE.3
NC
82
65
VDD
83
PE.2
NC
84
66
VSS
85
PE.1
VSS
86
67
AVSS
87
PE.0
AVSS
88
68
PA.0/AD0
89
PC.13
PA.1/AD1
90
69
PA.2/AD2
91
70
PA.3/AD3
92
PC.11
PA.4/AD4
93
PC.12
PA.5/AD5
94
71
PA.6/AD6
95
72
PA.7/AD7
96
NuMicro Nano100 LQFP 128-pin
VREF
97
64
PB.9
NC
98
63
PB.10
AVDD
99
62
PB.11
AD8/PD.0
100
61
PE.5
AD9/PD.1
101
60
NC
AD10/PD.2
102
59
NC
AD11/PD.3
103
58
PE.6
NC
104
57
PC.0
PD.4
105
56
PC.1
PD.5
106
55
PC.2
PC.7
107
54
PC.3
PC.6
108
53
PC.4
PC.15
109
52
PC.5
PC.14
110
51
PD.15
PB.15
111
50
PD.14
NC
112
49
PD.7
XT1_IN
113
48
PD.6
XT1_OUT
114
47
PB.3
NC
115
46
PB.2
nRESET
116
45
PB.1
VSS
117
44
PB.0
VSS
118
43
NC
NC
119
42
NC
VDD
120
41
NC
NC
121
40
NC
PF.4
122
39
NC
PF.5
123
38
PE.7
VSS
124
37
PE.8
PVSS
125
36
PE.9
PB.8
126
35
PE.10
PE.15
127
34
PE.11
PE.14
128
33
PE.12
Oct 11, 2012
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PD.11
PD.12
PD.13
PB.4
PB.5
PB.6
PB.7
NC
LDO_CAP
NC
NC
VDD
NC
VSS
VSS
VSS
VSS
11
PA.9
15
10
PA.10
PD.10
9
PA.11
14
8
NC
PD.9
7
X32I
13
6
X32O
PD.8
5
NC
12
4
PB.12
Figure 3-2 NuMicro
PA.8
3
PB.13
NANO100
LQFP 128-pin
3.3.1.1
NuMicro Nano100 Pin Diagrams
3.3.1
PB.14
3.3
PE.13
TM
Nano100 LQFP 128-pin Diagram
Page 34 of 72
Revision V1.00
PA.4/AD4
PA.3/AD3
PA.2/AD2
PA.1/AD1
PA.0/AD0
AVSS
ICE_CLK/PF.1
ICE_DAT/PF.0
PA.12
PA.13
PA.14
PA.15
PC.8
PC.9
PC.10
PC.11
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD5/PA.5
49
32
PB.9
AD6/PA.6
50
31
PB.10
VREF
51
30
PB.11
AVDD
52
29
PE.5
PC.7
53
28
PC.0
PC.6
54
27
PC.1
PC.15
55
26
PC.2
PC.14
56
25
PC.3
PB.15
57
24
PD.15
XT1_IN
58
23
PD.14
XT1_OUT
59
22
PD.7
nRESET
60
21
PD.6
VSS
61
20
PB.3
NANO100
LQFP 64-pin
Oct 11, 2012
15
16
VSS
12
PB.6
VDD
11
PB.5
14
10
PB.4
13
9
PA.8
PB.7
TM
LDO_CAP
PA.9
PA.10
5
X32I
Figure 3-3 NuMicro
PA.11
PB.0
17
X32O
64
PB.1
PB.8
PB.2
18
PB.12
19
63
PB.13
62
VDD
PVSS
PB.14
3.3.1.2
Page 35 of 72
Revision V1.00
PA.4/AD4
PA.3/AD3
PA.2/AD2
PA.1/AD1
PA.0/AD0
AVSS
ICE_CLK/PF.1
ICE_DAT/PF.0
PA.12
PA.13
PA.14
PA.15
36
35
34
33
32
31
30
29
28
27
26
25
AD5/PA.5
37
24
PB.9
AD6/PA.6
38
23
PB.10
VREF
39
22
PB.11
AVDD
40
21
PE.5
PC.7
41
20
PC.0
19
PC.1
18
PC.2
NANO100
LQFP 48-pin
Figure 3-4 NuMicro
Oct 11, 2012
PB.5
PA.10
TM
12
PB.0
VSS
PB.1
13
11
14
48
VDD
47
PB.8
10
PVSS
PB.2
LDO_CAP
15
46
PB.4
nRESET
PB.3
PA.8
16
45
PA.9
XT1_OUT
PC.3
17
PA.11
44
XT1_IN
X32I
43
42
X32O
PC.6
PB.15
3.3.1.3
PB.12
Page 36 of 72
Revision V1.00
ICE_DAT/PF.0
PA.12
PA.13
PA.14
PA.15
PC.8
PC.9
PC.10
79
78
77
76
75
74
73
PE.4
ICE_CK/PF.1
80
PE.3
NC
81
65
VDD
82
PE.2
NC
83
66
VSS
84
PE.1
VSS
85
67
AVSS
86
PE.0
AVSS
87
68
PA.0
88
PC.13
PA.1
89
69
PA.2
90
70
PA.3
91
PC.11
PA.4/AD4/LCD_SEG39
92
PC.12
PA.5/AD5/LCD_SEG38
93
71
PA.6/AD6/LCD_SEG37
94
72
PA.7/AD7/LCD_SEG36
95
3.3.2.1
96
3.3.2
97
64
PB.9/LCD_V1
NC
98
63
PB.10/LCD_V2
AVDD
99
62
PB.11/LCD_V3
AD8/PD.0
100
61
PE.5
AD9/PD.1
101
60
NC
AD10/PD.2
102
59
VLCD
AD11/PD.3
103
58
PE.6
NC
104
57
PC.0/LCD_DH1
LCD_SEG35/PD.4
105
56
PC.1/LCD_DH2
LCD_SEG34/PD.5
106
55
PC.2/LCD_COM0
PC.7
107
54
PC.3/LCD_COM1
PC.6
108
53
PC.4/LCD_COM2
LCD_SEG33/PC.15
109
52
PC.5/LCD_COM3
LCD_SEG32/PC.14
110
51
PD.15/LCD_SEG0
LCD_SEG31/PB.15
111
50
PD.14/LCD_SEG1
NC
112
49
PD.7/LCD_SEG2
XT1_IN
113
48
PD.6/LCD_SEG3
XT1_OUT
114
47
PB.3/LCD_SEG4
NC
115
46
PB.2/LCD_SEG5
nRESET
116
45
PB.1/LCD_SEG6
VSS
117
44
PB.0/LCD_SEG7
VSS
118
43
NC
NC
119
42
NC
VDD
120
41
NC
NC
121
40
NC
PF.4
122
39
NC
PF.5
123
38
PE.7/LCD_SEG8
VSS
124
37
PE.8/LCD_SEG9
PVSS
125
36
PE.9
LCD_SEG30/PB.8
126
35
PE.10
LCD_SEG29/PE.15
127
34
PE.11
LCD_SEG28/PE.14
128
33
PE.12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
LCD_SEG27/PE.13
LCD_SEG26//PB.14
LCD_SEG25/PB.13
LCD_SEG24/PB.12
NC
X32O
X32I
NC
LCD_SEG23/PA.11
LCD_SEG22/PA.10
LCD_SEG21/PA.9
LCD_SEG20/PA.8
LCD_SEG19/PD.8
LCD_SEG18/PD.9
LCD_SEG17/PD.10
LCD_SEG16/PD.11
LCD_SEG15/PD.12
LCD_SEG14/PD.13
LCD_SEG13/PB.4
LCD_SEG12/PB.5
LCD_SEG11/PB.6
LCD_SEG10/PB.7
NC
LDO_CAP
NC
NC
VDD
NC
VSS
VSS
VSS
VSS
NANO110
LQFP 128-pin
Figure 3-5 NuMicro
Oct 11, 2012
TM
Page 37 of 72
Revision V1.00
VREF
PA.4/AD4/LCD_SEG21
PA.3/AD3/LCD_SEG22
PA.2/AD2/LCD_SEG23
PA.1/AD1
PA.0/AD0
AVSS
ICE_CLK/PF.1
ICE_DAT/PF.0
PA.12/LCD_SEG24
PA.13/LCD_SEG25
PA.14/LCD_SEG26
PA.15/LCD_SEG27
PC.8/LCD_SEG28
PC.9/LCD_SEG29
PC.10/LCD_SEG30
PC.11/LCD_SEG31
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
3.3.2.2
LCD_SEG20/AD5/PA.5
49
32
PB.9/LCD_V3
LCD_SEG19/AD6/PA.6
50
31
PB.10/LCD_V2
VREF
51
30
PB.11/LCD_V1
AVDD
52
29
LCD_VLCD
LCD_SEG17/PC.7
53
28
PC.0/LCD_DH1
PC.6
54
27
PC.1/LCD_DH2
LCD_SEG16/PC.15
55
26
PC.2/LCD_COM0
LCD_SEG15/PC.14
56
25
PC.3/LCD_COM1
LCD_SEG14/PB.15
57
24
PD.15
XT1_IN
58
23
PD.14
XT1_OUT
59
22
PD.7
nRESET
60
21
PD.6
VSS
61
20
PB.3/LCD_COM2
Nano110
LQFP 64-pin
Oct 11, 2012
10
11
12
13
14
15
16
LCD_SGE8/PA.10
LCD_SGE7/PA.9
LCD_SGE6/PA.8
LCD_SGE5/PB.4
LCD_SGE4/PB.5
LCD_SGE3/PB.6
LCD_SGE2/PB.7
LDO_CAP
VDD
VSS
Figure 3-6 NuMicro
LCD_SGE9/PA.11
PB.0/LCD_SEG1
X32I
17
X32O
64
3
PB.1/LCD_SEG0
LCD_SEG13/PB.8
LCD_SGE10/PB.12
PB.2/LCD_COM3
18
19
63
62
LCD_SEG11/PB.13
VDD
PVSS
LCD_SEG12/PB.14
TM
Page 38 of 72
Revision V1.00
ICE_DAT/PF.0
PA.12
PA.13
PA.14
PA.15
PC.8
PC.9
PC.10
80
79
78
77
76
75
74
73
PE.4
ICE_CLK/PF.1
81
PE.3
NC
82
65
VDD
83
PE.2
NC
84
66
VSS
85
PE.1
VSS
86
67
AVSS
87
PE.0
AVSS
88
68
PA.0
89
PC.13
PA.1
90
69
PA.2
91
70
PA.3
92
PC.11
PA.4
93
PC.12
PA.5
94
71
PA.6
95
72
PA.7
96
97
64
PB.9
NC
98
63
PB.10
AVDD
99
62
PB.11
PD.0
100
61
PE.5
PD.1
101
60
NC
PD.2
102
59
NC
PD.3
103
58
PE.6
NC
104
57
PC.0
PD.4
105
56
PC.1
PD.5
106
55
PC.2
PC.7
107
54
PC.3
PC.6
108
53
PC.4
PC.15
109
52
PC.5
PC.14
110
51
PD.15
PB.15
111
50
PD.14
NC
112
49
PD.7
XT1_IN
113
48
PD.6
XT1_OUT
114
47
PB.3
NC
115
46
PB.2
nRESET
116
45
PB.1
VSS
117
44
PB.0
VSS
118
43
USB_D+
NC
119
42
USB_D-
VDD
120
41
USB_VDD33_CAP
NC
121
40
USB_VBUS
PF.4
122
39
NC
PF.5
123
38
PE.7
VSS
124
37
PE.8
PVSS
125
36
PE.9
PB.8
126
35
PE.10
PE.15
127
34
PE.11
PE.14
128
33
PE.12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PB.13
PB.12
NC
X32O
X32I
NC
PA.11
PA.10
PA.9
PA.8
PD.8
PD.9
PD.10
PD.11
PD.12
PD.13
PB.4
PB.5
PB.6
PB.7
NC
LDO_CAP
NC
NC
VDD
NC
VSS
VSS
VSS
VSS
NANO120
LQFP 128-pin
Figure 3-7 NuMicro
Oct 11, 2012
TM
Page 39 of 72
Revision V1.00
VREF
PB.14
3.3.3.1
PE.13
3.3.3
PA.4
PA.3
PA.2
PA.1
PA.0
AVSS
ICE_CLK/PF.1
ICE_DAT/PF.0
PA.12
PA.13
PA.14
PA.15
PC.8
PC.9
PC.10
PC.11
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA.5
49
32
PB.9
PA.6
50
31
PB.10
VREF
51
30
PB.11
AVDD
52
29
PE.5
PC.7
53
28
PC.0
PC.6
54
27
PC.1
PC.15
55
26
PC.2
PC.14
56
25
PC.3
PB.15
57
24
PB.3
NANO120
LQFP 64-pin
XT1_IN
58
23
PB.2
XT1_OUT
59
22
PB.1
nRESET
60
21
PB.0
Figure 3-8 NuMicro
Oct 11, 2012
10
11
12
13
14
15
16
PA.9
PA.8
PB.4
PB.5
PB.6
PB.7
LDO
VDD
VSS
USB_VBUS
PA.10
17
64
PB.8
X32I
USB_VDD33_CAP
PA.11
18
63
X32O
USB_D-
PVSS
USB_D+
19
20
62
PB.12
61
PB.13
VSS
VDD
3.3.3.2
PB.14
TM
Page 40 of 72
Revision V1.00
PA.4
PA.3
PA.2
PA.1
PA.0
AVSS
ICE_CLK/PF.1
ICE_DAT/PF.0
PA.12
PA.13
PA.14
PA.15
36
35
34
33
32
31
30
29
28
27
26
25
PA.5
37
24
PC.0
PA.6
38
23
PC.1
VREF
39
22
PC.2
AVDD
40
21
PC.3
PC.7
41
20
PB.3
PC.6
42
19
PB.2
PB.15
43
18
PB.1
XT1_IN
44
17
PB.0
XT1_OUT
45
16
USB_D+
nRESET
46
15
USB_D-
PVSS
47
14
USB_VDD33_CAP
PB.8
48
13
USB_VBUS
Oct 11, 2012
TM
10
11
12
VDD
VSS
8
PB.4
PB.5
7
PA.8
LDO_CAP
6
PA.9
4
PA.11
3
X32I
PA.10
2
X32O
Figure 3-9 NuMicro
NANO120
LQFP 48-pin
PB.12
3.3.3.3
Page 41 of 72
Revision V1.00
ICE_DAT/PF.0
PA.12
PA.13
PA.14
PA.15
PC.8
PC.9
PC.10
79
78
77
76
75
74
73
PE.4
ICE_CLK/PF.1
80
PE.3
NC
81
65
VDD
82
PE.2
NC
83
66
VSS
84
PE.1
VSS
85
67
AVSS
86
PE.0
AVSS
87
68
PA.0/AD0
88
PC.13
PA.1/AD1
89
69
PA.2/AD2
90
70
PA.3/AD3
91
PC.11
PA.4/AD4/LCD_SEG39
92
PC.12
PA.5/AD5/LCD_SEG38
93
71
PA.6/AD6/LCD_SEG37
94
72
PA.7/AD7/LCD_SEG36
95
3.3.4.1
96
3.3.4
VREF
97
64
PB.9/LCD_V3
NC
98
63
PB.10/LCD_V2
AVDD
99
62
PB.11/LCD_V1
AD8/PD.0
100
61
PE.5
AD9/PD.1
101
60
NC
AD10/PD.2
102
59
VLCD
AD11/PD.3
103
58
PE.6
NC
104
57
PC.0/LCD_DH1
LCD_SEG35/PD.4
105
56
PC.1/LCD_DH2
LCD_SEG34/PD.5
106
55
PC.2/LCD_COM0
PC.7
107
54
PC.3/LCD_COM1
PC.6
108
53
PC.4/LCD_COM2
LCD_SEG33/PC.15
109
52
PC.5/LCD_COM3
LCD_SEG32/PC.14
110
51
PD.15/LCD_SEG0
LCD_SEG31/PB.15
111
50
PD.14/LCD_SEG1
NC
112
49
PD.7/LCD_SEG2
XT1_IN
113
48
PD.6/LCD_SEG3
XT1_OUT
114
47
PB.3/LCD_SEG4
NC
115
46
PB.2/LCD_SEG5
nRESET
116
45
PB.1/LCD_SEG6
VSS
117
44
PB.0/LCD_SEG7
VSS
118
43
USB_D+
NC
119
42
USB_D-
VDD
120
41
USB_VDD33_CAP
NC
121
40
USB_VBUS
PF.4
122
39
NC
PF.5
123
38
PE.7/LCD_SEG8
VSS
124
37
PE.8/LCD_SEG9
PVSS
125
36
PE.9
LCD_SEG30/PB.8
126
35
PE.10
LCD_SEG29/PE.15
127
34
PE.11
LCD_SEG28/PE.14
128
33
PE.12
Oct 11, 2012
20
21
22
23
24
25
26
27
28
29
30
31
32
LCD_SEG12/PB.5
LCD_SEG11/PB.6
LCD_SEG10/PB.7
NC
LDO
NC
NC
VDD
NC
VSS
VSS
VSS
VSS
13
LCD_SEG19/PD.8
19
12
LCD_SEG20/PA.8
LCD_SET13/PB.4
11
LCD_SEG21/PA.9
18
10
LCD_SEG22/PA.10
LCD_SEG14/PD.13
9
LCD_SEG23/PA.11
17
8
NC
LCD_SEG15/PD.12
7
X32I
16
6
X32O
LCD_SEG16/PD.11
5
NC
15
4
LCD_SEG24/PB.12
LCD_SEG17/PD.10
3
LCD_SEG25/PB.13
TM
14
Figure 3-10 NuMicro
LCD_SEG18/PD.9
LCD_SEG26/PB.14
NANO130
LQFP 128-pin
LCD_SEG27/PE.13
Page 42 of 72
Revision V1.00
PA.4/AD4/LCD_SEG21
PA.3/AD3/LCD_SEG22
PA.2/AD2/LCD_SEG23
PA.1/AD1
PA.0/AD0
AVSS
ICE_CLK/PF.1
ICE_DAT/PF.0
PA.12/LCD_SEG24
PA.13/LCD_SEG25
PA.14/LCD_SEG26
PA.15/LCD_SEG27
PC.8/LCD_SEG28
PC.9/LCD_SEG29
PC.10/LCD_SEG30
PC.11/LCD_SEG31
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
3.3.4.2
LCD_SEG20/AD5/PA.5
49
32
PB.9/LCD_V3
LCD_SEG19/AD6/PA.6
50
31
PB.10/LCD_V2
VREF
51
30
PB.11/LCD_V1
AVDD
52
29
VLCD
LCD_SEG17/PC.7
53
28
PC.0/LCD_DH1
PC.6
54
27
PC.1/LCD_DH2
LCD_SEG16/PC.15
55
26
PC.2/LCD_COM0
LCD_SEG15/PC.14
56
25
PC.3/LCD_COM1
LCD_SEG14/PB.15
57
24
PB.3/LCD_COM2
XT1_IN
58
23
PB.2/LCD_COM3
XT1_OUT
59
22
PB.1/LCD_SEG0
nRESET
60
21
PB.0/LCD_SEG1
VSS
61
20
USB_D+
VDD
62
19
USB_D-
PVSS
63
18
USB_VDD33_CAP
LCD_SEG13/PB.8
64
17
USB_VBUS
Oct 11, 2012
TM
10
11
12
13
14
15
16
LCD_SGE6/PA.8
LCD_SGE5/PB.4
LCD_SGE4/PB.5
LCD_SGE3/PB.6
LCD_SGE2/PB.7
LDO_CAP
VDD
VSS
5
X32I
LCD_SGE7/PA.9
4
X32O
LCD_SGE8/PA.10
3
LCD_SGE10/PB.12
LCD_SGE9/PA.11
LCD_SEG11/PB.13
Figure 3-11 NuMicro
LCD_SEG12/PB.14
Nano130
LQFP 64-pin
Page 43 of 72
Revision V1.00
4
4.1
BLOCK DIAGRAM
Nano100 Block Diagram
LXT
EBI
FLASH
123/64/
32 KB
Cortex-M0
42 MHz
DMA
CLK_CTL
P
L
L
LIRC
HXT
HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
ISP 4KB
SRAM
16/8 KB
I2C 1
I2C 0
PWM 1
PWM 0
Timer 2/3
Timer 0/1
UART 1
UART 0
SPI 1
SPI 0
I2S
SPI 2
SC 0/UART3
RTC
SC 1/UART4
WDT
BOD (1.7/2.0/2.5 V)
GPIO
A,B,C,D,E,F
12-b ADC
12-b DAC
1.8/2.5V REF
Touch Key
Peripherals with PDMA
SC 2/UART5
NOTE: BOD can wake up system.

External interrupts, included in GPIO, can wake up system, too.
Figure 4-1 NuMicro
Oct 11, 2012
TEMP Sensor
TM
Peripherals with wake-up
Page 44 of 72
Revision V1.00
4.2

LXT
EBI
FLASH
123/64/
32 KB
Cortex-M0
42 MHz
DMA
CLK_CTL
P
L
L
LIRC
HXT
HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
BOD (1.7/2.0/2.5 V)
ISP 4KB
SRAM
16/8 KB
I2C 1
I2C 0
PWM 1
PWM 0
Timer 2/3
Timer 0/1
UART 1
UART 0
SPI 1
SPI 0
I2S
SPI 2
SC 0/UART3
RTC
SC 1/UART4
WDT
GPIO
A,B,C,D,E,F
12-b ADC
12-b DAC
1.8/2.5V REF
Touch Key
LCD Booster
LCD
LCD COM/SEG
Up to
4x40/6x38
SC 2/UART5
Figure 4-2 NuMicro
TM
Page 45 of 72
Revision V1.00

Oct 11, 2012
TEMP Sensor
4.3

LXT
EBI
FLASH
123/64/
32 KB
Cortex-M0
42 MHz
DMA
CLK_CTL
P
L
L
LIRC
HXT
HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
BOD (1.7/2.0/2.5 V)
ISP 4KB
SRAM
16/8 KB
I2C 1
I2C 0
PWM 1
PWM 0
Timer 2/3
Timer 0/1
UART 1
UART 0
SPI 1
SPI 0
I2S
SPI 2
SC 0/UART3
RTC
SC 1/UART4
WDT
GPIO
A,B,C,D,E,F
12-b ADC
12-b DAC
1.8/2.5V REF
Touch Key
USB -512B
USB PHY
SC 2/UART5

Figure 4-3 NuMicro
Oct 11, 2012
TEMP Sensor
TM
Page 46 of 72
Revision V1.00
4.4

LXT
EBI
FLASH
123/64/
32 KB
Cortex-M0
42 MHz
DMA
CLK_CTL
P
L
L
LIRC
HXT
HIRC
1.8V LDO
(input: 1.8 ~ 3.6V)
POR (1.8V)
BOD (1.7/2.0/2.5 V)
GPIO
A,B,C,D,E,F
ISP 4KB
SRAM
16/8 KB
I2C 1
I2C 0
PWM 1
PWM 0
Timer 2/3
Timer 0/1
UART 1
UART 0
SPI 1
SPI 0
I2S
SPI 2
LCD
SC 0/UART3
RTC
USB -512B
SC 1/UART4
WDT
12-b ADC
12-b DAC
1.8/2.5V REF
Touch key
TEMP Sensor
LCD Booster
LCD COM/SEG
Up to
4x40/6x38
USB PHY
SC 2/UART5
Figure 4-4 NuMicro
Oct 11, 2012
TM
Peripherals with wake up
Page 47 of 72
Revision V1.00

APPLICATION CIRCUIT
5.1
5.1.1
LCD Charge Pump
C-type 1/3 Bias
0.1uF
VLC
D
DH
1
DH
2
NANO130
V3
V2
V1
5.1.2
0.1uF
0.1uF
0.1uF
0.1uF
C-type 1/2 Bias
0.1uF
DH
1
DH
2
Oct 11, 2012
NANO130
Page 48 of 72
VLC
D
0.1uF
V3
0.1uF
V2
0.1uF
V1
0.1uF
Revision V1.00
5.2
ADC Application Circuit
Voltage Reference Source
5.2.1
5.2.1.1
AVDD
NANO100
AVDD
AVDD
M ADC Vref
U
X
AVDD
VREF
REFSEL[1:0]
EXT_MODE=0
Int Vref
0.1uF
100nF
0.1uF
100nF
AVSS
REFSEL[1:0] of ADCR
00 AVDD as Voltage reference
01 Int. Vref as Voltage reference
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
10 Ext. VREF pin as Voltage reference

11 Reserve
5.2.1.2
Vref Pin
AVDD
M ADC Vref
U
X
VREF
VREF
REFSEL[1:0]
EXT_MODE=0
Int Vref
0.1uF
100nF
0.1uF
100nF
AVSS
REFSEL[1:0] of ADCR
NANO100
AVDD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11

11 Reserve
Oct 11, 2012
Page 49 of 72
Revision V1.00
5.2.1.3
Int Vref
NANO100
AVDD
AVDD
M ADC Vref
U
X
VREF
REFSEL[1:0]
EXT_MODE=1
Int Vref
0.1uF
100nF
0.1uF
100nF
AVSS
REFSEL[1:0] of ADCR
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11

11 Reserve
zz
Oct 11, 2012
Page 50 of 72
Revision V1.00
5.3
DAC Application Circuit
Voltage Reference Source
5.3.1
5.3.1.1
AVDD
NANO100
AVDD
AVDD
M
DAC Vref
U
X
AVDD
VREF
DAC1_out
REFSEL[1:0]
EXT_MODE=0
DAC2_out
Int Vref
0.1uF
100nF
0.1uF
100nF
AVSS
REFSEL[1:0] of DAC
5.3.1.2
Vref Pin
AVDD
M
DAC Vref
U
X
VREF
VREF
EXT_MODE=0
DAC1_out
REFSEL[1:0]
DAC2_out
Int Vref
0.1uF
100nF
0.1uF
100nF
AVSS
REFSEL[1:0] of DAC
Oct 11, 2012
Page 51 of 72
Revision V1.00
NANO100
AVDD
5.3.1.3
Int Vref
NANO100
AVDD
AVDD
M
DAC Vref
U
X
VREF
EXT_MODE=1
DAC1_out
REFSEL[1:0]
DAC2_out
Int Vref
0.1uF
100nF
0.1uF
100nF
AVSS
REFSEL[1:0] of DAC
Oct 11, 2012
Page 52 of 72
Revision V1.00
5.4
Whole Chip Application Circuit

DVDD
DVDD
DVDD
C15
0.1uF
C0603
CB4
100nF
C0603
Reset Circuit
C14
100nF
C0603
PE.14
PE.15
PB.8
PVSS
VSS
PF.5
PF.4
NC
VDD
NC
VSS
VSS
RESET
NC
XT1_Out
XT1_In
NC
PB.15
PC.14
PC.15
PC.6
PC.7
PD.5
PD.4
NC
PD.3
PD.2
PD.1
PD.0
AVDD
NC
VREF
U1
C13
0.1uF
C0603
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
PIN128
PIN127
PIN126
PIN125
PIN124
PIN123
PIN122
PIN121
PIN120
PIN119
PIN118
PIN117
PIN116
PIN115
PIN114
PIN113
PIN112
PIN111
PIN110
PIN109
PIN108
PIN107
PIN106
PIN105
PIN104
PIN103
PIN102
PIN101
PIN100
PIN99
PIN98
PIN97
C1
1uF/10V
TANT-A
XTAL2
XTAL1
CB3
0.1uF
C0603
TICE_RST
SW
PUSH BUTTON
TICE_RST
R1
100K
0603R
SW1
From ICE Bridge's USB Power

DVDD
2
4
6
8
10
TICE_DAT
TICE_CLK
TICE_RST
X32KO
X32KI
HEADER 5PX2
HEADER 5PX2
ICE Interface
C3
R2
XTAL2
20pF
0603C
C2
DVDD
X2
0
12MHz 0603R
XTAL3-1
1uF/10V
TANT-A
C5
XTAL1
20pF
0603C
C7
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
PIN8
PIN9
PIN10
PIN11
PIN12
PIN13
PIN14
PIN15
PIN16
PIN17
PIN18
PIN19
PIN20
PIN21
PIN22
PIN23
PIN24
PIN25
PIN26
PIN27
PIN28
PIN29
PIN30
PIN31
PIN32
DVDD
X32KO
X1
32.768KHz
XTAL3-1
CB2
0.1uF
C0603
C8
X32KI
PE.13
PB.14
PB.13
PB.12
NC
X32O
X32I
NC
PA.11
PA.10
PA.9
PA.8
PD.8
PD.9
PD.10
PD.11
PD.12
PD.13
PB.4
PB.5
PB.6
PB.7
NC
LDO
NC
NC
VDD
NC
VSS
VSS
VSS
VSS
PA.7
PA.6
PA.5
PA.4
PA.3
PA.2
PA.1
PA.0
AVSS
AVSS
VSS
VSS
NC
VDD
NC
ICE_CK/PF.1
ICE_DAT/PF.0
PA.12
PA.13
PA.14
PA.15
PC.8
PC.9
PC.10
PC.11
PC.12
PC.13
PE.0
PE.1
PE.2
PE.3
PE.4
NANO130_LQFP128
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PIN96
PIN95
PIN94
PIN93
PIN92
PIN91
PIN90
PIN89
PIN88
PIN87
PIN86
PIN85
PIN84
PIN83
PIN82
PIN81
PIN80
PIN79
PIN78
PIN77
PIN76
PIN75
PIN74
PIN73
PIN72
PIN71
PIN70
PIN69
PIN68
PIN67
PIN66
PIN65
DVDD
TICE_CLK
TICE_DAT
DVDD
CB5
0.1uF
C0603
PIN33
PIN34
PIN35
PIN36
PIN37
PIN38
PIN39
PIN40
PIN41
PIN42
PIN43
PIN44
PIN45
PIN46
PIN47
PIN48
PIN49
PIN50
PIN51
PIN52
PIN53
PIN54
PIN55
PIN56
PIN57
PIN58
PIN59
PIN60
PIN61
PIN62
PIN63
PIN64
10pF
0603C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PE.12
PE.11
PE.10
PE.9
PE.8
PE.7
NC
VBUS
VDD33
USB_DM
USB_DP
PB.0
PB.1
PB.2
PB.3
PD.6
PD.7
PD.14
PD.15
PC.5
PC.4
PC.3
PC.2
PC.1
PC.0
PE.6
VLCD
NC
PE.5
PB.11
PB.10
PB.9
1
3
5
7
9
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
JP4
10pF
0603C
C9
0.1uF
C0603
C10
1uF
C0603
C12
1uF
C0603
Crystal
Oct 11, 2012
Page 53 of 72
Revision V1.00
POWER COMSUMPTION
Part No
Nano100 (B)
series
128 KB Flash
16 KB RAM
Test Condition
VDD
CPU Clock
Current
Operating Mode:
CPU run while(1) in FLASH ROM
Clock = 12 MHz Crystal Oscillator
Disable all peripherial
3.3V
12MHz
2.41mA
200uA/MHz
1.8V
12MHz
N/A
Idle Mode:
CPU stop
Clock = 12MHz Crystal Oscillator
Disable all peripherial
3.3V
12MHz
900uA
75uA/MHz
1.8V
12MHz
N/A
3.3V
10uA
1.8V
3.3V
2.5uA
1.8V
N/A
RTC + LCD Mode: (RAM retention)

(Power down with 32K and LCD
enabled)
CPU stop
Clock = 32.768 kHz Crystal Oscillator
Disable all peripherial except RTC and
LCD circuit
Without panel loading
RTC Mode: (RAM retention)
(Power down with 32K enabled)
CPU stop
Clock = 32.768 kHz Crystal Oscillator
Disable all peripherial except RTC
circuit
3.3V
1uA
Power-down Mode: (RAM retention)

CPU and all clocks stop
1.8V
0.8uA
Wake-Up from Power-down Mode
3.3V
7us
Note: Wake-up time: 7us from wake-up event to first CPU core valid clock; 10us from interrupt event
to interrupt service routine first instruction.
Oct 11, 2012
Page 54 of 72
Revision V1.00
7
7.1
ELECTRICAL CHARACTERISTIC
Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN
MAX
UNIT
VDDVSS
-0.3
+4.0
Input Voltage on 5V Tolerance Pin
VIN
VSS -0.3
VDD +3.7
Input Voltage on Any Other Pin without 5V

Tolerance Pin
VIN
VSS -0.3
VDD +0.3
1/tCLCL
24
MHz
Operating Temperature
TA
-40
+85
Storage Temperature
TST
-55
+150
Maximum Current into VDD
150
mA
Maximum Current out of VSS
150
mA
Maximum Current sunk by a I/O Pin
25
mA
Maximum Current Sourced by a I/O Pin
25
mA
Maximum Current Sunk by Total I/O Pins
100
mA
Maximum Current Sourced by Total I/O Pins
100
mA
DC Power Supply
Oscillator Frequency
Oct 11, 2012
Page 55 of 72
Revision V1.00
7.2
Nano100/Nano110/Nano120/Nano130 DC Electrical Characteristics

(VDD-VSS=3.3V, TA = 25C, FOSC = 32 MHz unless otherwise specified.)
S SPECIFICATIONS
Y
M
MIN.
TYP. MAX. UNIT
.
PARAMETER
Operation voltage
Power Ground
VDD
1.8
-0.3
VLDO1
1.62
1.8
1.98
MCU operating in Run or Idle mode
VLDO2
1.49
1.66
1.83
MCU operating in Power-down mode
VSS
AVSS
3.6
TEST CONDITIONS
VDD =1.8V up to 32 MHz
Analog Operating
Voltage
Operating Current
AVDD
VDD
IDD1
19.5
mA
IDD2
10
mA
IDD3
15.5
mA
IDD4
mA
IDD5
mA
IDD6
2.5
mA
IDD7
5.5
mA
IDD8
2.4
mA
IDD9
6.7
mA
IDD10
2.9
mA
Run Mode
at XTAL 12MHz,
HCLK = 32 MHz
Operating Current
Run Mode
at XTAL 12MHz,
HCLK = 12MHz
Operating Current
Run Mode
at IRC 12MHz,
HCLK = 12MHz
VDD = 3.6V at 32 MHz,

all IP and PLL enabled
VDD = 3.6V at 32 MHz
all IP disabled and PLL enabled
all IP enabled and PLL disabled
all IP and PLL disabled
VDD = 3.6V at 12MHz,
LDO Output Voltage
S SPECIFICATIONS
Y
M
MIN.
TYP. MAX. UNIT
.
PARAMETER
Operating Current
6.4
mA
IDD12
2.8
mA
IDD13
2.3
mA
IDD14
1.2
mA
IDD15
2.2
mA
IDD16
1.1
mA
IDD17
90
uA
IDD18
80
uA
IDD19
75
uA
IDD20
72
uA
IDD21
80
uA
IDD22
75
uA
IDD23
67
uA
IDD24
65
uA
IIDLE1
14
mA
IIDLE2
4.5
mA
Run Mode
at XTAL 4MHz,
HCLK = 4MHz
Operating Current
Run Mode
at XTAL 32.768 kHz,
HCLK = 32.768 kHz
Operating Current
Run Mode
at IRC 10kHz,
HCLK = 10kHz
Operating Current
Idle Mode
at XTAL 12 MHz,
HCLK = 32 MHz
Oct 11, 2012
Page 57 of 72

VDD = 3.6V at 32.768 kHz
all IP enabled and PLL disabled,
VDD = 3.6V at 32.768 kHz
VDD = 1.8V at 32.768 kHz
VDD = 1.8V at 32.768 kHz
VDD = 3.6V at 10 kHz
VDD= 3.6V at 32 MHz
all IP and PLL enabled,
VDD=3.6V at 32 MHz
Revision V1.00
IDD11
TEST CONDITIONS
S SPECIFICATIONS
Y
M
MIN.
TYP. MAX. UNIT
.
PARAMETER
Operating Current
IIDLE3
11.7
mA
IIDLE4
4.3
mA
IIDLE5
3.6
mA
IIDLE6
0.8
mA
IIDLE7
3.5
mA
IIDLE8
0.75
mA
IIDLE9
4.7
mA
IIDLE10
0.9
mA
IIDLE11
4.6
mA
IIDLE12
0.8
mA
IIDLE13
1.72
mA
IIDLE14
0.6
mA
IIDLE15
1.6
mA
IIDLE16
0.6
mA
IIDLE17
85
uA
IIDLE18
75
uA
Idle Mode
at XTAL 12MHz,
HCLK = 12MHz
Operating Current
Idle Mode
at IRC 12MHz,
HCLK = 12MHz
Operating Current
Idle Mode
at XTAL 4MHz,
HCLK = 4MHz
Operating Current
Idle Mode
at XTAL 32.768 kHz,
HCLK = 32.768 kHz
Oct 11, 2012
Page 58 of 72
TEST CONDITIONS
VDD = 1.8V at 32MHz

VDD = 3.6V at 32.768 kHz
VDD = 3.6V at 32.768 kHz
Revision V1.00
S SPECIFICATIONS
Y
M
MIN.
TYP. MAX. UNIT
.
PARAMETER
Operating Current
IIDLE19
70
uA
IIDLE20
65
uA
IIDLE21
80
uA
IIDLE22
75
uA
IIDLE23
65
uA
IIDLE24
63
uA
IPWD1
1.5
IPWD2
0.8
IPWD3
Idle Mode
at IRC 10 kHz,
HCLK = 10 kHz
Standby Current
Power-down Mode
TEST CONDITIONS
VDD = 1.8V at 32.768 kHz

VDD = 1.8V at 32.768 kHz
VDD = 3.6V, RTC OFF, all clock stop
With RAM Retenstion, IO no loading
VDD = 1.8V, RTC OFF, all clock stop
VDD = 3.6V, RTC ON, all clock stop
except 32.768 kHz
IPWD4
2.0
VDD = 1.8V, RTC ON, all clock stop

except 32.768 kHz
Input Pull Up Resistor

PA, PB, PC, PD, PE,
PF
RIN
Input Leakage Current

PA, PB, PC, PD, PE,
PF
ILK
Input Low Voltage PA,

PB, PC, PD, PE, PF
-0.1
VIL1
40
VDD = 3.3V
98
VDD = 1.8V
VDD = 3.3V, 0<VIN<VDD
+0.1
0.4VDD
5.5
(Schmitt input)
Input High Voltage PA,
PB, PC, PD, PE, PF
VIH1
0.6VDD
(Schmitt input)
Hysteresis voltage of
PA~PF (Schmitt input)
Oct 11, 2012
VHY
0.2VDD
Page 59 of 72
ADC and DAC shared pins without Input

5V tolerance.
Revision V1.00
S SPECIFICATIONS
Y
M
MIN.
TYP. MAX. UNIT
.
PARAMETER
TEST CONDITIONS
Input Low Voltage

[*2]
XT1
VIL2
0.4
Input High Voltage

[*2]
XT1
VIH2
1.5
VDD
+0.2
Input Low Voltage

[*2]
X32I
VIL4
0.3
Input High Voltage

[*2]
X32I
VIH4
1.5
1.98
VILS
1.28
1.33
1.37
VDD = 3.3V
VIHS
1.75
1.98
2.25
VDD = 3.3V
Source Current PA,

PB, PC, PD, PE, PF
ISR21
-10
-14
mA
(Push-pull Mode)
ISR22
-3
-5
mA
Sink Current PA, PB,

PC, PD, PE, PF
ISK1
10
15
mA
(Push-pull Mode)
ISK1
mA
Negative going
threshold
(Schmitt input),
/RESET
Positive going
threshold
(Schmitt input),
/RESET
VDD = 3.3V
VDD = 3.3V
VDD = 3.3V,
VS = Vdd-0.7V
VDD = 1.8V,
VS = Vdd-0.45V
VDD = 3.3V,
VS = 0.7V
VDD = 1.8V,
VS = 0.45V
Note:
1.
/RESET pin is a Schmitt trigger input.
2.
Crystal Input is a CMOS input.
3.
It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are connected between VDD and
the closest VSS pin of the device.
4.
For ensuring power stability, a 4.7uF or higher capacitor must be connected between LDO pin and the closest VSS
pin of the device. Also a 100nF bypass capacitor between LDO and VSS help suppressing output noise
Oct 11, 2012
Page 60 of 72
Revision V1.00
7.3
AC Electrical Characteristics
7.3.1
External Input Clock

SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
tCHCX
20
nS
Clock Low Time
tCLCX
20
nS
Clock Rise Time
tCLCH
10
nS
Clock Fall Time
tCHCL
10
nS
Clock High Time
MAX. UNIT
t CLCL
t CLCX
tCHCL
7.3.2
t CHCX
External 4~24 MHz XTAL Oscillator

SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
fHXTAL
12
24
Temperature
THXTAL
-40
+85
Operating current
IHXTAL
Oscillator frequency
7.3.2.1
0.3
MAX. UNIT
MHz
o
VDD = 1.8V ~ 3.6V
C
VDD = 3.0V
mA
Typical Crystal Application Circuits

CRYSTAL
4MHz ~ 24 MHz
C1
C2
Optional(Depend on crystal specification)
C1
XTAL IN
R
C2
XTAL OUT
Figure 7-1 Typical Crystal Application Circuit
R
without
t CLCH
7.3.3
External 32.768 kHz Crystal

SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
Oscillator frequency
fLXTAL
Temperature
TLXTAL
Operating current
IHXTAL
7.3.4
TYP.
MAX.
32.768
-40
UNIT
kHz
+85
VDD = 1.8V ~ 3.6V
1.2
VDD = 3.0V
Internal 12 MHz Oscillator

SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
Supply voltage
[1]
Calibrated Internal Oscillator

Frequency
VHRC
MAX.
1.8
UNIT
V
o
11.88
12
12.12
MHz 25 C, VDD = 3V
11.76
12
12.24
MHz -40 C~+85 C, VDD = 1.8V~3.6V
FHRC
11.97
Operating current
TYP.
IHRC
12
12.03
TBD
-40 C~+85 C, VDD = 1.8V~3.6V

MHz Enable 32.768K crystal oscillator
and set TRIM_SEL[1:0]=10
mA
Note: Internal oscillator operation voltage comes from LDO.
7.3.5
Internal 10 kHz Oscillator

SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
Supply voltage
[1]
Center Frequency
Operating current
VLRC
FLRC
ILRC
TYP.
MAX.
1.8
UNIT
V
o
10
13
kHz
25 C, VDD = 3V
10
15
kHz
-40 C~+85 C, VDD = 1.8V~3.6V
VDD = 3V
0.7
Note: Internal oscillator operation voltage comes from LDO.
Oct 11, 2012
Page 62 of 72
Revision V1.00
7.4
Analog Characteristics
7.4.1
12-bit ADC
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
3.6
Operating voltage
AVDD
Operating current
IADC
Resolution
RADC
Reference voltage
VREF
Reference input current (Avg.)
IREF
ADC input voltage
VIN
Conversion time
TCONV
0.5
Sampling Rate
FSPS
Integral Non-Linearity Error
INL
Differential Non-Linearity
DNL
0.8
Gain error
EG
LSB VREF is external Vref pin
Offset error
EOFFSET
Absolute error
EABS
ADC Clock frequency
FADC
TBD
42
MHz
ADCYC
20
CIN
Internal Capacitance
Monotonic
7.4.2
TBD
mA AVDD = VDD = 3.0V
1.8
12
Bit
AVDD
V
A
TBD
VREF
V
S
2M
AVDD = VDD
Hz
VDD = 3V
-1~+1.5 LSB VREF is external Vref pin
Cycle
5
Guaranteed
pF
-
Brown-out Detector
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
3.6
Operating voltage
VBOD
BOD17 Quiescent current
IBOD17
TBD
AVDD = 3.0V, BOD17 enabled
IBOD20
TBD
IBOD25
TBD
BOD17 detection level
VB17dt
1.6
1.7
1.8
25 C
VB20dt
1.9
2.0
2.1
25 C
VB25dt
2.4
2.5
2.6
25 C
1.8
o
o
o
Clock cycle
1.8
7.4.3
Power-on Reset
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Reset voltage
VPOR
1.6
Quiescent current
IPOR
nA
7.4.4
LDO output > Reset voltage
Temperature Sensor
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
o
Detection Temperature
TDET
-40
Operating current
ITEMP
Gain
VTG
-1.73
mV/
o
C
Offset
VTO
740
mV Tempeature at 0 C
+125
Note: Internal operation voltage comes form LDO.
7.4.5
12-bit DAC
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
Operating voltage
AVDD
Operating current
IDAC
Resolution
RADC
Reference voltage
VREF
Reference input current (Avg.)
IREF
DAC output swin range
VOUT
Conversion Rate (code to

adjacent code)
FSPS
Integral Non-Linearity Error
INL
Differential Non-Linearity
TYP.
2.0
MAX.
UNIT
3.6
AVDD = VDD
AVDD = VDD = 3.0V
500
1.8
12
Bit
AVDD
V
A
TBD
0.9 x
VREF
400
kHz
VDD = 3V
TBD
LSB
VREF is external Vref pin

Not include offset and gain error
DNL
TBD
LSB
VREF is external Vref pin

Not include offset and gain error
Gain error
EG
TBD
LSB
Offset error
EOFFSET
TBD
LSB
Oct 11, 2012
0.1 x
VREF
Page 64 of 72
Revision V1.00
7.4.6
LCD
SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
VDD
1.8
3.6
VLCD voltage
VLCD34
3.4
CPUMP_VOL_SET=111, no loading
Reset voltage
VLCD33
3.3
Reset voltage
VLCD32
3.2
Reset voltage
VLCD31
3.1
Reset voltage
VLCD30
3.0
Reset voltage
VLCD29
2.9
Reset voltage
VLCD28
2.8
Reset voltage
VLCD27
2.7
ILCD
10
VDD = 3V, frame rate = 32Hz

Without loading
Operating voltage
Operating current
7.4.7
Touch Key (TK)

SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
VDD
1.8
3.6
Operating current
ITK
TBD
FTKOSC
10
MHz
TK oscillator frequency
Oct 11, 2012
Page 65 of 72
Operating voltage
VDD = 3V
Revision V1.00
7.4.8
Internal Voltage Reference

SPECIFICATIONS
PARAMETER
SYM.
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Operating voltage
AVDD
1.8
3.6
1.8V voltage reference
VREF1
1.8
AVDD >= 2.0V
2.5V voltage reference
VREF2
2.5
AVDD >= 2.8V
TREFTAB
ms
IVREF
30
Stable Time
Operating current
7.4.9
AVDD = 3V
USB PHY Specifications
7.4.9.1
USB PHY DC Electrical Characteristics
SYMBOL
PARAMETER
VIH
Input high (driven)
VIL
Input low
VDI
Differential input sensitivity
VCM
VSE
CONDITION
MIN.
TYP.
2.0
Differential
common-mode range
MAX.
UNIT
V
0.8
|PADP-PADM|
0.2
Includes VDI range
0.8
2.5
0.8
2.0
Single-ended receiver threshold

Receiver hysteresis
200
mV
VOL
Output low (driven)
0.3
VOH
Output high (driven)
2.8
3.6
VCRS
Output signal cross voltage
1.3
2.0
RPU
Pull-up resistor
1.425
1.575
RPD
Pull-down resistor
14.25
15.75
VTRM
Termination Voltage for

upstream port pull up (RPU)
3.0
3.6
ZDRV
Driver output resistance
Steady state drive*
10
CIN
Transceiver capacitance
Pin to GND
20
pF
TYP.
MAX.
UNIT
*Driver output resistance doesnt include series resistor resistance.
7.4.9.2
USB PHY Full-Speed Driver Elevtrical Characteristics
SYMBOL
Oct 11, 2012
PARAMETER
CONDITION
Page 66 of 72
MIN.
Revision V1.00
TFR
Rise Time
CL=50p
20
ns
TFF
Fall Time
CL=50p
20
ns
TFRFF
Rise and fall time matching
TFRFF=TFR/TFF
90
111.11
CONDITION
MIN.
TYP.
MAX.
UNIT
7.4.9.3 USB PHY Power Dissipation

SYMBOL
IVDDREG
(Full
Speed)
PARAMETER
VDDD and VDDREG Supply

Current (Steady State)
Standby
50
uA
Input mode
TBD
uA
Output mode
TBD
uA
7.4.9.4 USB LDO DC Electrical Characteristics

SYMBOL
PARAMETER
CONDITION
MIN.
VBUS
TYP.
MAX.
V33
Output voltage
Iop
Operation Current
VBUS = 5V, 25 C
2.97
3.3
TBD
UNIT
V
3.63
V
uA
Oct 11, 2012
Page 67 of 72
Revision V1.00
8
8.1
PACKAGE DIMENSIONS
128L LQFP (14x14x1.4 mm footprint 2.0 mm)
Oct 11, 2012
Page 68 of 72
Revision V1.00
8.2
Oct 11, 2012
Page 69 of 72
Revision V1.00
Oct 11, 2012
Page 70 of 72
Revision V1.00
8.3
Oct 11, 2012
Page 71 of 72
Revision V1.00
REVISION HISTORY
Date
2012.10.11
Revision Description
V1.00
Formal release
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, Insecure Usage.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customers risk, and in the event that third parties lay
claims to Nuvoton as a result of customers Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Oct 11, 2012
Page 72 of 72
Revision V1.00

NuMicro Nano100 (B) Series Product Brief en V1.00

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NUMICRO NANO100 TECHNICAL REFERENCE MANUAL

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NUMICRO NANO100 TECHNICAL REFERENCE MANUAL