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Republic of the Philippines

Mindanao State University - Iligan Institute of Technology

College of Engineering
Tibanga, 9200 Iligan City, P.O. Box No.5644 Tel. Nos. (063) 221-4050 Loc.130
Direct line (063) 2351E-mail:fbalagao@yahoo.com
Homepage:http://www.msuiit.edu.ph/coe

WRITTEN REPORT on

Logic Gate: Inverter


In partial fulfillment for the course
EE 177.1 (Logic Circuit and Switching Theory Laboratory)

Date:
Time:

December 1, 2014
1:00 PM 4:00 PM

Reported by:
Michael Lance Mioza

Submitted to:
Prof. Jeffrey C. Pasco

LOGIC GATE: INVERTER

I. Objectives

To study the basic logic gate: inverter, its representation by truth table, logic diagram
and Boolean algebra

To familiarize with the Quartus II computer-aided design tool in the inverter simulation.

To observe the pulse response of the inverter.

II. Materials
Computer
Quartus II Web Edition
III. Basic Concepts
Boolean algebra
In mathematics and mathematical logic, Boolean algebra is the subarea of algebra in
which the values of the variables are the truth values true and false, usually denoted 1 and 0
respectively. Instead of elementary algebra where the values of the variables are numbers, and
the main operations are addition and multiplication, the main operations of Boolean algebra
are the conjunction and, denoted , the disjunction or, denoted , and the negation not,
denoted . It is thus a formalism for describing logical relations in the same way that ordinary
algebra describes numeric relations. [1]
Logic Gate
In electronics, a logic gate is an idealized or physical device implementing a Boolean
function; that is, it performs a logical operation on one or more logical inputs, and produces a
single logical output. Depending on the context, the term may refer to an ideal logic gate, one
that has for instance zero rise time and unlimited fan-out, or it may refer to a non-ideal physical
device.

Logic gates are primarily implemented using diodes or transistors acting as electronic switches,
but can also be constructed using electromagnetic relays (relay logic), logic, pneumatic
logic, optics, molecules, or even mechanical elements. With amplification, logic gates can be
cascaded in the same way that Boolean functions can be composed, allowing the construction
of a physical model of all of Boolean logic, and therefore, all of the algorithms
and mathematics that can be described with Boolean logic. [2]
Inverter
In digital logic, an inverter or NOT gate is a logic gate which implements logical
negation.
An inverter circuit outputs a voltage representing the opposite logic-level to its input.
Inverters can be constructed using a single NMOS transistor or a single PMOS transistor coupled
with a resistor. Since this 'resistive-drain' approach uses only a single type of transistor, it can
be fabricated at low cost. However, because current flows through the resistor in one of the
two states, the resistive-drain configuration is disadvantaged for power consumption and
processing speed. Alternatively, inverters can be constructed using two complementary
transistors in a CMOS configuration. This configuration greatly reduces power consumption
since one of the transistors is always off in both logic states. Processing speed can also be
improved due to the relatively low resistance compared to the NMOS-only or PMOS-only type
devices. Inverters can also be constructed with bipolar junction transistors (BJT) in either
a resistortransistor logic (RTL) or a transistortransistor logic (TTL) configuration. [3]
An inverter can be classified according to its purpose and also can be easily identified in
diagram with its unique design. Logic gate inverter has a tiny circle (o) located either in the
input(s) or output(s). In Fig 1.b, the circle is clearly located on the output of the logic gate.

Input Output
1

Fig 1.a Truth Table of an Inverter (Binary)

Fig 1.b Graphical Diagram for Inverter


IV. Procedure

Download and install Quartus II (Web Edition)

Open Quartus II (Web Edition)

Located on the upper left corner, click File>New Project Wizard and follow the
instructions.

Series of windows will show after the clicking New Project Wizard
o Directory, Name, Top-Level Entity (1/5)

Select your location in which your project will be saved.

Choose a name for your project.

o Add files (2/5) you can skip this part.


o Family and Device Settings (3/5)

Under the Family choose

o EDA Tool Settings (4/5) you can skip this part.


o Summary (5/5)

Click Finish.

Go to Assignments>Settings>EDA Tool Settings>Simulation>More EDA Netlist Writer


Settings>Generate netlist for simulation only and turn it on>Location of user compiled
simulation library and then assign the location by just using the location where you
saved your project earlier>Ok>More NativeLink Settings and make sure that the location
of user compiled simulation library is the same with the previous one>Ok.

Start entering schematic design. Go to File>New>Block Diagram/Schematic File>OK

Double click on the blank space and a window will appear. Go to primitives>logic>not.
This will enable you to add a NOT logic gate to your workspace the press ESC.

Add one input and one output by double-clicking an empty area in the workspace and
go to pin and choose input and output. Put the input on the left side of the gate and the
ouput on the right side.

Connect all the components by hovering your cursor to the rightmost part of the input.
The cursor will turn into a crosshair which enables you to create a wire, connect it to the
terminal of the NOT gate. Do the same for the output pin.

Save your work and start compiling by going to Processing>Start Compilation. It will take
few minutes to compile and a dialog will pop-out to confirm successful compilation.

Save your work by pressing CTRL+S.

Open the ModelSim-Altera program to create a wave-form diagram for the schematic
circuit you have made in your Quartus II.

Go to File>New>Project. Enter the location in which you have saved your recent work
and click OK.

The program will ask if you want to add your project. Click Add Existing File> Browse and
find your output netlist file. Then add the VHO file and click Open.

Right click on you VHO file and choose Compile.

Click on Simulate>Start Simulation>work>Click on your netlist file>Ok.

Go to Objects and select all your input and ouput then right click>Add>To
wave>Selected Signals

All your selected signals are now moved to Wave window.

Right click on the input signal>Clock>Set the Period to be 50>Ok.

Press F9 to run the simulation.

V. Data and Graphs

Fig 1.c Schematic diagram of an inverter using Quartus II Web Edition

Fig 1.d Wave generated of the schematic diagram inverter using ModelSim-Altera

VI. Conclusion
An inverter is also called the NOT logic gate and it is the simplest logic gate. Its sole
purpose is to negate all incoming signal. If the input is 0 and pass through an inverter, the
signal will now be a negation of 0 or NOT 0 which will be 1. It is clearly shown in the
ModelSim-Altera, the input is shown in HIGH and LOW. Whenever the input is HIGH the output
is LOW and vice versa.

REFERENCES
[1] http://en.wikipedia.org/wiki/Boolean_algebra
[2] http://en.wikipedia.org/wiki/Logic_gate
[3] http://en.wikipedia.org/wiki/Inverter_(logic_gate)