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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 11, NOVEMBER 2014
I. I NTRODUCTION
0018-9383 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 11, NOVEMBER 2014
Fig. 4.
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Fig. 8. Illustration of 3-D architecture that has an NVM plane above the
logic plane.
Fig. 6.
Fig. 7.
Low-temperature transfer characteristics compared with roomtemperature results and output characteristics (inset).
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W Cox VDS
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 11, NOVEMBER 2014