ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers

ASIC-System on Chip-VLSI Design

Digital chip design articles, tutorials, classes and news

Home

Links

Verilog

Low Power VLSI

Static Timing Analysis

Physical Design

Synthesis

DFT

Formal Verification

Backend (Physical Design) Interview Questions and

Answers
Below are the sequence of questions asked for a physical design engineer.

In which field are you interested?

Answer to this question depends on your interest, expertise and to the requirement for which you
have been interviewed.
Well..the candidate gave answer: Low power design
file:///C|/Users/COMSOL/Desktop/ASIC-System%20on%20Chip-VLSI%20Design%20%20Backend%20(Physical%20Design)%20Interview%20Questions%20and%20Answers.htm[7/17/2014 10:14:34 AM]

ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers

Can you talk about low power techniques?

How low power and latest 90nm/65nm technologies are related?
Refer here and browse for different low power techniques.
Do you know about input vector controlled method of leakage reduction?
Leakage current of a gate is dependant on its inputs also. Hence find the set of inputs which gives
least leakage. By applyig this minimum leakage vector to a circuit it is possible to decrease the
leakage current of the circuit when it is in the standby mode. This method is known as input vector
controlled method of leakage reduction.

WRITE TO ASICSOCBLOG
Send your comments, suggestions, guest articles,
thesis, research papers to: asicsocblog@gmail.com

To subscribe asic-soc blog enter your email

address:

How can you reduce dynamic power?

-Reduce switching activity by designing good RTL
-Clock gating

Subscribe

-Architectural improvements
-Reduce supply voltage
file:///C|/Users/COMSOL/Desktop/ASIC-System%20on%20Chip-VLSI%20Design%20%20Backend%20(Physical%20Design)%20Interview%20Questions%20and%20Answers.htm[7/17/2014 10:14:34 AM]

ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers

-Use multiple voltage domains-Multi vdd

What are the vectors of dynamic power?
Voltage and Current
How will you do power planning?
Refer here for power planning.
If you have both IR drop and congestion how will you fix it?
-Spread macros
-Spread standard cells
-Increase strap width
-Increase number of straps
-Use proper blockage
Is increasing power line width and providing more number of straps are the only solution
to IR drop?
-Spread macros
-Spread standard cells
-Use proper blockage
In a reg to reg path if you have setup problem where will you insert buffer-near to
launching flop or capture flop? Why?
(buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise
we try to fix setup voilation with the sizing of cells; now just assume that you must insert buffer !)
Near to capture path.
Because there may be other paths passing through or originating from the flop nearer to lauch flop.
Hence buffer insertion may affect other paths also. It may improve all those paths or degarde. If all
those paths have voilation then you may insert buffer nearer to launch flop provided it improves
slack.
How will you decide best floorplan?
Refer here for floor planning.
What is the most challenging task you handled?
What is the most challenging job in P&R flow?
-It may be power planning- because you found more IR drop
-It may be low power target-because you had more dynamic and leakage power
-It may be macro placement-because it had more connection with standard cells or macros
-It may be CTS-because you needed to handle multiple clocks and clock domain crossings
-It may be timing-because sizing cells in ECO flow is not meeting timing
-It may be library preparation-because you found some inconsistancy in libraries.
-It may be DRC-because you faced thousands of voilations

Top Posts
What is the difference between FPGA and ASIC?
This question is very popular in VLSI fresher
interviews. It looks simple but a deeper insight
into the subject reveals the fact that the...
Companywise ASIC/VLSI Interview Questions
Senior Physical design engineer position, Below
interview questions are contributed by
ASIC_diehard (Thanks a lot !). Be...
Process-Voltage-Temperature
(PVT) Variations and Static
Timing Analysis
The major design challenges of
ASIC design consist of
microscopic issues and
macroscopic issues [1]. The microscopic issues
are ultra-high s...
Backend (Physical Design) Interview Questions
and Answers
Below are the sequence of questions asked for a
physical design engineer. In which field are you
interested? Answer to this question...
Clock Gating
Clock tree consume more than 50
% of dynamic power. The
components of this power are: 1)
Power consumed by
combinatorial log...
Clock Definitions
lock Definitions: Rising and falling
edge of the clock For a +ve edge
triggered design +ve (or rising)
edge is called ...
Setup and hold slack
13. Setup and hold slack Slack
Slack is defined as difference
between actual or achieved time
and the desired time for a timing
...
Embedded System for Automatic
Washing Machine using Microchip
PIC18F Series Microcontroller
The design uses the PIC18F
series microcontroller. All the
control functionalities of the
system are built around this. Upgradeability is
th...
What is the difference between FPGA and
CPLD?
FPGA-Field Programmable Gate Array and
CPLD-Complex Programmable Logic Device-both are programmable logic devices made by

file:///C|/Users/COMSOL/Desktop/ASIC-System%20on%20Chip-VLSI%20Design%20%20Backend%20(Physical%20Design)%20Interview%20Questions%20and%20Answers.htm[7/17/2014 10:14:34 AM]

ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers

How will you synthesize clock tree?

the same compani...

Constraints: Clock, Logical DRC,
Area, Power
14. Constraints: Clock, Logical
DRC, Area, Power Design
constraints are generally specified
in Synopsys Design Constraints

-Single clock-normal synthesis and optimization

-Multiple clocks-Synthesis each clock seperately
-Multiple clocks with domain crossing-Synthesis each clock seperately and balance the skew
How many clocks were there in this project?

...

-It is specific to your project

-More the clocks more challenging !
How did you handle all those clocks?

Search

-Multiple clocks-->synthesize seperately-->balance the skew-->optimize the clock tree

Read More...

Are they come from seperate external resources or PLL?

-If it is from seperate clock sources (i.e.asynchronous; from different pads or pins) then balancing
skew between these clock sources becomes challenging.
-If it is from PLL (i.e.synchronous) then skew balancing is comparatively easy.
Why buffers are used in clock tree?
To balance skew (i.e. flop to flop delay)
What is cross talk?
Switching of the signal in one net can interfere neigbouring net due to cross coupling
capacitance.This affect is known as cros talk. Cross talk may lead setup or hold voilation.
How can you avoid cross talk?
-Double spacing=>more spacing=>less capacitance=>less cross talk
-Multiple vias=>less resistance=>less RC delay
-Shielding=> constant cross coupling capacitance =>known value of crosstalk
-Buffer insertion=>boost the victim strength
How shielding avoids crosstalk problem? What exactly happens there?
-High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded layers are connected to
either VDD or VSS.
Coupling capacitance remains constant with VDD or VSS.
How spacing helps in reducing crosstalk noise?
width is more=>more spacing between two conductors=>cross coupling capacitance is less=>less
cross talk
Why double spacing and multiple vias are used related to clock?
Why clock?-- because it is the one signal which chages it state regularly and more compared to

There was an error in

this gadget

Verilog
(38)
Synthesis (36)
ASIC
synthesis (34)
Verilog HDL
(34)
verilog
examples (32)
verilog
interview
questions (30)
verilog
tutorials (29)
Verification
(28)
verilog
tutorial
for
beginners (28)
ASIC (26) DSP
(22) HDL (19) Low
Power Techniques
(16) logic synhesis
(16) FPGA (15)
MATLAB
(15)
Static
Timing
Analysis (STA) (15)
Timing
Analysis
(15) logic synthesis
(13)
Mentor
Graphics
(12)
Verification IP (12)
Physical
Design
(11) DSP filters (10)
Digital

design

(9)

Blog Archive
2014 (1)
2013 (58)
2012 (21)
2011 (7)
2010 (2)
2009 (14)
2008 (36)
December 2008
(1)
November 2008
(1)
October 2008 (1)
September 2008
(1)
August 2008 (1)
July 2008 (1)
June 2008 (7)
May 2008 (1)
April 2008 (13)
March 2008 (4)
PVT, Derarting
and STA
Leakage Power
Trends
Process-VoltageTemperature
(PVT)
Variations and

file:///C|/Users/COMSOL/Desktop/ASIC-System%20on%20Chip-VLSI%20Design%20%20Backend%20(Physical%20Design)%20Interview%20Questions%20and%20Answers.htm[7/17/2014 10:14:34 AM]

ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers

any other signal. If any other signal switches fast then also we can use double space.
Double spacing=>width is more=>capacitance is less=>less cross talk
Multiple vias=>resistance in parellel=>less resistance=>less RC delay

How buffer can be used in victim to avoid crosstalk?

Buffer increase victims signal strength; buffers break the net length=>victims are more tolerant to
coupled signal from aggressor.

CMOS
(8)
Verilog
Classes
(8)
Asynchronous
FIFO
(7) 3-D ICs (6) Basic
gates using MUX (6)
Digital filters (6) PIC
Microcontroller (6) low
power (6) .lib (5)
Libraries
(5)
PIC
16F877A (5) interview
(5) Leakage Power (4)
VIP (4) VLSI (4) Design
For Test-DFT (3) Multi
Vdd (3) Multi Vt (3)
Power
Planning
(3)
Reconfigurable
Computing (3) System
on Chip (3) hold time (3)
operating Condition (3)
setup time (3) ASIC
syynthesis (2)
Clock
Tree Synthesis (CTS) (2)
DVFS (2) Design For
Test (DFT) (2) EDA (2)
Floorplanning (2) Full
Custom (2) New Devices
(2) OVM (2) Placement
(2) RTL (2) SPICE (2)
SRAM cell design (2)
Semi Custom (2) SoC
Design
(2)
SoC
Integration (2) Synopsys
(2) Timing paths (2)
Transition delay (2) UVM
(2) constraints (2) layout
(2) 5.2.8. Blocking vs non-

Tags: Physical Design, Synthesis, Timing Analysis

1 comment:
VARAHA NAGESWARARAO May 23, 2014 at 3:42 PM
Good for knowledge
Reply

Add comment

Your Comments... (comments are moderated)

S...
Backend
(Physical
Design)
Interview
Questions and
...
February 2008
(2)
January 2008 (3)
2007 (109)

There was an error in

this gadget

blocking-race condition (1)

7

Segment

Display

(1)

AMBA AHB (1) AMBA APB

(1) AMBA AXI (1) AMBA
Bus

(1)

Basic

Microelectronics
Blocking
(1)

CMOS

Clock

Comment as:

(1)

Vs Nonblocking
Design

Gating

(1)

(1)
Clock

Logic (1) Clock definitions

(1)

Congestion

(1)

CoreConnect Bus (1) DFT

Publish

Preview

Notify me

(1) DTMF (1) Deep Sub

Micron Issues (1) Delays
(1)

Design

For

Manufacture-DFM

(1)

Dynamic

Power

(1)

Embedded

Systems

(1)

Embedded etc (1) FFT (1)

FIR Filter (1) FSM

(1)

file:///C|/Users/COMSOL/Desktop/ASIC-System%20on%20Chip-VLSI%20Design%20%20Backend%20(Physical%20Design)%20Interview%20Questions%20and%20Answers.htm[7/17/2014 10:14:34 AM]

ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers
Finite State Machine (1)
Gate Delay (1) History of
VLSI (1) IC Fabrication (1)
IP Cores (1) IPs (1) Intel
(1)

Internal

Power

Intrinsic Delay

(1)

(1)
Lynx

Design System (1) Magma

(1)

Memory

Design

Microprocessors

Newer Post

Home

Older Post

(1)
(1)

Monitors (1) Nangate 45nm

cell libraries (1) Net delay
(1) NoC (1) OpenSPARC

Subscribe to: Post Comments (Atom)

processor (1) Others ..DSP

(1) PVT vs STA (1) Power

Search This Blog

Gating

(1)

Propagation

delay (1) Protocols (1) RTL

Loading...

Coding (1) Reset Logic (1)

Routing (1) SDC (1) SRAM
Chip (1) STA (1) Short
Circuit Power (1)

Static

memory design (1) Sub

Threshold
Systolic

Leakage
Array

fabrication
Scaling

(1)

(1)
(1)

(1)
VLSI

Voltage

WLM

(1)

Washing Machine (1) Wire

load

models

(1)

free

download of processor (1)

jitter (1) latency (1) optical
lithography (1) optimization
(1) process variation (1)
skew (1) transition fixing
(1) transition violation (1)
uncerainty (1)

Copyright/Disclaimer

Listed in

This work is licensed under a Creative Commons

Attribution-Share Alike 2.5 India License.

"Nahi Jnanena Sadrusham". Simple template. Powered by Blogger.

file:///C|/Users/COMSOL/Desktop/ASIC-System%20on%20Chip-VLSI%20Design%20%20Backend%20(Physical%20Design)%20Interview%20Questions%20and%20Answers.htm[7/17/2014 10:14:34 AM]

ASIC-System on Chip-VLSI Design: Backend (Physical Design) Interview Questions and Answers

file:///C|/Users/COMSOL/Desktop/ASIC-System%20on%20Chip-VLSI%20Design%20%20Backend%20(Physical%20Design)%20Interview%20Questions%20and%20Answers.htm[7/17/2014 10:14:34 AM]