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I. INTRODUCTION
Last generation of Microprocessors and DSPs require high
current slew rates, fast transient response together with low
output voltage [1]. Different solutions have been presented in
recent years [2-3]. Regarding with the transient response, some
of them are based on improving the linear control [4] and other
solutions introduce the non-linear control. Among the nonlinear solutions two different ways can be distinguished. Those
in which the non-linear control operates all the time like
hysteresis control and V2 control [5], and those in which the
non-linear control works in a short period of time. Finally, this
last way can be implemented either modifying the power block
[6] or modifying the control gain [7].
1329
Vi
L
(d (t ) D ) dt
M1
(1)
V0
Vi
+
-
M2
Driver
Z2
_
Q
Pulse Modulator
Comp.
Io
R
1
1
D0
DL
D0
IL
IL
ULT
V0
VRef
Threshold
Logic
ULT
UHT
Non-Linear Control
(a)
UHT
(b)
IL
t=0
+
Error Amp.
Linear Control
Duty Cycle
Saturation
Logic
0
Z1
_+
(d (t ) D0 )dt
d(t)
L/NL
DH
Q
S
Multiplexor
d(t)
1
Ro
+
_
I L (t ) =
Fig. 3), the Threshold Logic block set the multiplexer selection
input (L/NL) to 0 and the linear control regulates the converter.
(a)
But, if output voltage exceeds the limits, the input L/NL is
set to 1 and the converter results under a Non-linear control
(Fig. 3d). The Duty Cycle Saturation Logic block forces to 1
the duty cycle if LT is surpassed, and set the duty cycle to 0 if
output voltage is above the higher threshold, HT (see figures 3c
and 3d).
Io
d(t)
1
(1 D ) dt
d(t)
D0
IL
IL
IL
t
t=0
(b)
Figure 1. Duty Cycle waveform under a positive load current step in
a typical Buck converter. a) Linear Control Without Saturation. b)
LnLc Control.
iO
a)
c)
III.
vO
1330
HT
b)
LT
d)
(Nominal value)
duty cycle
D
L / NL
Figure 3. Multiplexer selection input (L/NL), duty cycle and output voltage
evolution under load current steps.
B1 ( ) =
2
2 Vi
1 Use
2
2
2
2
Use Eo Use + Eo Use
G L ( ) cos( ) Eo sin
Eo
E 0
(7)
and is the phase introduced by the linear gain GL(j).
IV.
Verror
Use
0
Uie
A1 ( ) 2 + B1 ( ) 2
EoVi
Verror
where:
A1
B1
1 = tan 1
j1
+1
-1
2-1
2
t
dLnLc
1
D L0
0
(b)
dLnLc
1
DL0
Uie
0 Use
Verror
(c)
Figure 4.
GL (s)
0
(a)
Eo
(4)
Eo
Use
1
0
1 < 0
(5)
Eo
Use
2
(6)
1331
<0
Figure 5. Modulus and phase of the LnLc control gain versus normalized
error , Ec.(4). a) Modulus. b) Phase (<0).
TABLE I.
Vi
iO
C
S2
RL
250 kHz
7 H
10 mF
5V
1.5 V
16A
21A
Vref
0
Linear Control
1
CONTROL
Vo
Vo
RL
VO
BUCK
Driver
Io
iO
C
S2
Vi
0.6V
Vo
Z2
Z1
Vo
Vref
CONTROL
Threshold
Logic
S1
Z2
Z1
Driver
L / NL
SWITCHING FREQUENCY
MAIN INDUCTANCE (L)
VO
BUCK
MUX
S1
Io
Linear Control
1332
Figure 8. Output voltage ripple, output voltage and output current, with fixed
load current. a) Stable control in BL. b) Unstable control in BL.
Vo
30mV
Vo
Vo
Io
Vo
a
Io
Vo
30mV
Vo
Vo
30mV
Io
Vo
b
Io
Figure 10. Output voltage ripple, output voltage and output current, with
load current steps. a) Slow control in BL. b) Slow control in BLnL.
Figure 9. Output voltage ripple, output voltage and output current, with
fixed load current. a) BLnL with Unstable Linear control. b) BLnL without
compensator in Linear control.
Vo
30mV
Vo
Io
a
Vo
30mV
Vo
1333
Io
b
Figure 11. Output voltage ripple, output voltage and output current, with
load current steps. a) Fast control in BL. b) Fast control in BLnL.
Vo
0.6V
|GLnLc |
Vo
Theoretical
10
Io
Measured
1
0.1
0.1
10
Eo/Use
100
1000
100
1000
Vo
30mV
0.01
GLnLc
Theoretical
-20
Vo
Measured
-40
-60
Io
-80
0.01
Comp.
Linear Control
-20
Plot
1
2
3
4
5
6
11
1.001
1.01
1.001
1.1
2
2
6
fc
103
Frecuency (Hz))
104
105
PWM
Multiplexor
6
UC3843A
6
4
-50
-100
L/NL
Threshold
Logic
+_
Usup
Uinf
E o Use
100
_
+
R3
20
-40
Error Amp.
VRef
40
60
R4
_+
Verror
(db)
R2
10
E
Eo/Use
||LLnLc(s)|
Figure 12. Output voltage ripple, output voltage and output current, with
load current steps. a) Unstable BL. b) BLnL with Unstable linear control.
R1 _
Figure 14. Modulus and phase of the LnLc control gain versus normalized
error: Theoretical and Measured.
C1
0.1
Duty Cycle
Saturation
Logic
No-Linear Control
-150
-180
< -180
-200
102
103
10 4
105
Frecuency ( Hz))
Figure 15. Theoretical Bode plot of the BLnL converter (figure 7).
1334
VII. REFERENCES
[1]
[2]
[3]
[4]
Kaiwei Yao, Yu Meng and Fred C. Lee, Control Bandwidth and Transient
Response of Buck Converters. IEEE Power Electronics Specialist Conference
(PESC). 2002.
1335
[5]
[6]
Angel V. Peterchev and Seth R. Sanders, Low Conversion Ratio VRM Design.
IEEE Power Electronics Specialist Conference (PESC). 2002.
[7]
[8]
[9]
[10] Katsuhiko Ogata, Modern Control Engineering (3th Edition) Ed. Prentice Hall;
ISBN: 0132273071; 3 edition.