CS 4340 Sect.

001 Computer Architecture

CS 4V95 Computer Architecture Laboratory
Instructor: Laurie Thompson
Office: ES 3.610
Office Hours: Tuesday 10:00am.–11:30am., Tuesday 1:30pm.–2:30pm., & Thursday 10:00am.–11:30am.
Telephone: (972) 883-4839
Email: lthomp@utdallas.edu

TA: Felix Tang

Office: ES 3.612
Office Hours: Monday & Wednesday 2:00pm. – 3:00pm.
Email: yiyan@utdallas.edu

Prerequisites: CS 2305 or TE 3307

Textbook: Logic and Computer Design Fundamentals, 3rd Edition. M. Morris Mano and Charles R. Kime,
2004.

Materials: Lecture notes, homework assignments, and homework solutions will be available at
webct.utdallas.edu.

Grading: Homework assignments – 15% your lowest homework grade will be dropped.
Exam #1 – 20% February 18, 2005
Exam #2 – 30% April 4, 2005
Final Exam – 35% April 29, 2005 11:00am. – 1:00pm.

Exams are closed book and closed notes.

You may not use calculators during the exams.
The final exam is comprehensive.
PDAs, cell phones, calculators, books, notebooks, and backpacks will not be allowed at desks
during examinations.
There will be assigned seating for all examinations.
You must bring two forms of photo ID to examinations.
Late homework assignments will not be accepted.
The instructor reserves the right to give unannounced quizzes to encourage lecture attendance. Each
quiz will count as a homework grade. There are no make-ups for missed quizzes.

Make up examinations will be administered only for well-documented emergencies. A student must
make every attempt possible, via telephone and email, to notify the instructor that he/she will miss
the exam prior to the examination date and time.

Scholastic
Dishonesty: Incidence of scholastic dishonesty will be handled according to university regulations.

Scholastic dishonesty includes, but is not limited to: copying assignments, giving your work to
another to be copied, looking at another students paper during the examination, using unauthorized
materials during examination, giving students in subsequent sections test or quiz questions, handing
in another persons work as your own, having someone else take an examination for you, and
changing a graded paper and requesting that it be regraded.

Laboratory: There will be 4 laboratory assignments conducted by a TA. In order to receive credit for CS 4V95
you must satisfactorily complete all laboratory assignments. There are no makeups for
laboratory assignments. You must attend CS 4V95 at the time you are scheduled. See laboratory
schedule.

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Objectives: To develop the student’s abilities to:

• Convert data between decimal and 2's complement notation.

• Perform arithmetic operations in 2's complement fixed-point fractional notation.
• Analyze and design gate-level combinational logic circuits.
• Analyze, design, and utilize combinational components such as adders, multiplexers, and
decoders.
• Analyze and design simple synchronous sequential circuits.
• Design shift registers.
• Design gate-level RAM and ROM chips, utilize ROM in combinational design, and
interconnect memory circuits to construct larger memories.
• Design an Arithmetic-Logic-Unit and a data path, given specific register transfer
requirements and using gates and components.
• Design macros (sequences of micro-operations) for a given set of machine instructions on a
simple computer, and for a given data path.

To develop the student’s understanding of:

• The use of a variety of addressing modes.

• The use of priority interrupt mechanism.

Tentative
Schedule:

Dates Class Material Reading Assignment Due

January 10 - 14 Review of syllabus & Data Representation Chapter 1 Text
January 19 - 21 Data Representation Chapter 5 Sections 5.3 - 5.4
January 24 - 28 Boolean Algebra, Standard Forms, Logic Gates & Map Chapter 2 Text
Simplification
January 31 - February 4 Map Simplification & NAND and NOR gate Circuits
February 7 - 11 NOR gates Circuits, XOR gates, Analysis & Design of Chapter 3 Text
Comb. Circuits
February 14 - 16 Design of Comb. Circuits & Comb. Components Chapter 4 Text
February 18 Exam #1
February 21 - 25 Combinational Components
February 28 - March 4 Comb. Circ. for Arithmetic & Latches Chapter 5 Text
March 14 - 18 Flip-Flops, Sequential Circuit Analysis & Design Chapter 6 Text
March 21 - 25 Sequential Circuits Analysis & Design, and RAM Chapter 9 Text
March 28 - April 1 RAM Expansion & Registers Chapter 7 Text
April 4 Exam #2
April 6 - 8 Counters & Register Transfers
April 11 - 15 Processor & ALU Design Chapter 10 Text
April 18 - 22 Datapath Design & Microprogrammed Control Unit
April 25 Instruction Set Architecture Chapter 11 Text
April 29 Final Exam 11:00am. - 1:00pm.

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