ENGG1203: Introduction to Electrical and Electronic Engineering

Second Semester, 201213

Lab 2
Objective:

To explore combinational logic further on Logisim and Xilinx ISE.

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1 Finding your lab partner
You will be working with a randomly assigned partner for this lab. To find your assigned lab
partner and the assigned table,
1. Log in to Moodle.
2. Select the assignment Lab 2 Partner
Please proceed to your assigned table.
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2 Getting the files
Download the files for this lab from
http://www.eee.hku.hk/~engg1203/sp13/labs/lab2.zip
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3 Adder One to . . . Four
In this part, we will use Logisim to develop a 4-bit adder, using single-bit full adders as building
blocks.
3.1 Full Adder A full adder (FA) adds two 1-bit inputs, a and b, with a single bit carry-in ci,
and produces a 1-bit output s and a carry-out bit co. The function of a FA can best be explained
with a simple half adder (HA). An HA is the same as an FA except there is no carry input.
The function of an HA is to simply add two inputs a and b. Since a, b = {0, 1}, the output can
only take the values 0, 1, or 2. If the output is 2, then it must produce an additional carry-out
bit to the position to the left. As a result, the function of a half adder can be specified by the
following truth table:
a
0
0
1
1

b
0
1
0
1

co
0
0
0
1

s
0
1
1
0

Another way to look at the function of a half adder is that the carry-out bit (co) and sum bit
(s) forms a two-bit output. (Notice how combining co and s together shows the values 0, 1, 1, 2
in binary.)
The function of a full adder is similar to that of a half adder with the additional carry-in (ci)
input. The ci input takes the value from the carry out of the bit position to the right.
Complete the truth table for a full adder below. Note that the first 4 rows where carry-in is 0
are the same as that of a half adder. When carry-in is 1, it is essentially adding an additional 1

ENGG1203: Introduction to Electrical and Electronic Engineering

Lab 2

to the result. (The maximum output may therefore be 3.) You may treat co and s as a two-bit
output like in the case of the half adder above.
ci

co

For more information on the action of adder, refer to the lecture notes.
3.2 A full adder in Logisim Implement a full adder in Logisim.
1. Select File New to start a new circuit.
2. Name your full adder FA.circ.
3. Make sure the INPUT pins are called ci, a, b.
4. Make sure the OUTPUT pins are called co, s.
3.3 Build it bigger Now, using the subcircuit function of Logisim that you have tried in
Lab 1, build a 4-bit adder using the 1-bit full adder (FA) above as a building block.
Refer to the Logisim users guide for more information. To learn how to use subcircuit, select
from Logisim Help Users Guide. Then select the section on Subcircuits.
Name your inputs a3, a2, a1, a0, b3, b2, . . .
3.4 Checkoff 1
Show your complete 4-bit adder to your TA. Explain how the carry-in and carry-out
functions.
When the input a is 1110 and b is 0010, what is the output? Explain why the result
is correct/incorrect.

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4 Adder on board. . . with display
Now that you have a 4-bit adder implemented in Logisim, we will implement the same function
on the Basys2 FPGA board. The 8 switches will be used to denote the two 4-bit input, with
sw7, sw6, sw5, sw4 denoting input A, sw3, sw2, sw1, sw0 denoting input B.
We will also use the 7-segment display to show the result of addition.
4.1 Open the project lab2/lab2.xise from the downloaded file using Xilinx Project Navigator.

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Lab 2

4.2 4-bit Adder Instead of building an adder from single-bit full adders, we will simply utilize
pre-implemented adder from the Xilinx library. Open the schematic lab2.sch by double-clicking
it under the Design pane.
Add a 4-bit adder to your design. You can find a 4-bit adder under the Arithmetic category
called add4. Add it to the schematics.
There is an input to the add4 named CI. This is the carry input signal for the adder in case
adders need to be chained together. Since we do not have any carry input, we should put a
constant 0 to it. To do so, we will connect CI to the gnd symbol, which outputs 0 all the time.
You can find the gnd symbol under the General category.
4.3 7-Segment Display We want to display the result of the addition to the 7-segment display
on the Basys2 board. A module called displaymux has already been designed for that purpose.
Add it to your schematic by clicking the Add Symbol button. Under the Categories area, you
will see one category named the same as your current project directory, right above Arithmetic.
Select that category. You should see a symbol called displaymux showing up under Symbols.
To connect displaymux, place it in the design.
Connect the output of the adder (s3. . .s0) to the input (d3. . .d0) of displaymux.
The symbol has 6 inputs on the left hand side, and 3 outputs on the right hand side. The
4 inputs named d3, d2, d1, d0 are the 4-bit input that should be displayed at the 7-segment
display. d3 is the most significant (left-most) bit.
The input bindecn selects whether the output should be in binary or in decimal. When bin is
1, the 4-bit binary input will be shown in the display as 1s and 0s. When bindecn is 0, output
is converted into decimal on the display. For example, 1100 will be displayed as 0012.
The input clk is the system clock signal. The 50 MHz clock source on the Basys2 board will be
used as this main clock.
Finally, seg(6:0), dp, and an(3:0) are outputs to control the onboard 7-segment display.
4.4 External Ports Name the remaining ports of the add4 and displaymux to an I/O port
using the Add I/O Marker button. It is important to name the I/O marker with the same
name as the I/O port in the block. Connect these to I/O markers:
Input
output

a3 a2 a1 a0 b3 b2 b1 b0 clk bindecn
seg(6:0) dp an(3:0)

NOTE that the output seg(6:0) and an(3:0) are bus signals. A bus is simply a bundle of
single bit signals, usually related to each other. For example, an(3:0) is a bundle that contains
signals an(3), an(2), an(1) and an(0).
You will notice that when you select Rename Port on a bus signal, a different dialog is displayed. It works similar to the case when you are renaming a single-bit port, with the following
exceptions:
Place the signal name under the field New Base Name of Bus. You dont need to put
the width of the bus here. That is, for seg(6:0), simply put seg here.
Select the signal under Related Buses and Nets. You will see the signals connected to
the port are highlighted in Yellow in the schematics.
Press OK.
4.5 Checking the External Connection A ucf file has already been added to the project that
connects the I/O ports to the correct connection on the board. Check that the connections are
correct. For example, the two inputs to the adders are connected to sw7 to sw0, the bindecn
signal is connected to button 0, etc.

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Lab 2

4.6 Implement & Download to Board Now implement your design to generate the final configuration bit file. Download and test the design on the Basys2 board.
4.7 Checkoff 2
Show to your TA the working design on a Basys2 board. Demonstrate the following:
How you connect the adder in the schematics.
Explain what happens when you add 1100 to 0100.
Explain how you can build an 8-bit adder using the 4-bit adder component.

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5 Getting Start with Sequential Logic Clock & Flip-Flop
We will start with a simple circuit to experiment with the behavior of sequential circuit design.
5.1 In Logisim, construct the following circuit:
b
a

Q
C

c
D

Q
C

clk

Figure 1: Simple sequential circuit

You can find symbols of D-flip-flop (DFF) from the Memory library. The symbol of a D-flip-flop
in Logisim is shown in Figure 2. Note that the symbol is different from the one in lecture notes
and from the Xilinx ISE tools. In Logisim, the input to the DFF is labeled D in the bottom left
corner of the symbol. The output Q is located in TOP RIGHT corner of the symbol.

Figure 2: D-Flip-Flop in Logisim

You should connect the clock signal clk to the clock input located in the top left corner of the
symbol of all DFFs. Instead of using a simple pin as input, use a Clock symbol
You can find the clock symbol under the Wiring library.

instead.

5.2 Check Yourself Test the behavior of the circuit using the Poke tool. You can toggle the
value of a clock input similar to the way you toggle the value of a pin.

If you toggle the value of an input to a DFF when the value of clk is 0, does the
value at the output Q change? What if the value of clk is 1 ?
When does the output of a DFF toggle?

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Lab 2

5.3 Timing Diagram Complete the following timing diagram of the circuit given above.

a
b
c
d
clk
5.4 Checkoff 3

Show to your TA the completed timing diagram of Figure 1.

If the value of d is 1 in cycle n, what is the value of a in cycle n 3?
What is the function of this circuit?

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6 OPTIONAL: Schematics, Truth Table, Boolean Expression
In this part of the lab, you will explore some functionalities of Logisim that will help you in
understanding combinational logic.
6.1 Express the output y of the following circuit in terms of the input a, b, c and d. You may
find it helpful to first express y in terms of some internal nodes, which are then expressed in
terms of the inputs.
a

b
y
c
d

Figure 3:

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ENGG1203: Introduction to Electrical and Electronic Engineering

Lab 2

6.2 Using a 4-input K-map, simplify the Boolean expression above into its canonical sum-ofproduct (SOP) form. In a canonical SOP form, the expression is structured as sum (OR) of
product terms (AND) with only the input signals and their complement.
Write your K-map for the above expression in the following space. Simplify the expression by
circling the groups of 1s.

What is the simplified Boolean equation?

y=

6.3 Simplifying Using Logisim Implement the above circuit in Logisim. Once you have finished
implementing the design, save your design and select Project Analyze Circuit.
It will bring up a nice little tool from Logisim called Combinational Analysis that will help you
better understand your circuit.
6.4 Select the Inputs tab and Outputs tab. Make sure it shows 4 inputs (a, b, c and d) and
1 output (y). If not, double check if you have named the I/O Pin correctly.
6.5 Now, still in Combinational Analysis window, click on Expression. You will notice that
Logisim has already deduced the Boolean expression of the circuit you have drawn up.
6.6 Minimized Now, click on Minimized and you will see Logisim has already performed the
simplification for your circuit using Karnaugh map (K-map).
The minimized expression is shown below the K-map.
6.7 Check yourself Is the Boolean expression deduced by Logisim before simplification the same
as the one that you have deduced above? How about the K-map and the minimized expression?
6.8 Build it... Now in the Minimized tab:
1. Click Set As Expression. It will set the simplified Boolean expression as the function of
your circuit.
2. Click Build Circuit.
3. Select Use Two-Input Gates Only
4. In the textbox for Circuit Name, type sop
5. Click OK
You will see that Logisim has now created the circuit automatically for you.
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