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Institute of Electrical and Electronics Engineers (IEEE)

Hyderabad Section

Joint Chapter of Circuits and Systems and Electron Devices Societies (CAS/EDS)
and IEEE CAS Chapter, MJCET
In collaboration with

Austria Microsystems (AMS) Hyderabad and Vasavi College of Engineering

Two day workshop on

Analog IC Design Spec to Reality

About the workshop:
Man made Digital. God made Analog. Everything we see, feel, hear is an analog signal which has a definite physical characteristics, frequency content and energy.
In the process of extracting useful information in the presence of noisy unwanted signals, we need appropriate signal conditioning. Low-power and precision
analog have always been wanted features to design applications with higher performance and longer application lifetimes. The present workshop is designed to
give a flavor of the entire IC product development flow and bridging the gap between real world requirements to IC requirements. This workshop is also intended
to excite modern researchers to focus on special topics like Reliability, ESD and EMC which are extremely important for successful IC design and application.
Workshop Faculty:
A.G. Krishna Kanth: A.G. Krishna Kanth received his Bachelors and Masters degrees from IIT Bombay with specialization in Microelectronics. He was the recipient
of President of India Shankar Dayal Sharma Gold medal in 2002. He started his career in Texas Instruments India as an analog design engineer. He worked with
QualcoreLogic heading the analog team, ensuring the success of many analog IPs. He started working for AMS from 2006 as Group Lead for the Analog design
team and is currently heading all the analog product development activities in India. He has three patents and two IEEE publications. He is also pursuing his parttime PhD research work from IIIT Hyderabad. His research interests include Power management circuits, amplifiers, filters and precision analog circuits.
V. Veeresh Babu: V. Veeresh Babu received his B.E from Sant Longowal Institute of Engineering and Technology in 2000 and M.Tech from IIT Bombay in 2003. He
worked as Analog Design engineer at QualcoreLogic. from 2003 to 2006. He started working for AMS from 2006 as Analog design engineer. He has a published
patent, two IEEE publications and is the recipient of best paper award in VLSI design conference. He is currently working as a senior engineer in AMS and also
pursuing his part-time PhD research work with BITS Hyderabad. His research interests include Battery management systems, high precision band gap references
and analog signal processing.
Chandra Nyshadham: Chandra Nyshadham received his Bachelor of Engineering in Electronics from Andhra University, Vishakhapatnam, India, in 2004. He
received his Master of Technology in VLSI Design from GGS Indraprastha University, New Delhi and was University Gold Medalist. From 2007 to 2010, he worked
on integrated PLLs and CMOS I/Os at QualCoreLogic. He joined AMS in 2010 and is currently working as Staff engineer- Analog. His research interests include
precision reference design, amplifiers and voltage regulators with special focus on EMC issues.
Harshitha Penmetsa: Harshitha Penmetsa started her career as analog layout engineer in QualcoreLogic in 2004, where she was responsible for many custom fullchip layouts. She joined AMS in the year 2006 and is currently heading the analog layout team. She is responsible for Custom Layout of ICs considering DRC, DFM,
DFY, ESD and EMC requirements of the IC, all the way to the full transfer of GDSII to FAB. She graduated from department of Electronics and Communication Engg
from JNTU Hyderabad.

Workshop Schedule and Topics:

Schedule DAY 2

Schedule DAY 1
Registration and Networking: 9.30 AM to 10.00 AM

SESSION 3 (9:30AM 1:30PM)

Inaugural Session: 10.00 AM to 11.00 AM

Design for What? - Specification, Test, Yield, Reliability/Quality,

Manufacturability, Safety

SESSION 1 (11AM 1:30PM)

LUNCH (1:30PM 2:30PM)
Motivation, Economics of IC Design, Understanding system/application
LUNCH (1:30PM 2:30PM)

SESSION 2 (2:30PM 5:30PM)

What happens after layout? (GDS to IC) Validation, ATE testing,
Qualification and Unlimited production, Demonstration,

SESSION 2 (2:30PM 5:30PM)

Closing ceremony
IC Architecture: Concept and Planning - Power partitioning, Analog/Digital
Interface, Design Architecture, Test concept, ESD/EMC concept, IC floorplanning, Pin-out, Package

For Registration please log on to


Date: Thursday and Friday, 18th and 19th September 2014 Time: 9.30 A.M to 5.30 P.M
Venue: Seminar Hall, Vasavi College of Engineering, Ibrahimbagh Hyderabad.

Registration Fee: Rs. 1000 for IEEE Members, Rs. 1500 for Non IEEE Members
Note: Registration fee includes Welcome kit, lunch and snacks for two days.
Registration is open to all. There are limited seats available and interested persons are requested to register online be paying
registration fees at http://bit.ly/1zfiMCe latest by 5th September 2014. For any further details please contact:
Workshop Coordinator: Prof. P.A. Govindacharyulu, Chair, IEEE CAS/EDS Joint Chapter, pagovindacharyulu@gmail.com
Mr. Mohammed Arifuddin Sohel, Secretary, IEEE CAS/EDS joint Chapter,9885 407 094, arif.sohel@mjcollege.ac.in