Vous êtes sur la page 1sur 15

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH

ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16


VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

AN MTCMOS TECHNIQUE FOR OPTIMIZING LOW POWER


FLIP-FLOP DESIGNS
S.Roja

C.Vijaya Bhaskar

P.G Student
VLSI, Department of E.C.E
SIETK, Puttur

Assistant Professor
Department of E.C.E
SIETK, Puttur

I. INTRODUCTION
Power consumption being the major problem in achieving high
performance and it is listed as one of the top three challenges in
electronics industry. The clock system, which consists of the clock
distribution network and flip-flops and latches, is one of the most power
consuming components in a VLSI system. It accounts for 30% to 60% of
the total power dissipation in a system. As a result, reducing the power
consumed by flip-flops will have a deep impact on the total power
consumed. A large portion of the on chip power is consumed by the clock
circuits.
Power consumption is determined by several factors including frequency
, supply voltage V, data activity , capacitance C, leakage, and short
circuit current
P=Pdynamic+Pshort circuit+Pleakage
In the above equation, dynamic power Pdynamic is also called the
switching power,
Pdynamic=CV2.
Pshort circuit is the short circuit power which is caused by the finite rise
and fall time of input signals, resulting in both the pull up network and
pull down network to be ON for a short while
Pshort circuit= Ishort circuitVdd

236

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

Pleakage is the leakage power. With supply voltage scaling down, the
threshold voltage also decreases to maintain performance. However, this
leads to the exponential growth of the sub threshold leakage current.
Sub threshold leakage is the dominant leakage now.
Pleakage= IleakageVdd.
Flip-Flop is an electronic circuit that stores a logical state of one or more
data input signals in response to a clock pulse. Flip-flops are often used
in computational circuits to operate in selected sequences during
recurring clock intervals to receive and maintain data for a limited time
period sufficient for other circuits within a system to further process
data. At each rising or falling edge of a clock signal, the data stored in a
set of Flip-Flops is readily available so that it can be applied as inputs to
other combinational or sequential circuitry. Such flip-flops that store
data on both the leading edge and the trailing edge of a clock pulse are
referred to as double-edge triggered Flip-Flops otherwise it is called as
single edge triggered Flip-Flops.
In digital CMOS circuits there are three sources of power dissipation,
the first is due to signal transition, the second comes from short circuit
current which flows directly from supply to ground terminal and the last
is due to leakage currents. As technology scales down the short circuit
power becomes comparable to dynamic power dissipation. Furthermore,
the leakage power also becomes highly significant. High leakage current
is becoming a significant contributor to power dissipation of CMOS
circuits as threshold voltage, channel length and gate oxide thickness
are reduced. Consequently, the identification and modeling of different
leakage components is very important for estimation and reduction of
leakage power especially for High-speed and low-power applications.
Multithreshold Voltage Based CMOS (MTCMOS) and voltage scaling
are two of the low power techniques used to reduce power.

237

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

II. SOURCES OF POWER DISSIPATION


Power dissipation in digital CMOS circuits is caused by four sources as
follows.
Low Power Design Space:
The three degrees of freedom inherent in the low-power design space:
voltage, physical capacitance, and data activity. Optimizing for power
entails an attempt to reduce one or more of these factors.
1) Voltage: Voltage reduction offers the most effective means of
minimizing power consumption the useful range of Vdd to a minimum
of two to three times Vt. One approach to reduce the supply voltage
without loss in throughput is to modify the Vt of the devices. Reducing
the Vt allows the supply voltage to be scaled down without loss in speed.
2) Switching Activity:
If there is no switching in a circuit, then no dynamic power will be
consumed. There are two components to switching activity, fclk which
specifies the average periodicity of data arrivals and E(sw) which
determines how many transitions each arrival will generate
3) Physical Capacitance:
Minimizing capacitances offers another technique for minimizing power
consumption. In order to consider this possibility we must first
understand what factors contribute to the physical capacitance of a
circuit. Power dissipation is dependent on the physical capacitances seen
by individual gates in the circuit.
The leakage current, which is primarily determined by the
fabrication technology, consists of two components
1) Reverse bias current in the parasitic diodes formed between source
and drain diffusions and the bulk region in a MOS transistor.
2) The sub threshold current that arises from the inversion charge
that exists at the gate voltages below the threshold voltage.

238

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

3) The standby current which is the DC current drawn continuously


from Vdd to ground.
4) The short-circuit current which is due to the DC path between the
supply rails during output transitions.
5) The capacitance current which flows to charge and discharge
capacitive loads during logic changes.
This paper surveys various low power flip-flops is described in Section II.
Section III gives the proposed MTCMOS technique. Section IV
represents MT-CPSFF and section V presents simulation results.
Section VI concludes this paper.
III. LOW POWER FLIP-FLOPS
Some of the different flip-flops are designed for reducing power
consumption. The following are the different low power flip-flops they
are
1) Conditional discharge flip-flop (CDFF)
2) Conditional data mapping flip-flop (CDMFF)
3) Clock pair shared flip-flop (CPSFF)
4) Multi threshold CMOS -Clocked paired shared flip-flop (MT-CMOS
CPSFF)
1) Conditional discharge flip-flop (CDFF):

FIG 3.1: CDFF


239

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

The schematic diagram of the conditional discharge flip-flop (CDFF),


is shown in Fig. It uses a pulse generator as in, which is suitable for
double-edge sampling. The flip-flop is made up of two stages. Stage one
is responsible for capturing the LOW-to-HIGH transition. If the input D
is HIGH in the sampling window, the internal node X is discharged,
assuming (q,qb)that were initially (LOW, HIGH) for the discharge path
to be enabled. As a result, the output node will be charged to HIGH
through P2 in the second stage. Stage 2 captures the HIGH-to-LOW
input transition. If the input D was LOW during the sampling period,
then the first stage is disabled and node X retains its precharge state.
Whereas, node Y will be HIGH, and the discharge path in the second
stage will be enabled in the sampling period, allowing the output node to
discharge and to correctly capture the input data. CDFF uses 13clocked
transistors resulting in reduction of the power consumption.
2) Conditional data mapping flip-flop (CDFF):
IN Conditional data mapping flip-flop (CDMFF) used only seven clocked
transistors, resulting in about 50% reduction in the number of clocked
transistors; hence CDMFF used less power than CDFF. This shows the
effectiveness of reducing clocked transistor numbers to achieve low
power. The conditional data mapping methodology exploits the property
of the flip-flop, by providing the flip-flop with a stage to map its inputs to
(0, 0) if a redundant event is predicted, such that the outputs will be
unchanged when clock signal is triggered. A conditional data mapper is
deployed in the circuit to map the inputs by using outputs as control
signals.

240

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

FIG 3.2: CDMFF


3) Clock paired shared flip-flop:
This low power flip flop is the improved version of Conditional Data
Mapping Flip flop (CDMFF). It has totally 19 transistors including 4
clocked transistors as shown in Figure. The N3 and N4 are called
clocked pair which is shared by first and second stage. The floating
problem is avoided by the transistor P1 (always ON) which is used to
charge the internal node X. This flip flop will operate, when clk and
clkdb is at logic 1. When D=1, Q=0, Qb_kpr=1, N5=OFF, N1=ON,
the ground voltage will pass through N3, N4 and N1 then switch on the
P2. That is Q output pulls up through P2. When D=0, Q=1, Qb_kpr=0,
N5= ON, N1= OFF, Y=1, N2= ON, then Q output pulls down to zero
through N2, N3 and N4.

241

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

The flip flop output is depending upon the previous output Qand Qb_kpr
in addition with clock and data input. So the initial condition should be
like when D=1 the previous state of Q should be 0 and Qb_kpr should
be 1. Similarly when D=0 the previous state of Q should be 1 and
Qb_kpr should be 0. Whenever the D=1 the transistor N5 is idle,
Whenever the D=0 input transmission gate is idle.
In high frequency operation the input transmission gate andN5 will
acquire incorrect initial conditions due to the feedback from the output.
The noise coupling occurred in the Q output due to continuous
switching at high frequency. The glitch will be appearing in the Q
output. It will propagate to the next stage which makes the system more
vulnerable to noise. In order to avoid the above drawbacks and reduce
the power consumption in proposed flip flop, we can make the flip-flop
output as independent of previous state. That is without initial
conditions and removal of noise coupling transistors. In addition double
edge triggering can be applied easily for power reduction to the proposed
flip flop. It will be a less power consumption than other flip flops.

FIG 3.3: CPSFF

242

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

IV. MTCMOS TECHNIQUE


Multi-Threshold Voltage CMOS (MTCMOS) is one of the highly
accepted circuit technique in the reduction of the leakage current. For
efficient power management in MTCMOS technology, the circuit works
on two modes, one being the "active" and the other "sleep" operational
modes. The conventional circuit works on single threshold voltage (Vt)
while the circuit employing the MTCMOS technique works on two
different threshold voltage switches are Low Vt and High Vt. The circuit
comprises of two different set of transistors- one which works on High Vt
are termed as "sleep" transistors and the transistors which works on Low
Vt comprises the logical circuit. The sleep transistors are used to achieve
high performance by reducing the leakage current while the Low Vt
transistors enhance the circuits speed performance.
The power gating technique using MTCMOS is shown in Fig. The
diagram consists of two sleep transistors S1 and S2 with higher Vt. The
logic circuit between the S1 and S2 is not directly connected to real
supply lines Vdd and Gnd, but in turn it is connected to virtual power
supply lines Vddv and Gndv and has low Vt. Both the sleep transistors
are given complementary inputs S and SBAR. The above circuit operates
in two modes active mode and standby mode.
In active mode, S=0 and SBAR=1 such that S1 and S2 are ON and
virtual supply lines Vddv and Gndv work as real supply lines therefore
the logic circuit operates normally and at a higher speed. In sleep mode,
S=1 and SBAR=0 such that S1 And S2 are OFF and this will cause
virtual power supply lines to float and large leakage current present in
circuit is suppressed by sleep transistors S1 and S2 resulting in lower
leakage current and thus reducing power consumption.

243

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

FIG 4.1:MTCMOS TECHNIQUE


V.PROPOSED LOW POWER FLIP-FLOP DESIGNS USING
MT-CMOS
To reduce standby leakage power consumption and to ensure efficient
implementation of sequential elements, we propose clocked pair shared
flip-flop using MTCMOS technique. We are designing this circuit
keeping the number of clocked transistors same as in the actual circuit.
The schematic of MT-CPSFF is shown in Fig.5.1

Fig.5.1 Schematic of Proposed CPSFF using MTCMOS


244

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

In this proposed Clocked Pair Shared Flip Flop, a high threshold voltage
NMOS transistor is provided with a sleep signal S, which is high in the
active mode and low during the standby mode.Here, the first and the
second stage shares the same clocked pair (M5 and M6). Furthermore,
the pMOS M1 is always turned on and is connected to the power supply
Vdd, thus charging the internal node X all the time. This reduces the
floating of node X and enhances the noise robustness.
The flip flop works, when both clk and clkdb are at logic 1. Pseudo
nMOS and conditional mapping technique both are combined using the
above scheme. The nMOS M3 is controlled by a feedback signal. For
input D=1and S=1,Q will be high, switching ON the transistor M8, and
turning OFF M3 thus parrying redundant switching activity and flow of
shortcircuit current at the node X. When D transits to 1 the output Q is
pulled up by pMOS M2 whereas M4 is used to pull down Q when D=0
and Y=1 at the arrival of clock pulse. When the input D transits from 0-1
the short-circuit occurs for once even though M1 is always ON, thus
disconnecting the discharge path and turning off M3 after two gates
delay by feedback signal. There will be no short-circuit even if the input
D stays high as M3 disconnects the discharge path. The output of the flip
flop depends upon the state previously acquired by Q and QB along with
the clock and the data signal inputs provided.
T-FLIP-FLOP MTCMOS TECHNIQUE
The below diagram which shows the extension of the MT-CPSFF.T
flip-flop which uses for the reducing switching activity and also power
consumption. This is the another proposed MTCMOS technique, The
schematic of MT-CPSFF is shown in Fig.5.2

245

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

Fig.5.2 Schematic of Proposed T- CPSFF using MTCMOS


VI.SIMULATION RESULTS
The simulation results for all existing and proposed flip-flops were
obtained in a 90nm CMOS technology at room temperature using
Tanner EDA Tools over various supply voltages and frequencies. Table I
show power comparison results for the CDFF, CDMFF, CPSFF and the
proposed MT-CPSFF for 1.5, 2.5 and 3.5 supply voltage (Vdd) over
750MHz and 500MHz clock frequencies. Table I show that CDFF has
38.39% less power consumption than conventional DEFF at 750MHz
clock frequency and 1.5Vdd.
The simulation results for all existing and proposed flip-flops were
obtained in a 90nm CMOS technology at room temperature using
Tanner EDA Tools 13.0 over varioussupply voltages and frequencies.
Table I show power comparison results for the CDFF, CDMFF, CPSFF
and the proposed MT-CPSFF for 1.5, 2.5 and 3.5 supply voltage (Vdd)
over 750MHz and 500MHz clock frequencies. Table I show that CDFF
has 38.39% less power consumption.
Similarly at 500MHz and 3Vdd CDFF consumes 74.02% less power than
conventional DEFF. With the reduction in the number of clocked
transistor in the CDMFF as compared to CDFF, the power consumption
by CDMFF at 750MHz and at1.5Vdd is 81.02% less as compared to the
246

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

CDFF. Albeit CDMFF reduces the power consumption to a considerable


amount, but it is susceptible to redundant clocking in addition to a
floating node. The CPSFF overcomes this drawback by reducing the
number of clocking transistors. For 500 MHz and at 3Vdd CPSFF
consumes 53.80% less power than CDMFF. Similarly at 750MHz and
1.5Vdd CPSFF consumes 9.74% less power as compared to CDMFF. The
comparison shows that reducing the clocked transistors has a major
effect on reducing the total power consumption of the design circuit.
The proposed MT-CPSFF which makes use of MTCMOS technique
shows higher performance as well as smaller Stand by leakage current.
The low Vt MOSFETs enhances the speed, while the higher Vt
MOSFETs reduces the standby leakage current. Table I show that for
MT-CPSFF at 500MHz and 3Vdd, the proposed circuit consumes 66.3%
less power as compared to conventional CPSFF. Similarly at 750MHz
and1.5Vdd MTCPSFF consumes 15.2% less power than conventional
cpsff.

Fig:6.1 Output wave form for D-ff


247

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

Fig: 6.2Output waveform for T-ff


DESIGN
NAME

CDFF
CDMFF
CPSFF
MT-CPSFF
MT-CPSFF

AREA

26

SWIT
ICHIN
G
TRANS
ISTOR
13

20
17
21
27

7
4
4
4

FREQUENCY
500MHZ
700MHZ
POWER CONSUMPTION
1.5
9.7
1.9
1.3
1.2
1.1

SUPPLY VOLTAGE
3
1.5
3V
54.8
14.6
82.0
49.6
2.7
53.7
22.9
2.5
32.8
7.7
2.12
11.6
7.5
2.00
10.5

VII CONCLUSION
In this paper, a new design for D and T flip-flop is introduced to reduce
internal switching activity of nodes and stand by leakage power; along
with this variety of design techniques for low power clocking system are
reviewed. This proposed flip-flop reduces local clock transistor number
and power consumption as well. The proposed MT-CPSFF outperforms
previously existing CDFF, CDMFF and CPSFF in terms of power and
good output response by approximately 20% to 85%. Furthermore,
248

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

several low power techniques, including low swing and double edge
clocking, can be explored to incorporate into the new flip-flop to build
system.
References
1.

M. Pedram, Power minimization in IC Design: Principles and


applications, ACM Transactions on Design Automation of
Electronic Systems, vol. 1, pp.3-56, Jan. 1996.

2.

S.M. Kang, Y. Leblebici CMOS Digital Integrated Circuits analysis


and design third edition, TMH, 2003.

3.

A. Keshavarzi, K. Roy, and C. F. Hawkins, Intrinsic leakage in low


power deep submicron CMOS ICs, in Proc. Int. Test Conf., pp.
146 155, 1997.

4.

Z. Peiyi, M. Jason, K. Weidong, W. Nan, and W. Zhongfeng Design


of Sequential Elements for Low Power Clocking System IEEE
Transaction of Very large Scale Integration July 2010.

5.

N.Weste and D. Harris, CMOS VLSI Design. Reading, MA:


Addison Wesley, 2004.

6.

M. Pedram, Q. Wu, and X. Wu, A New Design for Double Edge


Triggered Flip-flops, in Jan.2002

7.

P. Zhao, T. K. Darwish, and M. A. Bayoumi, High-Performance


and Low-Power Conditional Discharge Flip-Flop, IEEE
transactions on very large scale integration (VLSI) systems, vol.12
no.5, May 2004.

8.

P. Zhao, T. K. Darwish, and M. A. Bayoumi, High-Performance


and Low-Power Conditional Discharge Flip-Flop, IEEE
transactions on very large scale integration (VLSI) systems, vol.12
no.5, May 2004.

9.

T.Kavitha, Dr.V.Sumalatha A New Reduced Clock Power Flipflop


for Future SOC Applications. International Journal of Computer
Trends and Technology, volume3Issue4, 2012.
249

INTERNATIONAL JOURNAL OF MULTIDISCIPLINARY EDUCATIONAL RESEARCH


ISSN : 2277-7881; IMPACT FACTOR - 2.735; IC VALUE:5.16
VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

10. C. K. Teh, M. Hamada, T. Fujita,H. Hara, N. Ikumi, and Y. Oowaki,


Conditional Data Mapping Flip-Flops for Low-Power and
High-Performance Systems.IEEE Transactions on very large scale
integration (VLSI) systems, vol. 14, no. 12,December 2006.
11. F. Mohammad, L. A. Abhilasand P. SrinivasA new parallel counter
architecture with reduced transistor count for power and area
optimization, international conference on Electrical and
Electronics Engineering, Sept., 2012.
12. BhuvanaS, SangeethaRA Survey on Sequential Elements for Low
Power Clocking System, Journal of Computer Applications ISSN:
0974 1925, Volume-5, Issue EICA2012-3, and February 10, 2012.
13. B. Kousalya, Low Power Sequential Elements for Multimedia and
Wireless Communication applications, July 2012.
14. Mutoh S et al, 1-V Power supply high-speed digital circuit
technology with multithreshold- voltage CMOS, IEEE J. Solid
State Circuits, Vol. 30, pp. 847-854, August 1995.
15. HemanthaS, Dhawan A and Kar H, Multi-threshold CMOS design
for low power digital circuits, TENCON 2008-2008 IEEE Region
10 Conference, pp.1-5, 2008.
16. Q. Zhou, X.Zhao, Y.Cai, X.Hong, An MTCMOS technology for
low-power physical design, Integration VLSI J. (2008).

250