VLSI

S. NO

CODE

TITLE

KEYWORDS

YEAR

High-Throughput Multi standard Transform Multi

standard
Core Supporting MPEG/H.264/VC-1 Using transform
CSDA,
Common Sharing Distributed Arithmetic
Image & Video
compression, DCT
Improved 8-Point Approximate DCT for Image Approximate DCT,
and Video Compression Requiring Only 14 low-complexity
Additions
algorithms,
image
compression, Video
Compression, HEVC
Area-efficient,
Area-Delay Efficient Binary Adders in QCA
CSLA, Applicationspecific integrated
circuit (ASIC),
AreaDelayPower Efficient Carry-Select Adder,
arithmetic
Adder
unit,
low-power
design

2014

SDVL-05

Input Vector Monitoring Concurrent BIST Built-in

self-test,
Architecture Using SRAM Cells
design for testability,
testing

2014

SDVL-06

2014

SDVL-07

SDVL-08

SDVL-09

10

SDVL-10

11

SDVL-11

Simplifying clock gating logic by matching Clock gating, gating

Factored forms
logic factored form,
factoring tree
Data encoding techniques for reducing energy Data
encoding,
Consumption in network-on-chip
interconnection on
chip, low power,
network-on-chip
Area-Delay-Power Efficient Fixed-Point LMS Adaptive
filters,
Adaptive Filter With Low Adaptation-Delay
least mean square
algorithms,
fixedpoint Arithmetic
Analysis and Design of a Low-Voltage Low- Double-tail
Power Double-Tail Comparator
comparator, dynamic
clocked comparator,
High-speed ADC
converters, lowpower analog design
Fast Sign Detection Algorithm for the RNS Computer
Moduli Set {2n+1 1, 2n 1, 2n}
arithmetic, residue
number
system
(RNS),
restricted
moduli set, sign
detection.
Efficient Integer DCT Architectures for HEVC High
Efficiency
Video
Coding

SDVL-01

SDVL-02

SDVL-03

SDVL-04

2014

2014

2014

2014

2014

2014

2014

2014

(HEVC),
integer
discrete
cosine
transform
(DCT),
video coding, DCT,
H.265
Bit-Level Optimization of Adder-Trees for Adder-tree
Multiple Constant Multiplications for Efficient optimization, finite
FIR Filter Implementation
impulse response
Filter,
multiple
constant
multiplication, FIR,
MCM

12

SDVL-12

2014

13

SDVL-13

Design of Efficient Binary Comparators in Binary comparators,

Quantum-Dot Cellular Automata
majority gates

2014

14

SDVL-14

2014

15

SDVL-15

16

SDVL-16

17

SDVL-17

18

SDVL-18

19

SDVL-19

Reverse Converter Design via Parallel-Prefix Digital arithmetic,

Adders: Novel Components, Methodology, and parallel-prefix adder,
Implementations
residue
number
system
(RNS),
reverse converter.
Low-Complexity Low-Latency Architecture for Data
comparison,
Matching of Data Encoded With Hard ECC,
Hamming
Systematic Error-Correcting Codes
distance,
tag
matching, systematic
codes
Multifunction Residue Architectures for Computer arithmetic
Cryptography
Montgomery
multiplication,
parallel arithmetic &
logic Structures
Defense Against Primary User Emulation Network
security,
Attacks in Cognitive Radio Networks Using primary
user
Advanced Encryption Standard
emulation
attacks,
secures
spectrum
sensing,
dynamic
spectrum
Access,
and
eight-level
vestigial sideband
Aging-Aware Reliable Multiplier Design With Adaptive hold logic
Adaptive Hold Logic
(AHL), negative bias
temperature
Instability, positive
bias
temperature
instability, reliable
multiplier, variable
latency
Critical-Path Analysis and Low-Complexity Adaptive
filters,
Implementation of the LMS Adaptive critical-path
Algorithm
optimization, least

2014

2014

2014

2014

2014

mean
square
algorithms,
LMS
adaptive filter
20

SDVL-20

Eliminating Synchronization Latency Using Duplication, latency,

Sequenced Latching
metastability,
speculation,
synchronization

2014

21

SDVL-21

SDVL-22

23

SDVL-23

24

SDVL-24

AI encoding, errorfree
algorithm,
Daubechies wavelets
Gate
mapping,
Automation, NULL
convention
logic
(NCL),factoring,
grouping,
technology mapping
Efficient FPGA and ASIC Realizations of DA- Finite
impulse
Based Reconfigurable FIR Digital Filter
response
filter,
reconfigurable
implementation,
circuit optimization
distributed
arithmetic
Non binary LDPC Decoder Based on ECC,
Hardware
Simplified Enhanced Generalized Bit-Flipping architecture, iterative
Algorithm
decoding, nonbinary
low-density paritycheck codes, Symbol
flipping
Decoding

2014

22

Precise VLSI Architecture for AI Based 1-D/ 2D Daub-6 Wavelet Filter Banks With Low
Adder-Count
Gate Mapping Automation for Asynchronous
NULL Convention Logic Circuits

25

SDVL-25

Efficient Algorithm and Architecture for Crypto-processor,

Elliptic Curve Cryptography for Extremely Gaussian
normal
Constrained Secure Applications
basis (GNB), Koblitz
curves,
point
multiplication,
RFID,
security,
wireless
sensor networks

2014

26

SDVL-26

An Optimized Modified Booth Recoder for Add-Multiply

Efficient Design of the Add-Multiply Operator operation, arithmetic
circuits,
Modified
Booth
recoding,

2014

27

SDVL-27

Efficient VLSI Implementation of Neural Hyperbolic tangent,

Networks With Hyperbolic Tangent Activation neural
networks,
Function
nonlinear

2014

2014

2014

2014

activation function
Recursive Approach to the Design of a Parallel Binary
adders ,
Self-Timed Adder
CMOS
design,
Asynchronous
circuits,
Digital
arithmetic
Design of Digit-Serial FIR Filters: Algorithms, digit-serial
Architectures, and a CAD Tool
arithmetic,
finite
impulse
response
(FIR)
filters,
multiple
constant
multiplications
Parallel AES Encryption Engines for Many- Advanced
Core Processor Arrays
encryption standard
(AES),
parallel
processor, software,
fine-grained
Design of Testable Reversible Sequential Cellular automata,
Circuits
Fredkin
gate,
conservative
logic,
quantum-dot,
reversible logic

2014

SDVL-32

Test Patterns of Multiple SIC Vectors: Theory Built-in

self-test
and Application in BIST Schemes
(BIST), low power,
single-input
Change (SIC), test
pattern
generator
(TPG).

2013

33

SDVL-33

A Novel Modulo Adder for 2n-2k- 1Residue Carry

correction,
Number System
modular
adder,
parallel prefix,
Residue
number
system
(RNS),
VLSI.

2013

34

SDVL-34

2013

35

SDVL-35

36

SDVL-36

Improvement of the Security of ZigBee by a Chaos cryptosystem,

New Chaotic Algorithm
encryption, RFCA,
security, ZigBee
CORDIC Based Fast Radix-2 DCT Algorithm
Coordinate rotation
digital computer, fast
radix-2
algorithm,
DCT
Radix 6, Discrete
Split Radix Algorithm for Length 6mDFT
Fourier transforms,
fast
Fourier
transform
(FFT),
general split radix

28

SDVL-28

29

SDVL-29

30

SDVL-30

31

SDVL-31

32

2013

2013

2013

2013

2013

37

SDVL-37

Low-Complexity Multiplier for GF(2m) Based All-one polynomial,

on All-One Polynomials
finite field, systolic
design

2013

38

SDVL-38

Low-Power, High-Throughput, and Low-Area Adaptive

filter,
Adaptive FIR Filter Based on Distributed distributed
Arithmetic
arithmetic
(DA),
least mean square
algorithm

2013

39

SDVL-39

Multicarrier Systems Based on Multistage IFFT,

multicarrier
Layered IFFT Structure
systems

2013

40

SDVL-40

2012

41

SDVL-41

42

SDVL-42

43

SDVL-43

44

SDVL-44

Design of an Error Detection and Data Data recovery, error

Recovery Architecture for Motion Estimation detection,
motion
Testing Applications
estimation, residueand-quotient (RQ)
code
Period
Extension
and
Randomness Chaotic
map,
Enhancement
Using
High-Throughput mixing,
period
Reseeding-Mixing PRNG
extension,
pseudo
random
number
generator (PRNG),
reseeding
Area-Efficient Parallel FIR Digital Filter DSP,
FIR
Structures for Symmetric Convolutions Based algorithms, parallel
on Fast FIR Algorithm
FIR,
symmetric
convolution
Measurement and Evaluation of Power Null
convention
Analysis Attacks on Asynchronous S-Box
logic
(NCL),
Security,
Side
channel
attack
(SCA), substitution
box (S-Box)
Low-Power and Area-Efficient Carry Select ASIC, area-efficient,
Adder
CSLA, low power.

45

SDVL-45

A Low-Power Single-Phase Clock Multiband frequency

Flexible Divider
synthesizer,
highspeed digital circuits,
true
single-phase
clock

2012

2012

2012

2012

2012