INSTITUTO TECNOLGICO DE SALINA CRUZ

DISEO DIGITAL
Actividad:
REPORTE DE PRCTICAS

V semestre grupo C
Ingeniera Electrnica

Salina Cruz, Oaxaca a Octubre del 2014

INTRODUCCIN
Tal como lo indican sus siglas, VHDL (Hardware Description Language) es un
lenguaje orientado a la descripcin o modelado de sistemas digitales; es decir, se
trata de un lenguaje mediante el cual se puede describir, analizar y evaluar el
comportamiento de un sistema electrnico digital.
VHDL es un lenguaje poderoso que permite la integracin de sistemas
digitales sencillos, elaborados o ambos en un dispositivo lgico programable, sea
de baja capacidad de integracin como un GAL, o de mayor capacidad como los
CPLD y FPGA.
Ise Desing es un programa de la familia de Xilinx, este programa nos
permite disear y configurar nuestro comportamiento lgico digital en cada uno de
nuestros dispositivos lgicos programables.
Este programa es de alto nivel nos permite visualizar de manera grfica el
proceso de los dispositivos en determinados intervalos de tiempo, este proceso es
mejor conocido como test bench o bien banco de pruebas a dispositivos lgicos de
manera virtual.
En el siguiente trabajo se muestra un trabajo de manera sistemtica y de
HDL, se muestra cada una de las compuertas en su mdulo declarando las
variables de entrada y salida posteriormente mostrando el banco de pruebas (test
bench) donde aparece el comportamiento de estas compuertas: AND, NOT, OR,
NOR, XOR, XNOR y NAND.

OBJETIVO
Ver el comportamiento de cada dispositivo lgico de manera digital
grfica, y ver como modifica su sea en determinado tiempo.

en una

PROPSITO
Conocer el programa de diseo en HDL
compuerta lgica.

y ver el funcionamiento en cada

DESARROLLO
Para poder realizar esta prctica primero debemos de tener el software de diseo
en este caso es ISE DESING en este programa podemos declarar nuestras
variables, y definir nuestras entradas y salidas de cada compuerta a disear.
Es decir debemos de crear nuestro modulo la librera de la IEEE, librera
predeterminada.
Se crean los mdulos y test bench de la siguiente manera y para cada una de las
compuertas logicas.

Compuerta AND
MODULE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main_src is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
f : out STD_LOGIC);
end main_src;
architecture Behavioral of main_src is
begin
f <= x and y and z;

end Behavioral;
.....................................................................
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY main_tb IS
END main_tb;
ARCHITECTURE behavior OF main_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT main_src
PORT(
x : IN std_logic;
y : IN std_logic;
z : IN std_logic;
f : OUT std_logic
);
END COMPONENT;
--Inputs
signal x : std_logic := '0';
signal y : std_logic := '0';
signal z : std_logic := '0';
--Outputs
signal f : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: main_src PORT MAP (
x => x,
y => y,
z => z,
f => f
);
-- Clock process definitions
-- <clock>_process :process
-- begin
-<clock> <= '0';
-wait for <clock>_period/2;

-<clock> <= '1';

-wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
x <= not x;
end process;
stim_proc1: process
begin
wait for 50 ns;
y <= not y;
end process;
stim_proc2: process
begin
wait for 25 ns;
z <= not z;
end process;
END;

Compuerta OR
MODULE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;
--use UNISIM.VComponents.all;
entity Module_OR is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC);
end Module_OR;
architecture Behavioral of Module_OR is
begin
X <= A or B;
end Behavioral;
......................................................
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_bench_OR IS
END Test_bench_OR;
ARCHITECTURE behavior OF Test_bench_OR IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Module_OR
PORT(
A : IN std_logic;
B : IN std_logic;
X : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
--Outputs
signal X : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--

constant <clock>_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)

uut: Module_OR PORT MAP (

A => A,
B => B,
X => X
);
--------

-- Clock process definitions

<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100ns;
A <= not A;
end process;
stim_proc1: process
begin
wait for 50ns;
B <= not B;
end process;

END;

Compuerta NOT
MODULE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Module_NOT is
Port ( A : in STD_LOGIC;
X : out STD_LOGIC);
end Module_NOT;
architecture Behavioral of Module_NOT is
begin
X <= not A;
end Behavioral;
..............................................
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_Bench_NOT IS
END Test_Bench_NOT;
ARCHITECTURE behavior OF Test_Bench_NOT IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Module_NOT
PORT(
A : IN std_logic;
X : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
--Outputs
signal X : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name
--

constant <clock>_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Module_NOT PORT MAP (
A => A,
X => X
);
--------

-- Clock process definitions

<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
A <= not A;
end process;

END;

Compuerta NAND
MODULE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Module_NAND is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC);
end Module_NAND;
architecture Behavioral of Module_NAND is
begin
X <= not (A and B);
end Behavioral;
..............................................
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_Bench_NAND IS
END Test_Bench_NAND;
ARCHITECTURE behavior OF Test_Bench_NAND IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Module_NAND
PORT(
A : IN std_logic;
B : IN std_logic;
X : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';

--Outputs
signal X : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--

constant <clock>_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Module_NAND PORT MAP (
A => A,
B => B,
X => X
);
--------

-- Clock process definitions

<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
A <= not A;
end process;
stim_proc1: process
begin
wait for 50 ns;
B <= not B;
end process;

END;

Compuerta XOR
MODULE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Module_EXOR is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC);
end Module_EXOR;
architecture Behavioral of Module_EXOR is
begin
X <= (A and (not B)) or ((not A) and B);
end Behavioral;
.........................................
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_Bench_EXOR IS
END Test_Bench_EXOR;
ARCHITECTURE behavior OF Test_Bench_EXOR IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Module_EXOR
PORT(
A : IN std_logic;
B : IN std_logic;
X : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';

--Outputs
signal X : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--

constant <clock>_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Module_EXOR PORT MAP (
A => A,
B => B,
X => X
);
--------

-- Clock process definitions

<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
A <= not A;
end process;
stim_proc1: process
begin
wait for 50 ns;
B <= not B;
end process;

END;

Compuerta XNOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Module_EXNOR is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC);
end Module_EXNOR;
architecture Behavioral of Module_EXNOR is
begin
X <= (A and B) or ((not A) and (not B));
end Behavioral;
........................................
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_Bench_EXNOR IS
END Test_Bench_EXNOR;
ARCHITECTURE behavior OF Test_Bench_EXNOR IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Module_EXNOR
PORT(
A : IN std_logic;
B : IN std_logic;
X : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';

--Outputs
signal X : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--

constant <clock>_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Module_EXNOR PORT MAP (
A => A,
B => B,
X => X
);
--------

-- Clock process definitions

<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
A <= not A;
end process;
stim_proc1: process
begin
wait for 50 ns;
B <= not B;
end process;

END;

Compuerta NOR
MODULE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Module_NOR is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC);
end Module_NOR;
architecture Behavioral of Module_NOR is
begin
X <= not (A or B);
end Behavioral;
.........................................
TEST BENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_Bench_NOR IS
END Test_Bench_NOR;
ARCHITECTURE behavior OF Test_Bench_NOR IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Module_NOR
PORT(
A : IN std_logic;
B : IN std_logic;
X : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';

--Outputs
signal X : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--

constant <clock>_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Module_NOR PORT MAP (
A => A,
B => B,
X => X
);
--------

-- Clock process definitions

<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
A <= not A;
end process;
stim_proc1: process
begin
wait for 50 ns;
B <= not B;
end process;

END;

CONCLUSIONES
Actualmente cualquier proceso de investigacion dispone de un soporte software
que asiste al usuario en el desarrollo de sistemas complejos. Los sistemas
electronicos reconfigurables del tipo FPGA son un buen ejemplo de complejidad
que se puede alcanzar, esta complejidad no seria abarcable sin ayuda de un
entorno con herramientas que asistan

en el proceso de diseo, simulacion,

sintesis del resultado y configuracion del hardware.