Subject-Digital Circuit & System (CS - 303)

Important Question
UNIT I
Question 2 MarksQ.1
Q.2
Q.3

Convert the following.

(i) (27.125)10 = ( ) 8 = ( )2 (ii) (1011010111)2 = ( ) gray
Explain Minterm and Maxterm.
Convert the following .(Any Two) )
(i) (27.125)10 = ( )8 = ( )2
(ii)

(237)8 = ( )10

(iii) (249)10 = ( )16 = ( )2

(iv) (20.305) = ( )BCD
Q.4
Q.5

State and prove De-Morgans Theorem.

Explain SOP and POS form.

Question 3 MarksQ.1
Q.2
Q.3
Q.4
Q.5

Minimize the following function using Boolean algebra.

ABC + ( B + C) ( B + D) + (A+C+D)
Y = AB + AB , simplify Boolean equation and the corresponding logic circuit .
Prove the following Boolean expression.
(i) (A + B) (AB + C ) (B + AC) = AB
Reduce the following expression using Boolean Algebra:
(i)
ABC + ABC + ABC + ABC
What is K-map? Why we need K-maps? Give the various types of K-map.

Question 7 MarksQ.1
Q.2

Minimize the logic function(A,B,C,D) = m(0,1,2,3,5,7,8,9,11,14) . Use Karnaugh map.

Minimize the following function using Karnaugh Map Method and realizes using NAND
Gates.
F(A,B,C,D) = m (1,3,5,8,9,11,15)+d(2,13)

Q.3

Minimize the following function using Quine & McCluskey method

F (A, B, C, D) = m (1, 4, 6,7,8,9,10,11,15

Q.4

Simplify and draw the logic diagram for the given expression
F = ABC + AB C + ABC + A BC + A B C

Q.5

Minimize the following function using Karnaugh Map Method and realizes using NAND
gates.
F(A, B, C, D) = m( 1,4,5,6,11,12,13,14,15)
UNIT II

Question 2 MarksQ.1
Q.2
Q.3

Realize the following function using NAND Gate.

Y = A + BCD
Explain Combinational & Sequential Circuit.
Explain half adder circuit.

Q.4
Q.5

Design all logic gates using Universal Gates.

Write Truth Table all logic gates.

Question 3 MarksQ.1
Q.2
Q.3
Q.4
Q.5

What are the Half Subtractor?

Explain 4 bit Parallel adder.
Design BCD adder using logic gates.
State the procedure for designing combinational circuit.
Implement F= A (B + CD) + BC using NAND gates only.

Question 7 MarksQ.1
Q.2
Q.3
Q.4
Q.5

Design Full subtractor with two half subtractor and an OR Gate.

Design a look ahead carry generator.
Implement Y = (AB) + A + (B+C) using NAND Gates Only.
Design a full adder using two half adder.
Explain serial and parallel adder.
UNIT III

Question 2 MarksQ.1
Q.2
Q.3
Q.4
Q.5

Explain linear wave shaping Circuits.

Explain logic families.
Define fan in and fan out.
Explain multivibrator.
Explain RTL circuit

Question 3 MarksQ.1
Q.2
Q.3
Q.4
Q.5

Why MOS logic families are preferred over TTL logic families?
Discuss the operation of Integrated Injection Logic.
Explain the working of CMOS Inverter.
How is interfacing TTL to MOS.
Draw and explain NMOS NAND gate.

Question 7 MarksQ.1
Q.2
Q.3
Q.4

Draw and explain operation of an astable multivibrator.

Explain the working of Schottky TTL gate
With the help of circuit diagram explain the working of Bistable multivibrator.
Explain PMOS and NMOS.

Q.5

Compare the DTL, TTL, RTL and ECL logic.

UNIT IV

Question 2 MarksQ.1
Q.2
Q.3
Q.4
Q.5

What is multiplexer tree?

Explain decoder circuit
Explain shift register.
Explain counter.
Explain synchronous counter

Question 3 MarksQ.1
Q.2
Q.3
Q.4
Q.5

Explain 4*1 multiplexer.

Explain Demultiplexer.
Design a Mod-4 counter
Design a BCD to decimal decoders..
Implement a full adder with 3*8 decoder..

Question 7 MarksQ.1
Q.2
Q.3
Q.4
Q.5

Realize the following function using multiplexer.

Y = m(0,3,5,7,11,14)
What is a multiplexer? Design a 16*1 MUX using 4*1 and 2*1 MUX.
What is PLA? What is the difference between a PLA and ROM?
Design a MOD4 Counter using T Flip Flop.
Design and explain 1*8 demultiplexer.
UNIT V

Question 2 MarksQ.1
Q.2

What is analog and digital converter?

Explain sample and hold circuit.

Question 3 MarksQ.1
Q.2

Explain R-2R ladder type D/A converter.

Explain the principle working of V-F converter.

Question 7 MarksQ.1
Q.2

Explain with the help of block diagram any one type of analog to digital converter
Explain single and dual slope D/A converter.