IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO.

2, FEBRUARY 2014

569

Dual Three-Phase Indirect Matrix Converter With

Carrier-Based PWM Method
Tuyen D. Nguyen, Member, IEEE, and Hong-Hee Lee, Senior Member, IEEE

AbstractThis paper proposes an indirect matrix converter

(IMC) topology with dual three-phase outputs and its effective
carrier-based pulse width modulation (PWM) method. The proposed IMC topology can independently supply ac power for two
three-phase loads from a single three-phase ac power source. This
converter consists of a rectifier stage used in traditional three-phase
IMC and a five-leg inverter. Besides a proposed IMC topology, the
carrier-based PWM method suitable for this converter is also introduced. The proposed PWM method is easily implemented by
using only one symmetrical triangular carrier signal to generate
the PWM signals for a rectifier and five-leg inverter. Proposed
IMC topology features the advantages of conventional three-phase
IMC, such as sinusoidal input/output current waveforms, controllable input power factor, and simple commutation at the rectifier
stage. Analysis, simulation, and experimental results are provided
to demonstrate the advantages of the proposed IMC topology with
dual three-phase outputs and to validate the effectiveness of the
applied modulation strategy.

Fig. 1.

DMC topology.

Fig. 2.

IMC topology.

Index TermsCarrier-based pulse width modulation (PWM),

direct matrix converter (DMC), dual inverters, five-leg inverter,
indirect matrix converter (IMC), space vector PWM (SVPWM).

I. INTRODUCTION
HE three-phase to three-phase ac/ac matrix converters
(MCs) are originally presented in [1]. MCs allow direct
ac/ac power conversion without the dc energy storage component. They have recently received considerable attention as an alternative to the conventional ac/ac converter, which is composed
of rectifier/dc-link capacitor/inverter structures. MCs have many
advantages such as sinusoidal input and output current waveforms, unity power factor at the input side, increased power
density, and inherent four-quadrant operation. In addition, MCs
are highly reliable and durable due to the lack of a dc-link
electrolytic capacitor for energy storage [2].
MCs are classified into two types: direct matrix converters (DMC) and indirect matrix converters (IMC). The DMC
is a one stage ac/ac direct converter, where three-phase input

Manuscript received September 6, 2012; revised November 26, 2012, January

15, 2013, and February 7, 2013; accepted March 12, 2013. Date of current
version August 20, 2013. This work was supported by the National Research
Foundation of Korea (NRF) grant funded by the Korea government (MEST)
under Grant 2010-0025483. Recommended for publication by Associate Editor
J. R. Rodriguez.
T. D. Nguyen is with the Faculty of Electrical and Electronics Engineering,
Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam
(e-mail: ndtuyen@hcmut.edu.vn).
H.-H. Lee is with the School of Electrical Engineering, University of Ulsan,
Ulsan 680-749, Korea (e-mail: hhlee@mail.ulsan.ac.kr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2013.2255067

voltages are directly connected to three-phase output loads

through nine bidirectional switches as shown in Fig. 1 [3], [4].
On the other hand, the IMC topology is based on the ac/dc/ac
power conversion with no intermediate capacitor. The IMC comprises two stages such as rectifier stage and inverter stage, which
are illustrated in Fig. 2 [5][13]. DMC and IMC provide the
same input/output performance, maximum voltage transfer ratio, and number of power switches. However, the IMC topology
provides a soft switching commutation that is not applicable in
DMC. Furthermore, the IMC needs the simpler clamp circuit
for overvoltage protection as compared to the DMC.
IMC topology has recently been widely discussed and many
researchers have developed the various IMC topologies suitable
for specific applications. Kolar et al. [14][16] concentrated
to modify the rectifier stage structure with the reduced power
devices by utilizing the zero current commutation. In part of
the inverter stage, some novel IMC topologies have recently
been proposed such as the hybrid IMC [17], [18] and Z-source
IMC [19], [20] to increase the output voltage transfer ratio, the
four-leg IMC for unbalanced loads [21], and the multilevel IMC
to improve the output voltage quality [22], [23].

0885-8993 2013 IEEE

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 2, FEBRUARY 2014

Fig. 5.

Fig. 3. Dual three-phase output IMC topology based on the parallel connection
of two three-leg inverters.

Fig. 4. Dual three-phase output IMC topology based on the nine-switch

inverter.

On the other hand, the IMC with dual three-phase outputs

is also introduced in order to reduce the total cost and system volume [24], [25]. Dual ac-drive systems from conventional voltage source inverter (VSI) have been studied for special industrial applications such as electric vehicles, railway
traction system, steel processing, textile manufacturing, and
winders [26][33]. However, they have the same drawbacks associated with the rectifier/dc-link capacitor/inverter conversion
system. Dual three-phase outputs IMC topology consists of an
input stage and two output stages with a pair of conventional
three-leg inverters, as shown in Fig. 3. The drawback of this
topology is the large number of power switches in the inverter
stage, 12 power switches are used in the inverter stage. Another
approach to the IMC topology is proposed in [34] for independent control of two three-phase loads with fewer reduced power
switches. This topology is based on the traditional IMC, but the
inverter stage is replaced by a nine-switch inverter as shown in
Fig. 4. Even if this topology works with reduced numbers of
power switches, the switch capacity in the nine-switch inverter
stage is doubled.

Proposed dual three-phase output IMC topology.

In order to overcome the disadvantages in the previous IMC

topologies as shown in Figs. 3 and 4, this paper proposes the
IMC topology composed from a five-leg inverter connected to
a rectifier stage to generate dual three-phase outputs effectively
by using a common leg supplying both of two loads, which
is shown in Fig. 5. As shown in Fig. 5, two phases of each
load are supplied independently from four legs of the inverter
stage while each remaining phase for the two loads is connected
to the same leg. The proposed IMC topology can reduce two
power switches, in comparison to the conventional IMC topology shown in Fig. 3, and can halve the switch capacity compared
to the IMC topology with nine-switch inverter stage shown in
Fig. 4 except the switches in leg C due to the common current
path for both the currents of load 1 and load 2. Moreover, the
number of power switch in the proposed topology can be reduced by three in the case of unidirectional power flow from the
power supply to the loads.
Besides interest in the IMC topology for particular applications, modulation methods to effectively drive IMC have also
been investigated in recent technical publications. The space
vector PWM (SVPWM) method has been generally used to
control IMC because it has a good performance such as a lower
current harmonic and higher modulation index [5][10]. However, this method needs many calculations and lookup tables
to generate the switching pattern. On one hand, the carrierbased PWM method has been presented for three to three phase
IMC [35], [36]. However, the carrier signal used for the rectifier
stage is different from that of the inverter stage. The carrier signal used for the rectifier stage is a symmetrical triangular signal
with constant frequency, while the carrier signal with different
slope in the rising and falling edge is used for the inverter stage.
Furthermore, these slopes of the carrier signal are changed in
every sampling period due to the variation of the dc-link voltage.
In this paper, in order to overcome the limitation of the SVPWM
and the conventional carrier-based PWM method, we introduce
the carrier-based PWM method for the proposed IMC topology,
which uses only one symmetrical triangular carrier signal with
constant frequency and magnitude to generate PWM signals
for all switches of both the rectifier and five-leg inverter stage.
The proposed carrier-based PWM method can be implemented
easily by using only one up/down counter, which is available

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571

in most of digital signal processors. The proposed modulation

method is established based on space vector analysis.
This paper is organized as follows: the operational principles
and the SVPWM for the proposed IMC topology are introduced
in Section II. Section III describes the proposed carrier-based
PWM method, which is based on the space vector analysis in
Section II. Simulations studies and experiments on two threephase inductive loads are implemented and provided in Sections
IV and V, respectively, to demonstrate that two three-phase loads
are fed independently from single three-phase power supply.
Finally, Section VI offers some conclusions.
II. OPERATIONAL PRINCIPLES OF THE PROPOSED IMC
TOPOLOGY WITH DUAL THREE-PHASE OUTPUTS
In order to explain the operational principles of the proposed
IMC topology, we use the space vector theory, which is a wellknown technique commonly adopted in the previous technical
literatures. As shown in Fig. 5, the proposed topology comprises
a rectifier stage connected to a five-leg inverter stage. The target of the rectifier stages is to generate the maximum dc output
voltage at the dc-link bus as well as to produce the sinusoidal
input current waveforms. The desired output voltages with variable frequency for two loads can be obtained by controlling the
five-leg inverter stage. The rectifier stage is controlled based on
the reference input current vector, and the five-leg inverter stage
is controlled based on two reference output voltage vectors of
two loads. The two stages are controlled separately and both
switching patterns of the two stages are synthesized together.
A. Rectifier Stage Control
The rectifier stage is connected to a three-phase power supply
with constant amplitude and frequency. It is assumed that threephase input voltages are balanced as follows:

Fig. 6. Space vector diagram and the generation of reference input current
vector in the rectifier stage.

input current vector is located in sector 1(/6 i /6)

and lags behind the input voltage vector with the angle . The
duty cycle of the active vectors for the rectifier stage Iab and Iac
are determined as follows:
d = mi sin (/6 (i ))

(4)

d = mi sin (i + /6)

(5)

where mi is the rectifier stage modulation index.

Because the zero vectors are not used to synthesis the reference input current vector, the duty ratio d and d for two active
vectors Iab and Iac are recalculated as follows:
dx =

d
cos (i 2/3 )
=
d + d
cos (i )

(6)

dy =

d
cos (i 4/3 )
.
=
d + d
cos (i )

(7)

va = Vi cos (i t)
vb = Vi cos (i t 2/3)
vc = Vi cos (i t+2/3)

(1)

where Vi and i are the amplitude and angular frequency of the

input phase voltage, respectively.
We can describe the input current vector and input voltage
vector as follows:


ii = 2 ia + ib ej 2 /3 + ic ej 4 /3 = Ii ej i
(2)
3

2
vi =
(3)
va + vb ej 2 /3 + vc ej 4 /3 = Vi ej i
3
where i and i are current and voltage phase angles,
respectively.
Fig. 6 shows the space vector diagram of the rectifier stage.
Each active current vector represents the switching condition
between the input phase voltage and the dc-link bus. For example, the current vector Iab represents the input phase a and
b are connected to the positive pole and the negative pole of
dc-link bus, respectively. The zero vector means that the input
voltage is not applied to dc-link bus. Assume that the reference

The dc-link voltage has two values, vba with the duty cycle
dx , and vca with the duty cycle dy . Thus, the average value of
the dc-link voltage in one sampling period is
Vi
3
cos .
2 cos (i )
(8)
From (8), the minimum value of the Vdc is

Vdc = dx (va vb ) + dy (va vc ) =

Vdc(m in) =

3
Vi cos .
2

(9)

Depending on the position of the reference input current vector, suitable active vectors are chosen to generate the dc-link
voltage. By similar analysis, Table I summarizes the switching
state of all power switches, the corresponding dc-link voltage
and its average value according to the input current sector. In the
odd sector, the upper switch of the positive input phase voltage
is in the ON state at any time, and two lower switches of two
negative input phase voltages are modulated. In the other case
(i.e., in the even sector), the lower switch of the negative input

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TABLE I
MODULATED SWITCHES AND DC-LINK VOLTAGE ACCORDING TO THE INPUT CURRENT SECTOR

and the reference output phase voltages of the load 2 are

vA2 = Vo2 cos (o2 t + o2 )
vB 2 = Vo2 cos (o2 t + o2 2/3)
vC 2 = Vo2 cos (o2 t + o2 + 2/3)

Fig. 7.

Generation of reference output voltage for (a) Load 1. (b) Load 2.

phase voltage is in the ON state, and two upper switches of two

positive input phase voltages are modulated.
B. Five-Leg Inverter Stage Control
The SVPWM techniques have been widely used in inverter
control due to the lower current harmonic and higher modulation
index. The purpose of the SVPWM technique is to generate the
reference output voltage vector by conjoining the switching
states corresponding to the active and zero vectors. Fig. 7(a)
and (b) illustrates the active vectors, the zero vectors, and the
position of the reference output voltage vector in the case of
load 1 and load 2, respectively. The eight space vectors are used
in the SVPWM technique, where V1 V6 are active vectors, and
V0 and V7 are zero vectors. Each vector is denoted by the set
of switching functions: [SA SB SC] in the case of load 1, and
[SE SD SC] in the case of load 2. The switching function of the
upper switch in each leg is defined as

1 if SX is ON state
SX =
X = A E.
(10)
0 if SX is OFF state
It is assumed that the reference output phase voltages of the
load 1 are
vA 1 = Vo1 cos (o1 t + o1 )

where Vo1 , o 1 , and o 1 are the amplitude, angular frequency, and initial phase of the output phase voltage of load 1,
respectively.
Vo2 , o2 , and o2 are the amplitude, angular frequency, and
initial phase of the output phase voltage of load 2, respectively.
We can describe the reference output voltage vectors of two
loads as follows:

2
vA1 + vB1 ej 2 /3 + vC1 ej 4 /3 = Vo1 ej o 1 (13)
vo1 =
3

2
vA2 + vB2 ej 2 /3 + vC2 ej 4 /3 = Vo2 ej o 2 (14)
vo2 =
3
where o 1 and o 2 are the angles between each reference output
voltage vector and the basic active vector V1 as shown in Fig. 7.
Without loss of generality, the reference output voltage vectors of load 1 and load 2 are assumed to be located in sector
1 (0o1 /3) and sector 2 (/3o2 2/3), respectively.
From Fig. 7(a) and (b), the reference output voltage vector of
the two loads can be synthesized as follows:

(11)

1 + T2(1) V
2
vo1 = T1(1) V

(15)

2 + T3(2) V
3 .
vo2 = T2(2) V

(16)

Therefore, the application time of active vectors and zero

vectors of load 1 are written as
Vo1
3
Ts sin (/3 o1 )
Vdc
Vo1
= 3
Ts sin (o1 )
Vdc

1
Ts T1(1) T2(1)
= T0(1) =
2

T1(1) =

(17)

T2(1)

(18)

vB 1 = Vo1 cos (o1 t + o1 2/3)

vC 1 = Vo1 cos (o1 t + o1 + 2/3)

(12)

T7(1)

(19)

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Fig. 8. Switching pattern of load 1 when the reference output voltage vector
is in sector 1.

Fig. 10.

573

Switching pattern for the five-leg inverter stage.

Fig. 10 shows the symmetric switching scheme of the five-leg

inverter stage when two phases of two loads are connected to
the same point at leg C. It can be seen that the distribution of
application time for active vectors of each load is unchanged.
The distribution of application time for zero vectors V0 and V7
of each load is changed; however, the amount of application
time of zero vectors is kept constant.
Fig. 9. Switching pattern of load 2 when the reference output voltage vector
is in sector 2.

C. Maximum Voltage Transfer Ratio

The application time of all switches in the five-leg inverter
stage has to be positive. Therefore, we can obtain (28) from
(17)(27)

and those of load 2 are written as

Vo2
3
Ts sin (2/3 o2 )
Vdc
Vo2
= 3
Ts sin (o2 /3)
VDC

1
Ts T2(2) T3(2) .
= T0(2) =
2

T2(2) =

(20)

Vdc
Vo1 + Vo2 .
3

T3(2)

(21)

If we define q1 and q2 as the voltage transfer ratio of load 1

and load 2, respectively, then the voltage transfer ratios become

T7(2)

(22)

The symmetric arrangement of two active vectors and two

zero vectors of load 1 and load 2 are shown in Figs. 8 and 9,
respectively. Also, the sequence and the application time of all
upper switches are shown individually for each output load.
Two loads share the common leg C. Therefore, the two upper
switches of phases C1 and C2 have the same application time.
Hence, the application time for zero vectors V0 and V7 of two
loads should be changed, while the application time for active
vectors is unchanged to ensure that the magnitude of two reference output voltages are kept constant. The application time
of all upper switches of the five-leg inverter in one sampling
period is determined as follows:
TA = T7(1) + T2(1) + T1(1) + T7(2)
TB = T7(1) + T2(1) + T7(2)
TC = T7(1) + T7(2)

Ts
2

Ts
2

(25)

TD = T7(2) + T2(2) + T7(1) + T3(2)

TE = T7(2) + T2(2) + T7(1)

Ts
.
2

Ts
2

q1 =

Vo1
Vi

(29)

q2 =

Vo2
.
Vi

(30)

From (9) and (28), there is the constraint of output voltages

for two loads such as

3
cos .
(31)
q1 + q 2
2
From (31), we can see the maximum voltage transfer ratio,
0.866, is obtained under the unity power factor constraint (
= 0). However, the maximum voltage transfer ratio becomes
smaller by the factor cos for nonunity input power factor.
D. Switching Patterns and the Safe Commutation

(23)
(24)

Ts
2

(28)

(26)
(27)

In one sampling period the dc-link voltage has two values,

which depend on the switching state of the rectifier stage. Therefore, the five-leg inverter is fed by two positive line-to-line input
voltages. In order to obtain the balanced output voltages within
a sampling period, the switching pattern of the converter has to
mix the switching states of the rectifier stage and the five-leg
inverter stage.
Considering one half of sampling period Ts /2, the values of
the dc-link voltage are two line-to-line input voltages vab and vac
with the duration Tbn = dx Ts /2 and Tcn = dy Ts /2, respectively.

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Fig. 12. Closed-loop control block diagram based on the proposed carrierbased PWM method.

Fig. 11.

Switching states of the rectifier and inverter stages.

Consequently, the application time of all upper switches in the

five-leg inverter stage is separated into two parts. These values
are obtained by the cross product of the duty ratio of the rectifier
stage and the application time of the switches in the inverter
stage as follows:
TA (ab) = TA dx /2; TA (ac) = TA dy /2

(32)

TB (ab) = TB dx /2; TB (ac) = TB dy /2

(33)

TC (ab) = TC dx /2; TC (ac) = TC dy /2

(34)

TD (ab) = TD dx /2; TD (ac) = TD dy /2

(35)

TE (ab) = TE dx /2; TE (ac) = TE dy /2.

(36)

The switching states of the rectifier stage and the five-leg

inverter stage are arranged as shown in Fig. 11 in order to
maintain the zero dc-link current commutation at the rectifier
stage. The commutation of the rectifier stage always happens
during the time when the zero vectors in the five-leg inverter
stage are applied to synthesize two reference output voltage
vectors. Therefore, the complex multistep commutation can be
avoided. Furthermore, the switching losses in the rectifier stage
are reduced by applying the zero dc-link current commutation.
In the inverter stage, a complementary signal controls the upper
and lower switch in the same leg. Therefore, safe operation of
the inverter stage is implemented by the conventional dead-time
commutation.
III. CARRIER-BASED PWM METHOD FOR DUAL
THREE-PHASE OUTPUTS
Two independent SVPWMs are used to analyze the rectifier
and five-leg inverter stages. As aforementioned, there are six
switching patterns in the rectifier stage and 32 switching patterns in the inverter stage. The switching patterns of the whole

system are obtained by coordinating the switching states of the

rectifier and five-leg inverter stages. Therefore, the space vector
modulation approach for the proposed converter needs many calculations and tables to obtain the switching patterns according
to the positions of input current vector and two output reference
voltage vectors. In order to simplify the control technique, the
carrier-based PWM method is developed instead of SVPWM.
Fig. 12 shows the closed-loop control block diagram of the
proposed IMC based on the carrier-based PWM method. After
detecting the three-phase output voltages for each load, they
are transformed to dc values in the dq rotating reference frame.
The desired output voltages are compared with the measured
voltages, and the reference output voltages, which are used to
calculate the modulation signals, are generated through the PI
voltage controller.
In the carrier-based PWM method, the PWM signals are generated by comparing the modulation signals with a triangular
carrier signal. The modulation signals are calculated based on
the duty cycles in the rectifier stage, the average value of dclink voltage and the reference output voltages. To correlate the
SVPWM with the carrier-based PWM, the set of modulation
signals have to be obtained to generate the same PWM signals as the SVPWM method. The proposed carrier-based PWM
method is discussed in detail in the following sections.

A. Carrier-Based PWM for the Rectifier Stage

In the carrier-based PWM method, the PWM signals are generated by comparing the modulation signals with a triangular
carrier signal. To correlate the SVPWM with the carrier-based
PWM, the set of modulation signals (which are compared with
the carrier signal) have to be obtained to generate the same
PWM signals as the SVPWM method.
Fig. 13(a) illustrates the sequence and timing of modulated
switches in the rectifier stage when the reference input current
vector is in sector 1. In half of a sampling period, the duration
Tap , Tbn , and Tcn of the gating pulses for switches Sap , Sbn ,

NGUYEN AND LEE: DUAL THREE-PHASE INDIRECT MATRIX CONVERTER WITH CARRIER-BASED PWM METHOD

575

Fig. 13. (a) Sequence and timing of effective switches in the rectifier stage.
(b) Modulation signals and symmetrical carrier signals to generate PWMs for
the rectifier stage.

and Scn are

Tap =

Ts
Ts
Ts
; Tbn = dx ; Tcn = dy .
2
2
2

(37)

Fig. 13(b) shows two modulation signals vap and vbn , and
the triangular carrier signal vt . The gating pulses for the switch
Sap and Sbn are obtained from the intersection between the
modulation signals vap and vbn and the carrier signal. The gate
pulse for switch Scn is complementary to that of switch Sbn .
As shown in Fig. 13(b), the symmetrical triangular carrier
signal can be described by


4
vt =
t 1 Vi , 0 t T2s
(38)
Ts
where vt and Vi are the instantaneous and peak value of the
carrier signal, respectively.
Therefore, the modulation signals for the rectifier stage are
easily obtained from (37) and (38)
vap = Vi ; vbn = (2dx 1) Vi .

(39)

All remaining switches (San , Sbp , Scp ) are OFF state. Therefore, the modulation signals, which are used to generate gating
pulses for these switches, are determined as follows:
van = Vi ; vbp = Vi ; vcp = Vi .

(40)

B. Carrier-Based PWM for Five-Leg Inverter

Fig. 14(a) shows the sequence and the application time of all
upper switches in the five-leg inverter stage. In one half sampling period, the switching period of each switch is divided into
two parts with unequal values. For example, the application time
of the upper switch of leg A (TA /2) is separated into two values
TA (ab) and TA (ac) , which are determined in (32). The duration
time TA (ab) has to be applied to the switch SA when the dc-link
voltage is vab ; otherwise, the duration time TA (ac) has to be
applied when the dc-link voltage is vac . Unlike in the case of
the rectifier stage (where the switching frequency is equal to the
carrier signal frequency), the switching frequency in the fiveleg inverter stage is twice that of the carrier signal. Therefore,

Fig. 14. (a) Switching pattern of the five-leg inverter stage. (b) Waveforms of
two modulation signals and carrier signal. (c) PWM waveforms for switch S A .

we cannot use one modulation signal that is compared with the

carrier signal to generate a gate signal in the inverter stage. In order to elucidate the proposed carrier-based PWM in the inverter
stage, we consider how to generate the gate signal for the switch
SA . To create the gate signal for switch SA , two modulation
signals are needed. Fig. 14(b) shows two modulations signals
vA (upp er) and vA (lower) , and the carrier signal. The PWM0 and
PWM1 are the results of comparing two modulation signals with
the carrier signal. As shown in Fig. 14(c), the switching pattern
of switch S A is obtained by
SA = PWM0 PWM1 + PWM0 PWM1.

(41)

We then have to determine the instantaneous value of two

modulation signals. The time intervals TA (upp er) and TA (lower)
in Fig. 14(b) are calculated as follows:
TA (upp er) =

1
Ts
Ts
TA (ac) =

2
2
2


Ts
T7(1) +T1(1) +T2(1) +T7(2)
dy
2

(42)

1
TA (lower) = TA (ab) =
2


Ts
T7(1) +T1(1) +T2(1) +T7(2)
dx . (43)
2
By substituting TA (upp er) and TA (lower) from (42) and (43)
into (38) for variable t, two modulation signals vA (upp er) and
vA (lower) are obtained as follows:


vA 1 + vC 2 + voset1 + voset2
vA (upp er) = Vi 2dy
+
d
x
Vdc
(44)

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 2, FEBRUARY 2014


vA (lower) = Vi

vA 1 + vC 2 + voset1 + voset2
dy
2dx
Vdc

(45)
where voset1 and voset2 are two offset voltages, which are
written as
voset 1 = 0.5vA 1 0.5vC 1

(46)

voset 1 = 0.5vB 2 0.5vC 2 .

(47)

Likewise, the couple of modulation signals, which are used

to generate PWM signals for the remaining upper switches SX
(X = B E), are obtained as follows:


vB 1 + vC 2 + voset1 + voset2
+ dx
vB (upp er) = Vi 2dy
Vdc

vB (lower) = Vi 2dx

vB 1 + vC 2 + voset1 + voset2
dy
Vdc


vC (upp er) = Vi 2dy

vC (lower) = Vi 2dx

vD (upp er) = Vi 2dy

vD (lower) = Vi 2dx

vE (upp er) = Vi 2dy

vE (lower) = Vi 2dx

vA 2 + vC 1 + voset1 + voset2
Vdc

vA 2 + vC 1 + voset1 + voset2
Vdc

(50)


(51)

+ dx

vB 2 + vC 1 + voset1 + voset2
dy
Vdc

vB 2 + vC 1 + voset1 + voset2
Vdc

(52)

Fig. 16.

(53)

+ dx

(54)

dy .

(55)
Equations (44)(55) are established under the assumption
that the reference output voltages of loads 1 and 2 are located
in sectors 1 and 2, respectively. However, these results are valid
for all the other sectors when two offset voltages are chosen as
(56)
voset1 = 0.5 (vm ax 1 + vm in 1 )
voset2 = 0.5 (vm ax 2 + vm in 2 )

(57)

where
vm ax 1 = max (vA 1 , vB 1 , vC 1 ) ; vm in 1
= min (vA 1 , vB 1 , vC 1 )

(58)

vm ax 2 = max (vA 2 , vB 2 , vC 2 ) ; vm in 2
= min (vA 2 , vB 2 , vC 2 ) .

Fig. 15. Couple modulation signals v A (u p p e r) and v A (low e r) to generate the

gate signal for switch S A (a) f1 = f2 = 50 Hz. (b) f1 = 50 Hz, f2 = 100 Hz.

(49)

+ dx

vC 1 + vC 2 + voset1 + voset2
dy
Vdc

vC 1 + vC 2 + voset1 + voset2
Vdc

(48)


(59)

Block diagram of the proposed carrier-based PWM method.

Fig. 15 shows the waveforms of the normalized modulation

signals vA (upp er) and vA (lower) at the output frequencies: f1 =
f2 = 50 Hz and f1 = 50 Hz, f2 = 100 Hz, where f1 and
f2 are output frequencies of load 1 and load 2, respectively.
In case of the conventional VSI, the modulation signals have
sinusoidal waveforms because they have the only information
about the reference output voltage. However, the modulation
signals in the inverter stage contain the information about both
input voltage and reference output voltage in (44) and (45), so
that they cannot be sinusoidal as shown in Fig. 15.
The principle of the proposed carrier-based PWM method
explained up to now is shown in Fig. 16, which shows how to
generate gating signals for six bidirectional switches in the rectifier stage and ten unidirectional switches in the inverter stage.
All required functions are easily implemented without a lookup
table or complex calculations, and there is no need to coordinate
the switching state of the rectifier and five-leg inverter stages.
The performance of the proposed modulation is the same as that
of the SVPWM including the zero current commutation of the
rectifier stage because the proposed carrier-based PWM method
is derived based on the mathematical analysis with SVPWM.

NGUYEN AND LEE: DUAL THREE-PHASE INDIRECT MATRIX CONVERTER WITH CARRIER-BASED PWM METHOD

577

Fig. 17. Simulation waveforms of input voltage/current and output currents

under in-phase CF mode.
Fig. 19. Simulation waveforms of input voltage/current and output currents
under DF mode.

Fig. 18. Simulation waveforms of input voltage/current and currents under

CF mode with the phase shift 45 .

IV. SIMULATION RESULTS

The proposed IMC topology with dual three-phase outputs
shown in Fig. 5 has been simulated using Psim 9.0 software. In
this simulation, the proposed IMC is evaluated using two threephase RL loads. The simulation parameters are as follows:
1) three-phase power supply: the input line-to-line voltage is
200 V and the input frequency is 60 Hz;
2) LC input filter: L = 1.4 mH, C = 27 F;
3) the carrier signal frequency is 10 kHz (Ts = 100 s);
4) threephase RL load 1: R = 10 , L = 5 mH;
5) threephase RL load 2: R = 12 , L = 5 mH.
The performance of the proposed dual three-phase output
IMC with the carrier based-PWM modulation method is evaluated for two cases to determine whether it has similar performance as two independent three-phase IMCs: common output
terminal frequency (CF mode) and different output terminal
frequency (DF mode). For each case, the desired output frequencies (f1 , f2 ) and the voltage transfer ratios (q1 , q2 ) are set
as follows: in CF mode, f1 = 50 Hz, q1 = 0.3 for load 1, and
the f2 = 50 Hz, q2 = 0.5 for load 2; in DF mode, f1 = 50 Hz,
q1 = 0.3 for load 1, and the f2 = 100 Hz, q2 = 0.5 for load 2,
and open-loop control is applied.
Figs. 17 and 18 show the simulation results in CF mode
obtained by adjusting the current phase between two output
loads. Fig. 17 shows input voltage (va )/current (ia ) and output
currents of two loads in CF mode, when the output currents
of two loads, iA 1 and iA 2 are set in-phase. Both the input and
output current are sinusoidal waveforms. Due to the LC filter,

Fig. 20. Simulated waveforms of input voltage/current and output currents at

different load step: The load condition 1 changes from q1 = 0.25, f1 = 50 Hz
to q1 = 0.5, f1 = 100 Hz and the load condition 2 changes from q2 = 0.5, f2
= 100 Hz to q2 = 0.25, f2 = 50 Hz.

there is a displacement angle between the input current and input

voltage.
In order to verify that the output phase can be controlled
independently by using the proposed IMC, only current phase
commands is changed in Fig. 18 under the same conditions as
shown in Fig. 17; the current of load 1 lags behind that of load
2 by 45 , while the output frequencies remain the same. All
waveforms are the same as those shown in Fig. 17 except for
the output current phase difference, and the proposed IMC is
shown to control two output phases independently.
Fig. 19 shows the simulated waveforms of the input voltage/current and two output currents of two loads in DF mode.
Similar to the CF mode, the input/output currents have good
sinusoidal waveforms with the desired frequencies.
Fig. 20 shows the input voltage/current and two output currents of two loads in DF mode when the load condition 1 changes
from q1 = 0.25, f1 = 50 Hz to q1 = 0.5, f1 = 100 Hz and the load
condition 2 changes from q2 = 0.5, f2 = 100 Hz to q2 = 0.25,
f2 = 50 Hz. We can see the proposed converter maintains the
sinusoidal input/output currents and good dynamic performance
even though the load condition changes suddenly.
Fig. 21 shows the transient responses of the input current and
output voltages with the closed-loop V /f control. The output
voltage reference of load 1 steps up from 20 to 30 V and the
frequency also steps up from 20 to 30 Hz. In case of the load

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 2, FEBRUARY 2014

Fig. 21. Simulated waveforms of input currents, output voltages of load 1 and
load 2 with closed-loop V/f control.

Fig. 22.

THD of the input current and output voltages.

Fig. 24. Laboratory setup of the proposed IMC experiment: (a) Controller
board. (b) Power circuit board.

Fig. 23.

Input power factor according to the voltage transfer ratio q1 and q2 .

2, the output voltage reference steps up from 30 to 60 V and

the frequency steps up from 30 to 60 Hz. It can be found that
the balanced and sinusoidal input currents and output voltages
are obtained, and the dynamic response of the output voltages
is very good.
The total harmonic distortion (THD) of the input current and
output voltages according to the output frequency variation are
shown in Fig. 22, where q1 = 0.3 and q2 = 0.5; THD of input
current is lower than 1.8% and THD of output voltages are
lower than 1.4%. Fig. 22 shows the proposed converter has a
good power quality. Fig. 23 shows the input power factor of
the converter according to the voltage transfer ratios for two

loads. The input power factor is almost unity when the total
voltage transfer ratio (q1 + q2 ) is near to the maximum voltage
transfer ratio 0.866, and the power factor characteristic of the
total voltage transfer ratio is almost the same as that of the
conventional IMC.
According to the simulated results, the proposed IMC topology provides the sinusoidal input current on both of input and output sides. Thus, the proposed carrier-based PWM
method can effectively control the proposed converter with highperformance current at the power supply and loads.
V. EXPERIMENTAL RESULTS
To validate the proposed theory and simulated results, an experimental platform is setup in the laboratory. Fig. 24 shows
the laboratory IMC with dual three-phase outputs. The prototype consists of a controller board that executes the control
program, A/D converter, the generating PWM signals, and the
power board. The controller board is developed with a highperformance DSP TMS320F28335 by Texas Instruments and
a complex programmable logic device EPM7128LC84-15 by
Altera. The power switch IGBTs G4PF50WD have been
used to implement the power circuit in the rectifier and the

NGUYEN AND LEE: DUAL THREE-PHASE INDIRECT MATRIX CONVERTER WITH CARRIER-BASED PWM METHOD

Fig. 25.

Zero-dc-link current commutation in the rectifier stage.

579

Fig. 28. Experimental waveforms of input voltage/current and output currents

under DF mode.

Fig. 26. Experimental waveforms of input voltage/current and output currents

under in-phase CF mode.
Fig. 29. Experimental waveforms of input voltage/current and output currents
as the load 1 change from q1 = 0.25, f1 = 50 Hz to q1 = 0.5, f1 = 100 Hz
and load 2 change from q2 = 0.5, f2 = 100 Hz to q2 = 0.25, f2 = 50 Hz.

Fig. 27. Experimental waveforms of input voltage/current and output currents

under CF mode with phase shift 45 .

inverter stage. The PWM control signals are isolated from power
circuit by fiber optic (HFBR-1521) to protect controller board.
The frequency of the triangular carrier signal is set as 10 kHz
by using the up/down counter, which is available in the DSP. It
should be noted that the experimental parameters and the case
studies are identical to those applied in the simulation.
Fig. 25 shows the dc-link current and the PWM signals for
two bidirectional switches (Sbn , Scn ) in the rectifier stage in
order to verify the current switching, and it is clear that the
commutation between Sbn and Scn occurs at the time when the
dc-link current is zero.
The experimental results shown in Figs. 2630 correspond
to the results shown through simulations shown in Figs. 1721,
and the experimental conditions and commands are exactly the
same as the corresponding conditions and commands used in

Fig. 30. Experimental waveforms of s of input currents, output voltages of

load 1 and load 2 with closed-loop control.

simulations. In Figs. 2630, the experimental results match the

simulation results exactly: the proposed IMC has a sinusoidal
input current and provides good sinusoidal currents to two independent loads. There is a displacement angle between the input
voltage and the input current of the power supply due to the
effect of filter.
Fig. 31 shows the experimental results of THD of the input
current, output voltages of load 1 and load 2 according to the
different output frequencies, where q1 = 0.3 and q2 = 0.5.

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Fig. 31.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 2, FEBRUARY 2014

Experimental results of THD of the input current and output voltages.

It can be seen that the experimentally obtained THD of the

input current is much higher than that from the simulation due
to the limitation of hardware setup and practical commutation
problem, where all of power switches and LC filter are not the
ideal devices. However, the performance of the output voltages
is comparatively excellent; the THD of output voltages of two
loads is smaller than 2.2%. From Figs. 26 to 31, we found that
the proposed dual three-phase output IMC with carrier basedPWM modulation method has good performance and operation
similar to that of two independent three-phase IMC.
VI. CONCLUSION
This paper describes a new approach to provide dual threephase sources for two three-phase loads based on IMC. The
proposed IMC topology reduces the number of power devices
by two, and is useful and economical in multidrive applications. The proposed converter provides sinusoidal input/output
currents, and has all the advantages of the IMC, such as the possibility of soft switching commutation in the rectifier stage and
the simple clamp circuit for safety operation. Also, the carrierbased PWM method (which is derived from the relationship
with SVPWM) is developed to control the proposed converter
effectively to overcome the complexity of the SVPWM method.
The algorithm uses only one carrier signal to generate the PWM
signals for all switches, including the rectifier stage and the inverter stage; therefore, it is easily implemented based on DSP.
In the proposed IMC, the maximum output voltage transfer ratio for each inverter cannot be 0.866 simultaneously; the sum
of two voltage transfer ratios is limited within 0.866. Simulation and experimental results demonstrate that the proposed
IMC topology and modulation techniques provide the expected
benefits.
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581

Tuyen D. Nguyen (M13) was born in BinhDinh,

Vietnam, in 1982. He received the B.S. degree in electrical engineering from Ho Chi Minh City University
of Technology, Vietnam, in 2004, and the Ph.D. degree from the University of Ulsan, Ulsan, Korea in
2012.
He is currently a Lecturer for the Faculty of Electrical and Electronics Engineering, Ho Chi Minh City
University of Technology. His research interests include power electronics, electrical machine drives,
low-cost inverter, and renewable energy, especially
matrix converters.

Hong-Hee Lee (S88M91SM11) received the

B.S., M.S., and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in
1980, 1982, and 1990, respectively.
From 1994 to 1995, he was a Visiting Professor
with Texas A&M University. Since 1985, he has been
with the Department of Electrical Engineering, University of Ulsan, Ulsan, Korea, where he is currently
a Professor in the School of Electrical Engineering.
He is also the Director of the Network-based Automation Research Center, which is sponsored by the
Ministry of Knowledge Economy. His research interests include power electronics, network-based motor control, and renewable energy.
Dr. Lee is a Member of the Korean Institute of Power Electronics, the Korean Institute of Electrical Engineers, and the Institute of Control, Robotics and
Systems.