EMBEDDED SYSTEMS: Memory

Pooja Bellad

September 5, 2014

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September 5, 2014

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Table of contents

Memory Interfacing

Memory Selection for Embedded Systems

Memory Shadowing

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Memory Interfacing

Memory Interfacing

Memory Selection for Embedded Systems

Memory Shadowing

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Memory Interfacing

8085 interfacing with memory Chips

Microprocessor need to access memory quite frequently to read
instructions and data stored in memory; the interface circuit enables that
access.

The interface process involves designing a circuit that will match the
memory requirements with the microprocessor signal. Memory has
certain signal requirements to read from and write into memory. Similarly
Microprocessor initiates the set of signals when it wants to read from and
write into memory

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Memory Interfacing

Memory Structure and its Requirements

Figure: R/W Static Memory

Figure shows:
2048 registers, register store 8-bits, 8 input, 8-output lines
11 address lines(AD10-AD0), 1 chip select, 2 control lines to enable
input and output buffer.
Internal decoder to decode address lines
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Memory Interfacing

Memory Structure and its Requirements

Generally EPROMs are used as programe memory and RAM as data
memory: Chip must be programmed before it can be used as ROM.

Figure: EPROM

Figure shows:
4096 registers, register store 8-bits, 8 input lines
12 address lines(A11-A0), 1 chip select, 1 Read control Signal lines
to enable output buffer
Internal decoder to decode address lines
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Memory Interfacing

Basic concepts of Memory Interfacing

For interfacing memory devices to 8085, keep the following points in

your mind:
8085 can access 64KB memory since address bus is 16-bit
Is is not always necessary to select 1 EPROM and 1 RAM. We can
have multiple EPROMs and multiple RAMs as per the rquirement of
application
The capacity of program memory and data memory depends on the
application
It is important to note that MP can communicate (read/write) with
only one device at a time, so address decoding needed

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Memory Interfacing

Address Decoding techniques

There are two main techniques:

Absolute decoding/ Full Decoding
Linear decoding / Partial Decoding

Absolute Decoding:
All the higher address lines are decoded to select the memory chip,
and the memory chip is selected only for the specified logic level on
these high-order address, no other logic levels can select the chip

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Memory Interfacing

Absolute Decoding Technique

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Memory Interfacing

Linear Decoding

In small systems, h/w for the decoding logic can be eliminated by

using individual high-order address lines to select memory chips
This technique is also called partial decoding
It reduces the cost of the decoding cct., but it has a drawback of
multiple address (shadow addresses)

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Memory Interfacing

Linear Decoding Cont...

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Memory Interfacing

Decoding type comparison

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Memory Interfacing

Memory interface summary

Select the chip

Identify the register
Enable the appropriate buffer
MP system includes memory and I/O devices
MP can communicate with only one device1
So decoding needed to communicate with memory and I/O
So each device can be accessed independently
Type of decoding

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Memory Selection for Embedded Systems

Memory Interfacing

Memory Selection for Embedded Systems

Memory Shadowing

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Memory Selection for Embedded Systems

Memory selection for embedded systems

Typically, one of the fundamental problems in high-performance

applications is memory, because the challenges and limitations of system
performance often reside in memory architectur. When you select an
memory, consider the following factors:
Bandwidth and speed
Cost
Data storage capacity
Latency
Power consumption

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Memory Shadowing

Memory Interfacing

Memory Selection for Embedded Systems

Memory Shadowing

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Memory Shadowing

Memory Shadowing

In general, ROM operates much more slowly than RAM. Because

hardware code is typically stored in ROM, performance can suffer
each time hardware code is executed.
Performance can be improved by copying code in the slow ROMs
into RAM, and executing the code from RAM instead.
The RAM that contains the copied code is called shadow RAM.
Although RAM shadowing can dramatically improve performance, it
uses some additional RAM, which is then no longer available to
applications.

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Memory Shadowing

How Does Shadow RAM Work?

80386 machines, and 80286 machines using the NEAT or LEAP chip
sets (from Chips Technologies), can remap memory addresses.
On such systems, the BIOS copies itself into extended memory and
then remaps that piece of extended memory to occupy the address
that was used by the original ROM
Some BIOSes will do this for video adapter ROMs as well. The net
result is that the users available extended memory drops by
64K-128K, and hardware code runs from RAM. The original ROM is
no longer used during that session.

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Memory Shadowing

Shadow RAM Example

In machine X, the BIOS resides in the segment from F000-FFFFh.
On bootup, the BIOS copies itself into a piece of extended memory,
and then remaps that memory to respond to addresses in the
F000-FFFFh range.
Therefore, any attempts by the system to call program code in those
addresses will be answered by the shadow code in RAM, rather
than by the original ROM
So, once the shadow RAM is created, that memory is usually
protected so that it behaves like the original ROM. That is, any
accidental attempts to overwrite the code in those areas will fail,
and the memory will be unchanged.

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