KISHOR HASYAGAR

2827 Orchard Avenue,LA,CA-90007, (213) 587 3047, Email:hasyagar@usc.edu,14kishorgh@gmail.com

Objective
To secure summer internship in field of VLSI and Computer Architecture.
Education
University of Southern California
MS in EE(Current GPA-3.78/4)
Pune Institute of Computer Technology
BE in E&TC (GPA-4/4)

Dec 2015(expected)

July 2012

Courses
Undergraduate: VLSI, Integrated Circuits and Applications, Solid State Devices and Circuits, Electromagnetics, Computer
Organization and Architecture, Integrated Circuits and Applications, Computer Networks.
Completed: MOS VLSI Circuit Design(EE 477), Computer Systems Organization(EE 457).
Current: Computer Systems Architecture, VLSI System Design, Network Processor Design and Programming.
Prospective: Advanced Topics in Microarchitecture, VLSI tools and Techniques.
Graduate Projects
RCA: Schematic and layout design of 4 bit ripple carry adder implemented in Cadence Virtuoso. Main objectives included
estimation of critical paths and the associated delays and measurement of static and dynamic power consumed by circuit.
Carry Select Adder: A 16 bit CSA was implemented in schematic and layout in Cadence Virtuoso as part of labs.
ALU: 32 bit ALU implemented in schematic in Xilinx ISE 10.1 and Modelsim SE Verilog supporting a variety of operations .Test
benches executed for a variety of input pattern vectors. The difference in synthesis obtained by two codes was studied.
Noise Margin Calculation: Noise margin was calculated for basic gates inverter, nand and nor in Cadence Virtuoso with
emphasis on shifting of switching threshold for different sizes of gates.
Mini-Intrusion Detection System: Implemented a network intrusion detection system using schematics, IP cores and Verilog in
Xilinx 10.1 ISE in which pattern matching was used.
5 stage pipeline: Implemented 5 stage pipeline in Verilog incorporating basic features like internally forwarding register file,
stalling and forwarding to handle dependencies. Time space diagram was also shown. The 5 stage pipeline was converted to a 4
stage pipeline which had to take care of data dependencies by stalling the entire pipeline.
Network Router: Designed the schematic and layout of 4 bus router using bitonic sorting network. The idea was to assign 4 bus
lines to different speed buses depending on priority of buses. Congestion control mechanism was also implemented.
Undergraduate Projects
Space Diversity Receiver: Used two antennas to receive the same signal, one the original(reference)signal and other delayed
signal,added them both to increase the resultant SNR to combat multipath fading. It was implemented for band of FM(88-108
MHz). Generalized cross correlation method to estimate delay was implemented on DSP320C6713. An increase of 6 db was found
in resultant signal level. The system was simulated on Advanced Design System(ADS) by Agilent.
Traffic Light Controller
Designed a traffic light controller using Finite State Machine on Spartan 2 kit in VHDL using Xilinx tool.
Additional Projects
Full duplex intercom, FM receiver, 8051 microcontroller based temperature sensor.
Technical Skills
EDA Tools: Cadence Virtuoso, Xilinx FPGA Suites, Multisim, Matlab, Cad Feko, Advanced Design System.
HDL: Verilog, VHDL.
Programming Languages: C,C++.
DBMS Technologies: PL/SQL.
Scripting: Unix shell,PERL.
Professional Experience
Software Engineer, HSBC GLT India
2012-2013
Primary responsibilities included Software development of finance accounting rules using PL/SQL and Unix Technologies and
cooperating with overseas development teams for the same.
Interacting with users to collect their specific requirements.