4.

Transistors
The transistor is the main and the most important building block of all
modern electronic systems. They are 3 terminal devices and are of 2 types,
1) Bipolar Junction Transistors (BJTs),
2) Field Effect Transistors (FETs).
For BJTs the output current, voltage and/or power is controlled by the input
current. Conduction is due to both e- and h+ so are called bipolar.
For FETs the output characteristics are controlled by input voltage.
Conduction is due to either e- or h+ so are called unipolar.
In communication systems transistors are widely used as the primary
component in the amplifier (circuit that is used to increase the strength or
amplify an ac signal) and as a switch. We will first consider BJTs and look
at FETs later.
BJTs
The BJT transistor consists of two PN junctions and is formed from a single
bar of Si that has been doped in the proper way. There are two ways to
arrange the two PN junctions as shown in the figure. The BJT has essentially
three regions known as Emitter (E), Base (B) and Collector (C). All three
regions are provided with terminals.
E

NPN
Type

PNP
Type

B
E

1) Emitter (E): supplies charge carriers (e- and h+) to the other two regions
and this is a heavily doped region.
2) Base (B): Middle region that forms the two PN junctions. The Base of the
transistor is thin as compared to the E and is a lightly doped region,
3) Collector (C): collects the charge carriers (e- and h+) and is always larger
than the E and B. Its doping is intermediate between the E and B.
The junction between the Emitter and Base is known as the Emitter-Base (EB) junction and that between the Collector and Base as the Collector-Base
(C-B) junction.

Page 1 of 36

Circuit Symbols
The circuit symbols for the two types of BJTs are shown in Figure 30. Note
that the arrow points from P to N and indicates direction of conventional
current flow. The PNP is a complement of NPN.
NPN- majority careers are free e-. PNP- majority careers are h+.
E

C
B

NPN

PNP

We will discuss in terms of NPN.

For PNP we reverse the directions of current and the polarity of supplies.
The Unbiased Transistor
A transistor with E, B and C terminals left open is called an unbiased
transistor or open-circuited transistor. Diffusion across the PN junctions
produces two depletion layers as shown in the figure.
E-B dep
layer

C-B dep
layer

E-B depletion layer

Penetrates slightly into the Emitter (heavily doped) but deeply into the Base
(lightly doped).
C-B depletion layer
Penetrates more into the Base (lightly doped) and less into the Collector
(intermediate doping between E and B).
The E-B depletion layer width is smaller than the C-B depletion layer.
An unbiased transistor is never used in practice. In practice all terminals are
connected to DC voltage sources for proper transistor action and therefore it
is necessary to bias both PN junctions.
Depending on how the two PN junctions are biased, there are three possible
transistor configurations,
1) Common-Base (C-B)
2) Common Emitter (C-E)
3) Common Collector (C-C)
Page 2 of 36

Common-Base (C-B) Configuration

Bias
Figure below shows the biasing arrangement and e- flow for the two PN
junctions in the transistor. The forward biased E-B junction will diffuse
majority carrier e- from the E to B, and the reverse biased C-B junction will
drift these majority carriers (minority carriers in P or B) from B to C.
Majority
Carrier
Diffusion
N

Minority
Carrier
Drift

e-

- +
VEE

e-

E-B Junction is forward biased by VEE

ve terminal of VEE connected to N or E
+ve terminal of VEE connected to P or B.
Substantial flow of diffusion current
across junction due to flow of majority
carriers (e-) from N type E.

- +
Vcc

C-B junction is reverse biased by VCC

+ve terminal of VCC connected to N or C
ve terminal of VCC connected to P or B
Depletion layer is widened and only
current flow from B to C is due to the
minority e- crossing the junction.

Rule for Biasing: E-B junction forward biased; C-B junction reverse biased
Figure below shows the combined bias according to the biasing rule and the
equivalent circuit diagram. Note the equation for the currents
N

eIE

IE

IC

IC

IB
VEE

IB

VEE

VCC

VCC
IE = IC + IB

C-B Parameters and Characteristics

Common-Base Transistor Gain and ICBO
If Emitter is open as in the figure below, no carriers are injected to B from E.
The only current that flows is due to thermally generated carriers. This
current is called the reverse saturation current and designated as ICBO, the
Collector to Base current with Emitter open. (ICBO can be considered the
same as the reverse diode current).
Page 3 of 36

ICBO
OPEN

Vcc

Total collector current Ic then consists of

1) current produced by normal transistor action called injected current
Ic(INJ), and
2) Reverse saturation current ICBO.
Therefore total collector current Ic = Ic(INJ) + ICBO
We define an important parameter here as,
= Ic(INJ) /IE
which measures the portion of Emitter current that pass through the Base to
become Collector current.
is always < 1. Greater the value of (the closer it is to 1), the better the
transistor. For typical transistors = 0.95 to 0.995
Ic(INJ) = IE and therefore Ic = IE + ICBO
Theoretical value of ICBO is usually very small compared to IE, so
Ic = IE or = Ic /IE and is called the Common-Base DC current gain.
Example: The emitter current in a NPN transistor is 8.4 mA. If 0.8% of the
minority carriers injected into the base recombine with holes and the leakage
current is 0.1 A, find (a) the base current, (b) the collector current, (c) the
exact value of , (d) the approximate value of , neglecting ICBO.
(a) IB = 0.8% IE = 67.2 A,
(b) IC = IE-IB = 8.3328 mA
(c) IC(INJ) = IC ICBO = 8.3327 mA so = IC(INJ)/IE=0.99198
(d) IC/IE=0.992
Transistor Characteristics
These are curves that describe transistor behaviour. There are two
characteristics for any configuration.
1) Input Characteristics: gives relationship between the input
current and input voltage for a given output voltage,
2) Output Characteristics: gives relationship between the output
current and voltage for a given input current.

Page 4 of 36

Common-Base (C-B) Characteristics

The Input output voltage and currents for the transistors are defined as
below.
IE

Ic
+
VCB

VBE

INPUT

OUTPUT

C-B Input Characteristics

25 10 0 VCB(V)

IE

(mA) 10
8
6
4
2

Knee
0.4

0.5

0.6

0.7

0.8

VBE(V)

1) There is a threshold voltage (knee or cut-in) below which Emitter

current is negligible (very small) [this voltage is about 0.5V for Si],
2) Beyond the knee for a fixed VCB, IE increase rapidly with VBE. This
means the input resistance is small,
3) As VCB increases the curves shift upwards, We can determine the value
of ac resistance by ri = VBE /IE. The ac input resistance depends on
the location of the operating point selected along the curve.
Example: The transistor shown in the figure has the input characteristics
above. When Vcc = 25 V it is found that IC = 8.94 mA. Find
(a) of the transistor neglecting ICBO (b) Repeat if IC = 1.987 mA when
VCC is short circuited.
IE

0.55V

IB

IC

VCC

(a) VBE=0.55V. In the input characteristics a vertical line at this VBE

intersects the VCB = 25V curve at about IE=9 mA. So IC/IE=0.9933
(b) When VCC is shorted, VCB = 0. From input characteristics IE = 2 mA at
VCB=0 and VBE=0.55V. So IC/IE=0.9935
Page 5 of 36

C-B Output Characteristics

Saturation
Region

Ic(mA)

Breakdown Region

Active Region
IE= 10 mA

10

8 mA

6 mA

6
4

4 mA

2 mA
0 mA
-2

4
6
8
Cut-off Region

40

VCB(V)

50

60

(1) Curves may be divided into three regions: saturation, active and cutoff regions.
(a) Saturation : VCB is negative for NPN transistor. Means that the
C-B junction is also forward biased.
(b) Active : Collector current is constant and nearly equal to Emitter
Current ( 1),
(c) Cut-off: Along the horizontal axis. Correspond to IE = 0. Both
junctions reverse biased..
(2) Collector current flows even when VCB is zero. This is due to ebeing injected into the base under the forward biased E-B junction.
These e- reach the Collector due to internal junction barrier potential.
(3) A small current flows for IE = 0. This is the ICBO.
Common - Emitter (C-E) Configuration
Bias
Figure (a) below shows the circuit diagram for bias according to the biasing
rule. (b) shows the conventional way of drawing this circuit with input and
output.
Ic

NPN

+Vcc
Ic
IB

IB

OUTPUT

VCE

Vcc
INPUT
VBE
VBB
(a)

(b)
Page 6 of 36

C-E Transistor Gain and ICEO

Figure below shows the B-E circuit left open while VCC remains connected.
The only current that can flow is the reverse current across C-B junction.
Current flows from C through B to E. This current is designated ICEO, the
Collector to Emitter current with Base is open. ICEO is in the same direction
as Ic.
ICEO
Vcc

OPEN

From previous equations, Ic = IE + ICBO

Rearrange, Ic / ICBO/ = IE = Ic + IB
Ic(1 / 1) = IB + ICBO/
Ic = IB/(1-) + ICBO/(1-)
When IB = 0, ICEO = [1/(1-)] ICBO
As is close to 1, (1-) is close to zero and 1/(1-) can be quite large. So the
C-E leakage current >> C-B leakage current.
We define an important parameter here as
= /(1-)
the Common-Emitter DC current gain. is always > 1, and ranges from 20
to several hundred.
Ic = IB + ICBO/(1-) = IB + ICEO
Although ICEO >> ICBO, it is still very small compared to IB. Therefore,
Ic = IB and = Ic / IB the C-E DC current gain.
Example: A transistor has ICBO=48nA and =0.992. Find (a) and ICEO,
(b) its exact collector current when IB=30A, (c) the approximate collector
current, neglecting leakage current
(a) = /(1-) = 1.24; ICEO = ICBO/(1-)=6A
(b) IC= IB+ICEO = 3.726 mA, (c) IC IB = 3.72mA
C-E Input Characteristics
VCE = 5V 20V

IB 10
(A)8
6
4
2
0.4

0.5

0.6

0.7

Note: IB in A
Page 7 of 36

0.8

VBE(V)

There is a threshold voltage (0.5 for Si) below which Base current is very
small. ac input resistance can be found from ri = VBE/IB. ri varies with
location of operating point and typically in the range 600-4k
C-E Output Characteristics
Ic
(mA) Saturation
10

Active Region

IB=
50 A

40 A

30 A

20 A

0
0

10

15

20

25

VCE(V)

Cut-off

Note: Ic in mA.
(1) Can be divided into 3 parts: saturation, active and cut-off regions
(2) Can be used to find ac output resistance ro = VCE/IB. Typical values
from 10k-50k
(3) Can find .
Example: from points R and S in the Graph
= (6 - 3)mA/ (40 - 20)A = 150
Common - Collector (C-C) Configuration
Bias
From before Ic = IB
but IE = Ic + IB
= IB + IB
= ( + 1) IB

IE

+Vcc
IE
IB

Vcc

IB VBE
VCE
VCB

VCB

Page 8 of 36

VCE
+

INPUT

VBB

OUTPUT

C-C Input Characteristics

IB 100
(A)
80

10

15

=VCE

60
40
20
5

10

15

VCB (V)

C-C Output Characteristics

Saturation

10

IB=
50 A

40 A

IE 6
(mA)4

30 A
20 A

0
0

10

20

15

25

VCE(V)

cut-off

Bias Circuits
The bias circuits given above consider bias in terms of adjusting the DC
supply voltages. In practice we do this by having resistors in series with the
DC supplies and consider adjusting the resistor values to adjust the value of
bias. We do this to obtain specific values of input and output current and
voltages. When we have achieved this we have set the bias point.
C-B Bias Circuit
RE

IE

Rc

VBE

VCB

IC
VEE

VCC

Input voltage is no longer VEE because there is a voltage drop across RE.
Similarly, for the output. The characteristics are still valid. Apply Kirchoffs
Law to the output loop
Vcc = IcRc +VCB. Rearrange as: Ic = -(1/Rc)VCB + Vcc/Rc.
Consider Ic and VCB as variables and Vcc and Rc as constants This is an
equation of a straight line with slope -1/Rc and intercepts at VCB =Vcc and
Ic =Vcc/Rc. This is the load line for the transistor and can be plotted in the CB output characteristics to find the point of intersection Q or the Bias point.
To determine the point of intersection we need to know the current I E. The
Page 9 of 36

most practical way is to regard the B-E junction as a forward biased diode
having a voltage drop of 0.7V (for Si) and solve for diode current.
RE

- 0.7V
+
B

VEE

This gives IE = (VEE - 0.7) / RE

Transistor output characteristics are not usually used to design or analyze
transistor circuits because transistors of the same type can have a wide
variation in their characteristics. The entire bias circuit is analyzed by the set
of equations below, which can solve for all the input and output current and
voltages. We can also get expressions for RE and Rc from the equations to
chose RE and Rc values for desired input and output currents and voltages
NPN C-B Bias Circuit Equations
VBE = 0.7 (Si), 0.3 (Ge)
IE = (VEE -VBE) / RE
Ic = IE IB IE
VCB = Vcc - IcRc
These equations give the resistance values
RE = (VEE - VBE) / IE and Rc = (Vcc VCB) / IE
Example: Determine the bias point of the circuit below without using
characteristic curves
2.65K

IE

4K

VBE

IE = (VEE-0.7)/RE = 2 mA
Ic IE and VCB= Vcc-IcRc=12V
Thus the bias point is
IC=2mA and VCB=12V

VCB

IC
20V

6V

C-E Bias Circuit

+Vcc
RB

Ic

Rc
IB
+

RB
0.7V

Vcc
VCE

VBE

Page 10 of 36

It has only a single supply voltage Vcc. RB and Rc must be chosen so that the
voltage drop across RB > voltage drop across Rc to keep C-B junction in
reverse bias.
Using Kirchoffs law
Vcc = IcRc + VCE Rearrange to get Ic = (-1/Rc)VCE + Vcc / Rc
We can again draw the load line on the output characteristics to find Q the
bias point. We need to know IB to determine Q. IB is given by the diode
circuit as IB = (Vcc - VBE) / RB.
NPN C-E Bias Circuit Equations
VBE = 0.7 (Si), 0.3 (Ge)
IB = (Vcc -VBE) / RB
Ic = IB
VCE = Vcc Ic Rc
These equations give the resistance values
RB = (Vcc-VBE) / (Ic / ) and
Rc= (Vcc VCE) / Ic
Example:
The Si transistor in the C-E bias circuit below has a of 100. Find the bias
point.
+12V
376.67K

Ic

2K

VBE=0.7V, IB=(Vcc-VBE)/RB=30A
Ic= IB=3mA; VCE= Vcc-IcRc=6V
Bias Point Ic=3mA, VCE=6V

IB
+

VCE

VBE

C-C Bias Circuit

+Vcc

RB

VCB

+ +
VCE

RB

Vcc
IB

B + VBE

IB

IE

RE IE

RE

Applying Kirchoffs law

Vcc = IE RE + VCE Rearrange IE = - (1/RE) VCE+Vcc / RE
Page 11 of 36

To find IB to determine Q point using the diode circuit,

Vcc= IB RB + VBE + IE RE; But IE = (+1)IB
Substitute and rearrange to get IB = (Vcc - VBE) / [RB + (+1)RE]
NPN C-C Bias Circuit Equations
VBE = 0.7 (Si), 0.3 (Ge)
IB = (Vcc -VBE) / [RB + (+1)RE]
IE = (+1) IB
VCE = Vcc IE RE
These equations give the resistance values
RE = (Vcc - VCE) / IE and RB = (+1)(Vcc VBE IE RE) / IE
Bias Design Example: A C-B bias circuit is to be designed for a NPN Si
transistor to be used in a system having DC power supplies +15V and -5V.
The bias point is to be IE=1.5mA and VCB=7.5 V
(a) Design the circuit using standard valued resistors with 5% tolerance.
(b) What are the actual bias values if the resistors selected have their
nominal values?
(c) What are the possible ranges of IE and VCB taking the resistor
tolerances into account?
(a) From the C-B resistance values, RE = (VEE - VBE) / IE = 2867 and
Rc = (Vcc VCB) / IE = 5000. The standard 5% resistors closest to these
resistor values are RE = 3 k and Rc=5.1k
(b) Recalculate with these new resistor values; IE=1.43mA and VCB=7.69V
(c) The range of possible resistance values with 5% tolerance are
RE=3k0.05(3k)=2850 to 3150
Rc = 5.1k0.05(5k)=4845 to 5355
Then IE(min)=1.365mA, IE(max)= 1.509 mA, VCB(min) = 6.92V, VCB(max)= 8.39V
BJT Transistor as Amplifier
We consider small-signal operation, meaning that the output variations are
small and that there is negligible change in the value of device parameters (
, etc.). The transistor amplifier is studied from the standpoint of transistor
behaviour as an ac amplifier as illustrated below. What we mean by an ac
amplifier is that the transistor amplifier will give a magnified (or amplified
version) of the input ac signal amplitude. Generally the ac input can oscillate
about a DC level.

Page 12 of 36

Vin DC

DC

Vo

Amplifier
Symbol

Amplifier Parameters
Voltage gain Av = Vo / Vin . For a Voltage amplifier: Av > 1.
Only the ac components of the input and output are used to compute voltage
gain. DC values have no bearing on the value of gain.
Current gain Ai = Io / Iin. Device with Ai > 1 is a current amplifier.
It is possible to have Av > 1 and Ai < 1.
Power Gain Ap = Po / Pin = AvAi
Input and Output Resistance
The input resistance to an amplifier is the total equivalent resistance at its
input terminals. The DC input resistance Rin is the resistance that a DC
source sees when connected to the input terminals, and the ac input
resistance rin is the resistance that an ac input source sees at the input
terminals. The input resistance can be calculated as the ratio of input voltage
to input current: Rin = Vin/Iin (for DC), rin = vin/iin (for ac)
The ac input power Pin = [vin(rms)] / [iin(rms)]= vin(rms)2/rin = [iin(rms)]2rin
The output resistance of an amplifier is the total equivalent resistance at its
output terminals and is the same as the Thevenin equivalent resistance that
would appear in series with the output if the amplifier is replaced by its
Thevenin equivalent circuit. Output resistance is defined as Ro for DC and ro
for ac.
Example: Figure below shows a circuit with the normal amplifier symbol.
The input voltage to the amplifier is vin(t) = 0.7+0.008 sin 103t V. The
amplifier ac current gain is 80. If the input current is i in(t)=2.8x10-5+4x10-6
sin 103t A and the ac component of the output voltage is 0.4V rms,
find (a) Av, (b) Rin, (c) rin, (d)io(rms), (e) ro and (f) Ap
iin(t)

io(t)
vo=0.4V rms

+
vin(t) ~
-

RL

Page 13 of 36

(a) vin(rms)=0.707(0.008 v-pk)= 5.66x10-3V rms

Av= vo(rms)/vin(rms) = 70.7
(b) Rin=Vin/Iin=0.7/2.8x10-5=25k
(c) rin=vin/iin=0.008 V-pk/4x10-6 A-pk=2k
(d) io(rms)=Aiiin(rms) = 80 (0.707)(4x10-6 A-pk) = 0.226 mA rms
(e) ro = vo(rms)/io(rms) = 0.4/0.226x10-3 = 1770
(f) Pin=vin2(rms)/rin = 1.6x10-8W, Po=vo2(rms)/ro=9.04x10-5W
Ap=Po/Pin = 5650
Source Resistance
Every signal source has internal resistance called source resistance
designated as rs. If rin is the amplifier input resistance, rs and rin are in series
and form a voltage divider across the input of the amplifier as shown below.
+ rs
vs ~
-

vin

rin

Input voltage vin = [rin /(rs+rin)] vs.

Output voltage vo = Av vin.
Therefore
vo / vs = Av [rin / (rs + rin)]
Thus the overall amplifier voltage gain is reduced by a factor [rin /(rs + rin)]
as the value of this factor is always less than 1.
If rin >> rs then [rin / (rs + rin)] 1 and there is little reduction in amplifier
gain. Therefore for a voltage amplifier it is desirable to have a large input
resistance.
The overall amplifier current gain is io / is = Ai [rs / (rs + rin)].
Therefore the current amplifier should have a small input resistance.
Example: The amplifier shown has Av=10 and Ai=10. It is driven by a
source that has source resistance 1k, Find the overall voltage and current
gains, when (a) rin=10k and (b) rin=100. Assume output is open to
calculate voltage gain and output is grounded to calculate current gain
+
vs ~
-

1K

vin

rin

(a) rin=10K, vo / vs = Av [rin / (rs + rin)]= 9.09; io / is = Ai [rs / (rs + rin)]=0.909

(b) rin=100,vo / vs = Av [rin / (rs + rin)]= 0.909; io / is =Ai [rs / (rs + rin)]=9.09
Page 14 of 36

Load Resistance
ro
~ vo

RL

vL

If ro is the output resistance of the amplifier and RL the load resistance

vL = [RL / (ro + RL)] vo
Therefore for a voltage amplifier ro << RL so that vL = vo.
For a current amplifier iL = [ro / (ro + RL)] io so ro >> RL
Amplifier with Source and Load

ro
~
rin vo

+ rs
vs ~
-

vin

RL

vL

When both source rs and load RL are taken into account

Overall voltage gain
vL / vs = Av[rin /(rs + rin)][RL/ (ro + RL)]
Overall current gain
iL / is = Ai [rs /(rs + rin)] [ro/ (ro + RL)]
If rs is fixed, maximum power transferred from source to amplifier is when
rin = rs, when the amplifier is matched to the source. If ro is fixed, maximum
power transferred to load when RL = ro when the amplifier is matched to the
load.
Purpose of Bias in an Amplifier
In most single transistor amplifiers, the output voltage must always be +ve
(or ve). When this is the case, it is not possible for the output to be a pure ac
waveform, since the ac waveform fluctuates between +ve and ve values.
The purpose of bias in a transistor amplifier is to set a DC output level
somewhere in the middle of the total range of possible output voltages so
that an ac waveform can be superimposed on it as shown in the figure.
max o/p voltage
VB+A

Vout

VB

VB-A
min o/p voltage

vin = A0 sin t
Page 15 of 36

The ac input causes the output voltage to vary above and below the bias
voltage, but the instantaneous values of the output are always positive, in this
example.
Output voltage vo = VB + A sin(t)
where VB is bias voltage or DC component of the output and A = Av A0
where Av is voltage gain. A is the peak value of the sinusoidal ac output.
Values of VB and A must be such that VB+A is not greater than maximum
output voltage Vmax and VB-A is not less than minimum output voltage Vmin.
If this condition is not satisfied output voltage will reach its minimum or
maximum extremes before the total ac variation take place. The result is a
flattening of the output signal which is called clipping as shown in the
figure below. Purpose of an ac amplifier is to have as output an amplified
version of the input. Clipping distorts the output signal and is an example of
amplitude distortion.
VB

Vmax
Vmin

Vmax
VB

Vmax

Vmin
Vmin

+ve clipping
VB too large

-ve clipping
VB too small

+ve & -ve clipping

Amplitude A of signal
too large (overdriven)

In many amplifier applications the source or the load cannot be subjected to

a DC voltage or conduct DC current. To prevent the DC component of an
amplifiers output voltage from producing DC current in the load, a capacitor
can be connected in series with the load and similarly to prevent flow of DC
current from the amplifier to the source a capacitor can be connected in
series with the source as illustrated in the figure below. These are called
coupling or blocking capacitors and must be large enough to present
negligible impedance to the ac signal.

+
vs ~
-

rs
RL

vL

Amplifier analysis
Small signal parameters are parameters whose values are determined under
small signal ac operating conditions. We will use simple letters to signify ac.
Examples are = ic/ib | VCE=constant; = ic/ie| VCB=const.
Page 16 of 36

An important physical parameter is the small signal resistance from Emitter

to Base called the emitter resistance re for VCE constant given by
re = vbe / ie | VCE= const.
Since E-B junction can be seen as a forward biased diode, an approximate
value for re can be found as re = 0.026/IE (which is the same as the
dynamic resistance of a diode), where IE is the DC emitter current.
Small signal collector resistance rc is the ac resistance from collector to base
for IE constant. Because it is across a reverse bias junction rc = vcb/ic |IE=const.
and is of the order of several M.
Equivalent Circuits
We will consider the simplified models that do not take into account reverse
currents. There is a more accurate model called the Hybrid model.
C-B Transistor Equivalent Circuit
All voltages and currents are ac quantities, therefore all polarities
periodically alternate.
C-B Transistor Model
(a) Circuit representation and voltages and currents
(b) Small-signal ac equivalent circuit
ic
ic
E ie
E ie
C
C

vbe

vcb

vbe

re

B
(b)

(a)

ie

rc

vcb

Figure shows that an increase in current into E is accompanied by an

increase of current out of C.
C-B Amplifier Model
We first draw the complete circuit for the C-B amplifier with the DC bias
and ac source.
Rc
+
vs ~
-

RE
VEE

vo
Vcc

We then draw the ac equivalent: of that is external to the transistor. All DC

sources are treated as ac short circuits to ground.

Page 17 of 36

+
vs ~
-

RE

vo

Rc

Replace transistor with the small signal equivalent circuit

iin

ie

+ RE re
vs ~
-

ic

io

rc

Rc

vo

ie

In a practical C-B circuit, RE >> re, so re//RE re ;

rc >>Rc, so Rc//rc Rc
ie
+ vin re
vs ~
-

ic
ie

Rc

vo

vs = vin = ie re and vo = ic Rc = ie Rc but 1 so vo = ie Rc

Voltage Gain Av = vo / vin = Rc / re
Current Gain Ai = io /iin = ic / ie =
Example: For the circuit below with =1 , find (a) rin, (b) Av, (c) vL, (d) iL,
(e) iL/is
iL

Si
50
10mV+
~
rms -

2k

1k

-6V

4k

vL

+6V

(a) From C-B Bias equations IE=(VEE-VBE)/RE=(6-0.7)/2x105=2.65mA

From equation for diode dynamic resistance rin=re=0.026/IE=9.81
(b) Av=Rc/re=1000/9.81=101.9
(c) vL/vs=Av[re/(rs+re)][RL/(RL+Rc)]=13.37. Therefore vL=133.7mV rms
(d) iL=vL/RL=33.4A rms
(e) iL/is= [rs/(rs+re)][Rc/(RL+Rc)] = 0.167

Page 18 of 36

C E Transistor Equivalent Circuit

B

ib

vbe

re

ic

ib
re

C
rc/

ib

vbe

vcb

ie

Input resistance re is drawn inside the emitter terminal to emphasize that it is

an internal transistor parameter.
ac input resistance rin = vbe /ib
But ie = (+1) ib which can be derived from the DC relation.
[IE = IC+IB = IB + IB = (+1) IB ]
Then
rin = [(+1) vbe] / ie
But vbe / ie = re Therefore rin = (+1) re re as >>1
Equation shows that for the C-E configuration, input resistance is times
greater than C-B configuration. Similarly, output resistance is times
smaller than C-B configuration. Therefore the C-E amplifier is inherently
better suited for voltage amplification than the C-B counterpart.
C-E Amplifier Model
+Vcc

RB
+
vs ~

ic

ib

Rc

re

vo

+
RB
~
vs
- vin

rc/
Rc

ib

rc / is in parallel with Rc.

In most practical circuits rc / >> Rc so that (rc /) // Rc Rc
Therefore output resistance ro = Rc
Output voltage vo = ic ro = ib Rc
From equivalent circuit vin = re ib
Therefore voltage gain Av = vo/vin = - Rc/re
Negative sign is inserted to show that the ac output is 180 out of phase
with ac input.
Current gain Ai = ic / ib =
Page 19 of 36

vo

C-E Amplifier with source and load

+Vcc
ic

ib
RB

rs

Rc

rs
+
vs ~

+
vs ~
-

RB

re
ib

Rc RL vL

RL

vL / vs = [(RB // re) / (rs+RB / / re)] Av [RL/(RL+Rc)] where Av= - Rc / re

iL / is = [(rs // RB) / (rs // RB+ re)] Ai [Rc/(RL+Rc)]
Example: Find the output voltage of the amplifier shown assuming rs = 0.
+15V

1k
200k
Si
=100

rs

20mV rms

10k

vL

To find re we first find the quiescent emitter current:

IB = (Vcc-0.7)/RB = 71.5A. So IE Ic= IB =7.15mA.
Therefore re = 0.026/IE = 3.64
Av= -Rc/re = -274.7. As rs = 0, vL/vs=Av[RL/(RL+Rc)] = -249.7
Therefore vL=4.99V rms
Effect of ac load resistance
Using load resistance terms only
vL/vs = - (Rc / re)[RL/(RL+Rc)] = - (1/re)[(RLRc/(RL+Rc)]
= - (1/re) (RL // Rc) = -rL / re where rL is ac load resistance.
Therefore vL/vs is proportional to rL= RL// Rc
Since RL // Rc < Rc, the effect of connecting a load RL to the amplifier is to
reduce the voltage gain.

Page 20 of 36

C- C Amplifier Model
+Vcc
ib=iin B
rin

RB
rs

vs ~

rs
+

ib=iin
rin
vin

vs ~
-

RE

vo

RB
vin

re
ib

ie E
RE

vo

Collector is shown grounded in the ac equivalent as DC sources are treated

as ac short circuits.
Resistance between Base and Emitter is shown as re (+1)re
Input resistance at the Base of the transistor (between Base and Ground) is
rin = vin / iin = vin / ib
vin = ib (+1) re + ieRE (we have replaced with +1).
= ib (+1) re + (+1) ib RE = ib (+1) (re+RE)
Therefore rin = [Ib((+1)(re+RE)] / ib = (+1)(re+RE)
Let (+1) , then rin (re+RE)
In many practical ciruits RE >> re, and therefore rin RE
Voltage Gain Av = vo/ vin = ie RE / vin
Substituting for vin and simplifying Av = RE / (re+RE)
Since re + RE > RE, equation shows that the C- C Amplifier always has a
voltage gain < 1
Also as RE >> re then Av 1 or vo = vin
Thus, the ac output voltage ac input voltage in the C-C configuration.
There is no phase change between the input and output and they are
separated only by the small resistance of the forward biased B-E junction.
Since output voltage is the same as the input voltage in amplitude and phase,
the Emitter is said to follow the Base and is known as the Emitter
Follower rather than the Common-Collector.
Current Gain Ai = ie / ib = (+1) .
So the Current Gain can be >> 1 and so is the Power Gain Ap = AvAi Ai.

Page 21 of 36

Example: Find (a) rin and (b) Av for the C-C amplifier in the figure.
+15V

75k

rs

vs ~

rin

Si
=100
910

vo

(a) IB=(Vcc-VBE)/[RB+(+1)RE]=85.7A. Therefore IE=(+1)IB=8.57mA

re=0.026/IE=3.03. Therefore rin= (+1)(re+RE)=92.2k
(b) Av = RE/(re+RE) = 0.997 1
Transconductance
This is another derived parameter widely used in the analysis of electronic
devices, designated as gm and defined as
gm = io / vinvo=constant.
Units are of conductance (Siemens). This parameter is called
transconductance because it relates input and output quantities (across the
device). For BJTs transconductance is defined in terms of the C- E
configuration (input voltage vbe and output current ic). Therefore for C-E,
gm = ic/ vbe VCE=constant
For vbe < 10mv, gm can be approximated by gm = Ic/0.026 (at room
temperature) where Ic is the DC Collector current.
Transconductance Model for C-E transistor
ib
ic
B
gm vbe
re=
vbe /gm
E

Page 22 of 36

ro

Field Effect Transistors (FETs)

Like the BJT, FET is a three terminal semiconductor device but operates
under different principles. The current through a FET is due to either
electrons or holes and therefore called a unipolar device. The device is
called field effect because the current flow is controlled by an electric field
set up in the device by an externally applied voltage.
There are 2 main types of FETs
(a) the Junction Field Effect Transistor (JFET) and
(b) the Metal-Oxide-Semiconductor FET (MOSFET)

JFET
N-channel JFET

Drain (D)

Gate
(G)

N
P

channel
Source (S)

The basic construction of a N-channel JFET is shown in the Figure. It

consists of a N- type semiconductor bar with two P- type heavily doped
regions diffused on opposite sides of its middle part. The two P sides are
joined electrically and the common connection between them is called the
Gate (G). Electrical connections (called ohmic contacts) are made to both
ends of the N- type semiconductors and are taken out in the form of two
terminals called Drain (D) and Source (S).The region of N material between
the two opposing P regions is called the channel.
For a N- channel JFET, D is the terminal through which electrons leave the
semiconductor bar and S is the terminal through which electrons enter the
semiconductor. Thus conventional current flow is from D to S. The voltage
applied to G controls the flow of current between D and S.
(For a P channel JFET where current flow is due to holes, N-type heavily
doped regions are diffused into a P-type semiconductor bar).
Compared with the BJT, the Drain corresponds to the Collector, the Source
to the Emitter and the Gate to the Base. The voltage applied to the Gate
controls the flow of current between drain and source, just as the signal
applied to the base controls the flow of current between Collector and
Emitter in a BJT.
Page 23 of 36

Circuit Symbols for JFET

N-channel
G
JFET

P-channel
JFET

D
G

D
G

The symbols showing the G terminal off-center are used as a means of

identifying S. S is the terminal closest to the G arrow. Some JFETs are
manufactured with D and S interchangeable and the symbols for these
devices will have the G arrow in the center.
Formation of depletion regions
When an external voltage is applied between D and S so that D is +ve with
respect to S, electrons will flow form S to D. Thus conventional current flow
is from D to S and is limited by the resistance of the N-channel. In normal
operation, an external voltage is also applied between G and S. The P-type G
and N-type channel constitute a PN junction.
D
N
G

P
ID
S

VGS

VDS

We first consider the case for when VDS = 0.VGS is applied so that the PN
junctions of the channel are reverse biased. Thus G is made ve with
respect to S. The reverse bias causes a pair of depletion regions to form in
the channel as shown in the figure above. Since the channel is more lightly
doped than G, the depletion regions penetrate more into the N-type channel
than into the P-type G. The width of the depletion region depends on the
magnitude of the reverse bias voltage VGS. The illustration in the figure is for
the case when VGS is small (only a few tenths of a volt) so the depletion
regions are relatively narrow. As VGS is made more -ve, the depletion
regions expand and the width of the channel decreases. The reduction in
Page 24 of 36

channel width increases the resistance of the channel and decreases the flow
of current ID.
The reverse bias across the G-S junction can also be achieved by applying a
voltage VDS across the D and S terminals. As VDS is increased (for VGS =0)
the current ID increase in direct proportion to it, see center figure below.
pinch-off
D

ID
G

VGS=0

IDSS

ID

P
IDSS

VP
VGS=0

VDS

VDS

VGS=0

VDS

As VDS is increased further, noticeable depletion regions begin to form in the

channel. The depletion region is broader near the D end of the channel than
they are near the S end. This is because the current flowing through the
channel creates a voltage drop along the length of the channel. When V DS is
increased further, the depletion region expands and the channel becomes
very narrow near D, causing the total resistance of the channel to increase.
As a consequence the current is no longer directly proportional to V DS and
instead the current begins to level off. The figure on the right shows what
happens when VDS is increased to a value large enough to cause the
depletion regions to meet at a point near the channel D end. This condition is
called pinch-off. The point where pinch-off occurs the value of VDS (the ve
of) is called pinch-off voltage VP. VP is an important JFET parameter, whose
value depends on the doping and the geometry of the device. VP is always
ve for an N channel JFET (and +ve for P channel JFET). The center figure
above shows that the current reaches a maximum value at pinch-off and that
it remains at that value as VDS is increased beyond VP. This current is called
the saturation current and designated IDSS, the Drain to Source current with
the Gate shorted.
Example:
Lets set typical values of Vp = -4V and IDSS = 12 mA for when VGS = 0. Now
lets connect the JFET with these values in the circuit as before and make
VGS = -1V to reverse bias the G-S junction as shown in the figure below.
The reverse bias causes the depletion region to penetrate the channel further
Page 25 of 36

along the entire length of the channel than they did when VGS = 0. If we now
increase VDS above 0, the current again increases linearly as shown in the
figure on the right, but not as steep as before because the resistance of the
narrow channel is greater than before. If we continue to increase VDS the
depletion regions again approach each other near D. The further narrowing
of the channel increases its resistance and the current will again level off.
Since there is also a 1V reverse bias between G and the channel, the pinch
off condition is now reached at VDS = 3V instead of 4V (as VDS = VGS Vp),
as shown in the figure. The current saturates at the lower value of 6.75 mA
as VDS is increased beyond 3V.
D

ID (mA)
G

VGS=0

12

P
ID

6.75

S
34

VDS (V)

VDS

VGS=-1V

We can get other characteristic curvess by setting different values for VGS as
shown in the figure below.
ID
(mA)

Voltage controlled
resistance region

Parabola joining points

where pich-off occurs
VGS=0V

Transfer
Characteristic
For VDS=8V

Pinch-off region
VGS=-1V
VGS=-2V
VGS=-3V

4
2
-4

-2

VGS(V)

VDS(V)

10

VGS=-4V

The set of curves VDS vs. IDS are known as the Drain characteristics. The
dashed line which is parabolic joins the points on each curve where pinchoff occurs. A value of VDS on the parabola is called a saturation voltage
Page 26 of 36

VDS(sat). At any value of VGS, the corresponding value VDS(sat) is the

difference between VGS and Vp,
VDS(sat) = VGS-Vp.
The equation of the parabola is ID = IDSS [VDS(sat) / Vp]2.
The region to the right of the parabola is the pinch-off region (also known as
the active or saturation region). This is the region in which the JFET is
normally operated when used for small-signal amplification. The region to
the left of the parabola is called the voltage-controlled resistance region or
the ohmic region. In this region the resistance is controlled by V GS. The
device acts like a voltage-controlled resistor in this region, and there are
some practical applications that exploit this.
The figure above also shows that ID = 0 when VGS = -4V regardless of the
value of VDS. When VGS reverse biases the G to S junction by Vp, depletion
regions meet along the entire length of the channel and D is cut-off. As the
value of VGS at D cut-off is the same as Vp, pinch-off voltage is also called
the Gate to Source cut-off voltage. So there is two ways to determine Vp
from the drain characteristics. It is the value of VDS where ID saturates when
VGS = 0, and it is also the value of VGS that causes all drain current to cease,
Vp = VGS(cut-off) .
Transfer Characteristics
The transfer characteristic of a device is a plot of output current versus input
voltage, for a fixed value of output voltage. When the input to a JFET is the
Gate-to-Source voltage and the output current is Drain current, the transfer
characteristic can be derived from the Drain characteristics. It is only
necessary to construct a vertical line on the drain characteristics (a line of
constant VDS) and to note the value of ID at each intersection of the line with
a line of constant VGS. The values of ID can then be plotted against the
values of VGS to construct the transfer characteristic as shown in the above
figure for VDS = 8V. The choice of this value of VDS means that all points
are in the pinch-off region. The equation for the transfer characteristic in the
pinch-off region is, to a close approximation,
ID = IDSS (1 - VGS/Vp)2
Example: An N-channel JFET has a pinch-off voltage -4.5V and IDSS=9mA
(a) At what value of VGS in the pinch-off region will ID = 3mA?,
(b) What is the value of VDS(sat) when ID=3mA?
(a) ID = IDSS (1 - VGS/Vp)2. Therefore VGS=Vp[1-(ID/IDSS)] = -1.9V
(b) ID = IDSS [VDS(sat) / Vp]2. Therefore VDS(sat)=(Vp2ID/IDSS ) = 2.6V
Page 27 of 36

MOSFETs
The metal-oxide-semiconductor FET (MOSFET) is similar to the JFET, in
that they both have Drain, Gate and Source terminals, and both are devices
whose channel conductivity is controlled by a Gate-to-Source voltage. The
main difference between a MOSFET and a JFET is that the Gate terminal in
a MOSFET is insulated from its channel region. For this reason, a MOSFET
is also called an Insulated-Gate FET or IGFET. MOSFETs come in two
types, the depletion type and the enhancement type. These names are
derived from the two different ways that the conductivity of the channel can
be altered by variations in VGS.
Depletion-Type MOSFET
Drain (D)

SiO2

VDS

N+
Gate
(G)

N+

G
N

SS
VGS

metal
N+
Source (S)

(a)

N+

substrate

(b)

depletion
region

Figure (a) shows the structure of an N-channel, depletion type MOSFET. A

block of high resistance, P type silicon forms a substrate, in which are
embedded two heavily doped N type wells labeled N+. A thin layer of
Silicon Dioxide (SiO2), which is an insulating material, is deposited along
the surface. Metal contacts penetrate the SiO2 layer at the two N+ wells and
become the drain and source terminals. Between the two N+ wells is a more
lightly doped region of N material that forms the channel. Metal (Al) is
deposited on the SiO2 opposite the channel and becomes the gate terminal.
Note that the gate is insulated from the channel and that there is no PN
junction formed between gate and channel.
Figure (b) shows the normal mode of operation of a depletion-type Nchannel MOSFET. A voltage VDS is connected between Drain and Source to
make the Drain +ve with respect to the Source. The substrate is usually
connected to the Source as shown in the figure. When the Gate is made -ve
with respect to the Source by VGS, the electric field it produces in the
channel drives electrons away from a portion of the channel near the SiO 2
layer. This portion is thus depleted of carriers and the channel width is
Page 28 of 36

narrowed. The narrower the channel the greater its resistance, and smaller
the current flow from Drain to Source.
Thus, the device behaves very like a N-channel JFET, the main difference
being that the channel width is controlled by the action of the electric field
rather than by the size of the depletion region of a PN junction. Since there
is no PN junction VGS can be made +ve without any concern for the
consequence of forward biasing a junction. Making VGS +ve attracts more
electrons into the channel and increases or enhances its conductivity. Thus
the Gate voltage can be made both +ve and ve and the device can operate
both in a depletion and an enhancement mode. Although there is a PN
junction between the N material and the P substrate this junction is always
reverse biased and very little substrate current flows. Thus the substrate has
little bearing on the operation of the device. The resistance looking into the
gate is very large, and of the order of thousands of megaohms.
Enhancement Type MOSFETs
Drain (D)

SiO2
VDS

N+
Gate
(G)
metal

SS

N+

VGS
N+

Source (S)

(a)

N+

substrate

(b)

Induced N-channel

In the enhancement MOSFET there is no N-type material between the Drain

and the Source (as found in the depletion MOSFET). Instead the P-type
substrate extends all the way to the SiO2 layer as shown in Figure (a). Figure
(b) shows the normal electrical connections between D, G and S. As in the
depletion MOSFET the substrate is usually connected to the Source. Note
that VGS is connected so that the gate is +ve with respect to the Source. The
+ve gate voltage attracts electrons from the substrate to the region along the
insulating layer opposite the Gate. If the Gate is made sufficiently +ve
enough electrons will be drawn into that region to convert it into N type
material. Thus an N type channel will be formed between Drain and Source
and the P material is said to have been inverted to form an N type channel. If
the gate is made still more +ve, more electrons will be drawn into the region
and the channel will widen making it more conductive. Thus making VGS
more +ve, enhances the conductivity of the channel and increase the flow of
Page 29 of 36

current from Drain to Source. Since electrons are induced into the channel to
convert it into N type material the device is also known as an induced Nchannel enhancement type MOSFET.
Circuit Symbols
D

Depletion
Type
MOSFET

SS
D
S

P-channel

N-channel

Enhancement
Type

SS
D

SS

SS
S

N-channel

P-channel

Advantages of N-channel MOSFETs over P-channel

N-channel MOSFETs have become much more popular than P-channel. The
main advantage of an N-channel MOSFET, over a P-channel, is due to the
charge carriers in N-channel devices being electrons which have a mobility
of about 1300 cm2/V.S compared to the charge carriers in P-channel devices
being holes which have a mobility of about 500 cm2/V.S. Since the current
in a semiconductor is directly proportional to the mobility, the current in a
N-channel MOSFET is more than twice that of a P-channel with the same
dimensions.
The ON resistance of the N-channel MOSFET is 1/3 of that for P-channel.
This means that in order to achieve the same value of current and ON
resistance, the P-channel MOSFET requires 3 times the area of an equivalent
N-channel MOSFET. Thus electronic circuits using N-channel MOSFETs
are much smaller than circuits containing P-channel MOSFETs.

Page 30 of 36

BJT Transistor as a switch (BJT Inverter)

Transistors are widely used in digital circuits and switching applications. We
will consider the NPN inverter shown in the figure below.
+Vcc

Ic
(mA) 10 Saturation

Rc

IB=

50 A

40
A
30 A
20 A

RB

Vout =
VCE

VIN

4
2

0
0

10

20

15

25

Cut-off

VCE(V)

Transistor is in C-E configuration. No bias voltage is connected to the base.

RB is connected in series to the base and then directly to a square or pulse
type waveform that serve as the inverter input.
(1) When input to the inverter is high the B-E junction is forward biased and
current flows through RB to base. We choose RB and Rc so that the
amount of base current flowing is enough to saturate the transistor ie:
drive the transistor to the saturation region. The value of VCE
corresponding to this point called VCE(sat) is very nearly zero (typically
0.1V). Current at saturation point is called Ic(sat) Vcc / Rc. When
transistor is saturated it is said to be ON. Therefore High input to
transistor results in low output (0V).
(2) When input to transistor is low (0V), B-E junction has no forward bias
applied to it and hence no collector current flows. There is no voltage
drop across Rc, and so VCE = Vcc. In this case the transistor is in the cutoff region and is said to be OFF. A low input to the transistor results in a
high output.
+Vcc

Rc

Rc
VIN

RB

Vcc/Rc

Rc

Rc
RB

0V

Vcc

0V

Transistor saturated

Switch ON
(closed)

+Vcc

+Vcc

+Vcc

Vcc

Transistor cut-off

Page 31 of 36

Switch OFF
(open)

In designing transistor inverters we assume that Ic(sat)=Vcc/Rc and VCE(sat)=0.

Under these assumptions we can derive the voltage current relations. The
transistor is cut off when the input is low whatever the values of R B and Rc.
Therefore we only need to consider the case when the input is high.
We have derived these equations before, and with Ic=Ic(sat) we get
Ic=Ic(sat)=Vcc / Rc ; IB=Ic(sat) / =Vcc / Rc
IB=(VHI-VBE) / RB where VHI is the high level of the input.
To design a transistor inverter we must specify the values R B and Rc. From
the above equations the values are
RB (VHI-VBE)Rc / Vcc and Rc VccRB/[(VHI-VBE) where is the lowest
value for the transistors used in the circuit. These equations can be used to
find RB when Rc is known or RC when RB is known.
Example: A transistor switch having Rc = 1.5 k is to be designed so that it
will operate with Si transistors whose values range from 80 to 200. What
value of RB should be used? Assume that Vcc = VBE = +5 V.
Using equation for RB above with = min = 80, RB=103.2 k
Exercises: 4 Transistors
1. A Si PN junction is formed from N material doped with 2.5x10 21
donors/m3 and P material doped to have the same impurity density. Find the
thermal voltage and barrier voltage at 40 C.
2. A Si PN junction has a saturation current of 1.8x10-14A. Find the current
in the junction when the forward biasing voltage is 0.6V and temperature 27
C Assume = 1.
3. The forward current in a PN junction is 22 mA when the forward biasing
voltage is 0.64 V. If the thermal voltage is 26 mV and = 1. what is the
saturation current?
4. The forward current in a PN junction is 1.5 mA at 27 C. If Is = 2.4x10-14
A and = 1 what is the forward biasing voltage across the junction>
5. A bar of Si is doped so that one side (side A) has 1.85x10 22 electrons/m3
and the other side (side B) has 2.66x1010 electrons/m3. If the bar is to be
used as a junction diode, which side should be the anode and which side the
cathode? Justify your answer.
6. A diode conducts a current of 440 nA from cathode to anode when the
reverse biasing voltage across it is 8 V. What is the diode DC resistance?
7. A diode is connected in series with a DC source of 12 V and and a resistor
330 . Draw the circuit. If the current is 34.28 mA what is the voltage drop
across the diode? Repeat for a resistor value 220 and a current 51.63 mA.
Page 32 of 36

8. The forward biase I-V characteristics are described in the Table below.
Sketch curve for this values and find (graphically)
a) the approximate ac resistance when the current in the diode is 0.1 mA.
b) the current when the voltage across it is 0.64 V.
c) the DC resistance at the each point above.
9. A diode in forward bias has a voltage drop 0.65 V when connected in
series with a DC source of 3 V, an ac source of 0.5 sin t and a resistor of
1.5 k. Draw the circuit and
a) find the DC current in the iode
b) find the ac resistance of the diode at 27 C
c) write the mathematical expression (function of time) for the total
current and voltage at the diode.
d) what are the maximum and minimum values of the current?
10. A half-wave rectifier circuit has a source of 2 sin t and a load of 2.2
k. The Si diode has a characteristic as shown in the fgure below. Draw the
circuit diagram of the rectifier and find the peak value of the current i(t) and
the voltage VR(t) across the resistor. Sketch the waveforms for e(t), i(t) and
VR(t).
I

0.7

11. In a transistor the emitter current is 1.01 times the collector current. If
the emitter current is 12.12 mA, find the base current.
12. A conventional current of 26 A flow out of the base of a transistor. The
emitter current is 0.94 mA. What is the collector current and is the transistor
NPN or PNP? Draw the transistor circuit symbol sowing all current flows,
directions and magnitude.
13. In a transistor 99.5% of the carriers injected into the base cross the C-B
junction. If the leakage current is 5 A and the collector current is 22 mA,
find a) the exact , b) the emitter current, c) Approximate for ICBO = 0.
14. Derive the approximate equation IB = (1-) IE for ICBO = 0.
15. A transistor has the CB input characteristics shown in the figure below.
If = 0.95, find Ic when VBE=0.72 and VCB = 10V

Page 33 of 36

25 10 0 VCB(V)

IE

(mA) 10
8
6
4
2

Knee
0.4

0.5

0.6

0.7

0.8

VBE(V)

16. A transistor in CE has = 0.98 and a collector to base leakage current of

0.02 A. Find a) the collector to emitter leakage current, b) the , c) Ic when
IB = 0.04 mA, d) approximate Ic neglecting leakage current.
17. A transistor has ICBO = 0.1 A and ICEO = 16 A. Find its .
18. Derive the relation = / (+1)
Prove that the C-C equation IE = (+1) IB is equivalent to IE = IB/(1-)
19. In a NPN CB bias circuit VEE = 5V, VCC= 15V, RE= 2.2 k and RC = 3.3
k. a) Draw the circuit and determine the equation for the load line,
b) Sketch the line and label the value os the intercepts,
c) Find Ic when VCB = 10V, d) VCB when Ic = 1 mA.
20.In a NPN CE bias circuit VCC = +24 V, RB = 220 k and RC = 4.7 k.
Find a) VCE when IC = 1.5 mA, b) IC when VCE = 12 V, c) VCE when IC = 0.
ac amplifiers
21. An ac amplifier has a voltage gain of 55 and a power gain of 456.5. The
ac output current is 24.9 mA rms and the ac input resistance is 200 . Find
a) the current gain, b) the rms value of the input current, c) the rms value of
the input voltage, d) rms value of the ac output voltage, e) the ac output
resistance and f) the output power [Ans. a) 8.3, b) 3mA rms, c) 0.6V rms, d)
33 V rms, e) 1.325 k, f) 0.8215 W].
22. The signal source connected to the input of an ac amplifier has an
internal resistance of 1.2 k. The voltage gain of the amplifier from its input
to output is 140. What minimum value of input resistance should the
amplifier have if the voltage gain from signal source to amplifier output is to
be at least 100? [Ans. rin 3k]
23. The amplifier in the figure below has a current gain Ai = 80 from
amplifier input to amplifier output. Find the total current iL.

5k
3k

1k

is = 0.01 mA rms

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iL
15k

24. At VCE = 10V the CE output characteristics of a transistor show that I C

has the values listed in the Table below for different values of IB. At the Q
point where VCE = 10V what maximum range of IB values results in the
output being a linear reproduction of the input. [Ans. 10A to 25A]
IB A
10
15
20
25
30
35
40

IC mA
0.5
0.75
1.0
1.25
2.1
3.15
4.0

25. The Si transistor in the amplifier stage shown in the figure has = 0.99
and collector resistance rc = 2.5 M. Find a) the input resistance of the
amplifier stage, b) the output resistance of the amplifier stage, c) the voltage
gain of the amplifier, d) the current gain of the amplifier.
[Ans. a) 23.06, b)
10 k , c) 433.65, d) 0.99]
stage

Si
4.7k

+~
-

v0
+18V

-6V

26. Find the rms load voltage vL and the maximum peak to peak output
voltage swing of the amplifier in the figure for when RL equals a) 1 k, b)
10 k, c) 100 k.. Take = 100.
[Ans. a) 0.59 V rms,
b) 1.91 V rms,
c) 2.46 V rms,
+15V

3.3k
715k
Si
=100

10mV rms

10k

vL

27. a) For the amplifier shown in the figure below, find the value of R B that
results in maximum peak to peak output swing.
Page 35 of 36

b) What is the maximum peak to peak value of vs when RB is set to the

value in a)?
[Ans. a) 601.7 k, b) 58.08 mV p-p.
+18V

6.8k
RB
Si
=80

100

vs

1.2k

Transistor as a switch
28. a) The input to the circuit below alternates between 0v and 10V. If the Si
transistor has a of 120, verify that the circuit operates as an inverter.
b) What would be the output voltage of the inverter if i) the input levels
were changed to -5 V to +10 V, ii) the input levels were changed to 0 and
+15 V, iii) was changed to 150. [Ans. a) Icsat =Vcc /Rc= IB=4.545mA]
+10V
2.2k
245.52k

Vo

VIN

29. A transistor inverter is to be designed using Si transistor whose may

vary from 60 to 120. If the series Base resistance is to be 100k, what is the
value of Rc if Vcc = VHI = 4.5 V?

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