Introduction

As I was getting sick and tired of re-reading the instruction set information in the datasheet for the PIC16F8x
microcontroller (very informational, but difficult to read, and spread over several pages), I decided to compile this easy to
read, two page thing of all the instructions and register files. The information presented here has been compiled from the
datasheet, but since typos may appear please use this document with appropriate care. Thank you!
//denMike, April 4th, 2002

Microchip PIC16F8x Instruction Set Summary

Instruction Description

Example

Result

ADDLW
ADDWF

ADDLW 0x15
ADDWF reg,F
ADDWF reg,W
ANDLW
b01010101
ANDWF reg,F
ANDWF reg,W
BCF reg,7
BSF reg,7
BTFSC reg,7
next instruction
BTFSS reg,7
next instruction
CALL label
CLRF reg
CLRW
CLRWDT
COMF reg,F
COMF reg,W
DECF reg,F
DECF reg,W
DECFSZ reg,F
next instruction

W := W + 15h
Reg := Reg + W
W := Reg + W
W := W and 01010101b

ANDLW
ANDWF

Add constant to W
Add W to register, store in register
Add W to register, store in W
AND constant with W

BCF
BSF
BTFSC

AND W with register, store in register

AND W with register, store in W
Bit clear in register
Bit set in register
Bit test, skip if clear

BTFSS

Bit test, skip if set

CALL
CLRF
CLRW
CLRWDT
COMF

Call subroutine
Clear register
Clear W
Clear watchdog timer
Complement register, store in register
Complement register, store in W
Decrement register, store in register
Decrement register, store in W
Decrement register, store in register, skip if 0

DECF
DECFSZ

GOTO
INCF
INCFSZ

IORLW
IORWF
MOVF
MOVLW
MOVWF
NOP
RETFIE
RETLW
RETURN
RLF
RRF
SLEEP
SUBLW
SUBWF
SWAPF
XORLW
XORWF

Decrement register, store in W, skip if 0

DECFSZ reg,W
next instruction

Unconditional branch
Increment register, store in register
Increment register, store in W
Increment register, store in register, skip if 0

GOTO label
INCF reg,F
INCF reg,W
INCFSZ reg,F
next instruction

Increment register, store in W, skip if 0

INCFSZ reg,W
next instruction

Inclusive OR constant with W

Inclusive OR W with register, store in reg
Inclusive OR W with register, store in W
Move register to W
Nothing moved, but Z flag updated
Move constant to W
Move W to register
No operation
Return from interrupt
Return from subroutine with constant in W
Return from subroutine
Rotate register left through carry, store in reg
Rotate register left through carry, store in W
Rotate register right through carry, store in reg
Rotate register right through carry, store in W
Enter power-down mode
Subtract W from constant
Subtract W from register, store in register
Subtract W from register, store in W
Swap nibbles in register, store in register
Swap nibbles in register, store in W
Exclusive OR constant with W
Exclusive OR W with register, store in reg
Exclusive OR W with register, store in W

IORLW d137
IORWF reg,F
IORWF reg,W
MOVF reg,W
MOVF reg,F
MOVLW 13
MOVWF reg
NOP
RETFIE
RETLW 0AAh
RETURN
RLF Reg,F
RLF Reg,W
RRF Reg,F
RRF Reg,W
SLEEP
SUBLW 4
SUBWF reg,F
SUBWF reg,W
SWAPF reg,F
SWAPF reg,W
XORLW 137
XORWF reg,F
XORWF reg,W

Note: TOS = Top of Stack

Reg := Reg and W

W := Reg and W
Reg[bit 7] := 0
Reg[bit 7] := 1
if Reg[bit 7] = 1 then
NEXT INSTRUCTION
if Reg[bit 7] = 0 then
NEXT INSTRUCTION
TOS := PC+1; PC := label
Reg := 0
W := 0
WDT := 0
Reg := not Reg
W := not Reg
Reg := Reg - 1
W := Reg - 1
Reg := Reg - 1
if Reg <> 0 then
NEXT INSTRUCTION
W := Reg - 1
if W <> 0 then
NEXT INSTRUCTION
PC := label
Reg := Reg + 1
W := Reg + 1
Reg := Reg + 1
if Reg <> 0 then
NEXT INSTRUCTION
W := Reg + 1
if W <> 0 then
NEXT INSTRUCTION
W := W or 137d
Reg := Reg or W
W := Reg or W
W := Reg
Z flag updated
W := 13h
Reg := W
PC := TOS; GIE enabled
W := 0AAh; PC := TOS
PC := TOS
Reg := RCL Reg
W := RCL Reg
Reg := RCR Reg
W := RCR Reg
WDT := 0
W := 4 - W
Reg := Reg - W
W := Reg - W
Reg := RegHi xchg RegLo
W := RegHi xchg RegLo
W := W xor 137h
Reg := Reg xor W
W := Reg xor W

Flags
affected
C,DC,Z
C,DC,Z
C,DC,Z
Z
Z
Z
none
none
none
none
none
Z := 1
Z := 1
none
Z
Z
Z
Z
none

none

none
Z
Z
none

none

Z
Z
Z
Z
Z
none
none
none
GIE := 1
none
none
C
C
C
C
none
C,DC,Z
C,DC,Z
C,DC,Z
none
none
Z
Z
Z

Microchip PIC16F8x Memory Layout

BANK0
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
BANK1
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh

Name
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
EEDATA
EEADR
PCLATH
INTCON

Name
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
EECON1
EECON2
PCLATH
INTCON

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Indexed addressing data read/write (not a physical register)
8-bit real-time clock/counter
Low order 8 bits of the Program Counter (PC)
IRP
RP1
RP0
!TO
!PD
Z
Indexed addressing address pointer 0
Unimplemented, read as 0
RA4/TOCKI RA3
RA2
RB7
RB6
RB5
RB4
RB3
RB2
Unimplemented location, read as 0
EEPROM data register
EEPROM address register
Unimplemented, read as 0
Write buffer for upper 5 bits of the PC
GIE
EEIE
T0IE
INTE
RBIE
T0IF

Bit 0

DC

RA1
RB1

RA0
RB0/INT

INTF

RBIF

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Maps address 00h
!RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Maps address 02h
Maps address 03h
Maps address 04h
Unimplemented, read as 0
PORTA data direction register (1=input (default), 0 = output)
PORTA data direction register (1=input (default), 0 = output)
Unimplemented location, read as 0
Unimplemented, read as 0
EEIF
WRERR
WREN
WR
RD
EEPROM control register 2 - used internally for EEPROM writes (not a physical register)
Unimplemented, read as 0
Maps address 0Ah
Maps address 0Bh

STATUS REGISTER
bit Name Description
7
IRP
Not used - should be maintained clear
6
RP1
Not used - should be maintained clear
5
RP0
Register bank select bit
4
!TO
Time-out bit
3
!PD
Power-down bit
2
Z
Zero bit
1
DC
Digit carry/!borrow bit (for ADDWF and
ADDLW instructions)
0
C
Carry/!borrow bit (for ADDWF, ADDLW,
RRF, and RLF instructions)
INTCON REGISTER
bit Name Description
7
GIE
Global interrupt enable bit
6
EEIE EE write complete interrupt enable bit
5
T0IE TMR0 Overflow interrupt enable bit
4
INTE RB0/INT interrupt enable bit
3
RBIE PortB[7:4] Change interrupt enable bit
2
T0IF TMR0 oferflow interrupt flag bit
1
INTF RB0/INT interrupt flag bit
0
RBIF PortB[7:4] change interrupt flag bit

0
always
always
bank 0 (00h-7Fh)
WDT time-out occured
by execution of the SLEEP instr
Last result was NOT zero
No carry-out
No carry-out

0
Disable all interrupts
Disable
Disable
Disable
Disable
No overflow occured
No interrupt occured
No pin have changed

OPTION_REG REGISTER
bit
Name
Description
7
!RBPU
PortB pull-up enable bit
6
INTEDG Interrupt edge select bit
5
T0CS
TMR0 clock source select pin
4
T0SE
TMR0 external (RA4/T0CLK) source edge select bit
3
PSA
Prescaler assignment bit
2:0 PS2:PS0
Prescaler rate select bits
Bit value
000
001
010
011
EECON1
bit
Name
7:5 4
EEIF
3
WRERR
2
WREN
1
WR
0
RD

Bit 1

TMR0 rate
1:2
1:4
1:8
1:16

Description
Unimplemented read as 0
EE write operation interrupt flag bit
EE error flag bit
EE write enable bit
Write control bit
Read control bit

WDT rate
1:1
1:2
1:4
1:8

1
never
never
bank 1 (80h-FFh)
after power-up, CLRWDT or SLEEP instr
after power-up or by the CLRWDT instr
Last result was zero
A carry-out from the 4th low order bit of
the result
A carry-out from the MSB of the result
occured

1
Enables all un-masked ints
Enable
Enable
Enable
Enable
TMR0 has overflowed (must be cleared in software)
An RB0/INT interrupt occured
At least one pin changed (must be cleared in software)

0
Disable pull-ups
RB0/INT intr on falling edge
Internal (clk/4)
Increment on low-to-high
Assigned to TMR0
See below

Bit value
100
101
110
111

0
Always
Not complete
Write completed
Inhibits writes
Write complete
Does nothing

TMR0 rate
1:32
1:64
1:128
1:256

1
Enable pull-ups
RB0/INT intr on rising edge
Transition on RA4/T0CLK pin
Increment on high-to-low
Assigned to watchdog timer
See below

WDT rate
1:16
1:32
1:64
1:128

1
Never
The write operation completed (must be cleared in software)
Write didnt complete
Allows writes
Initiates a write (cleared in hardware)
Initiates an EE read (cleared in hardware)