Arm Board Document

Multi-Colour Line following Robot
CHAPTER 1
INTRODUCTION
The records of various parameters of weather like temperature, humidity and
pressure are vital for day-to-day activity of the people involved in agriculture, fishing etc
and also for industries like salt industry, food processing industry, food storage etc.
Therefore it is proposed to develop a monitoring system for various parameters of
weather using appropriate sensors like humidity sensor, temperature sensor, pressure
sensor for moistures, temperature. These sensors can be interfaced to microcontroller and
the corresponding parameter values can be measured and displayed it on PC.
1.1 MOTIVATION:
The majestic system is developed by using both PC based and microcontroller
section because this system offers low cost, compact, reliable due to integration of CPU,
memory and peripheral devices in a single chip and also mainly the system has been
developed in PC using modem and cordless section. Then we monitor the status on from
any remote area through PC by wireless communication simplex method.
For communication purpose between PC to PC simplex wireless communication
as been developed. The transmitter PC will send serial data at a specified baud rate
through its serial port, which is converted to TTL levels by MAX 232 and converted to
analog. The modulates the analog signal and then transmit through wireless
communication.
In the reception section there is one receiver to receive the data from the
transmitter. The receiver section will receive the transmitted signal and demodulate to
mark and space frequencies. The binary information is converted to RS-232C standard
levels and fed to serial port of receiver PC, which is in remote location area
1.2 Objective
The project deals with the voice recognisation based home automation control
system which is very useful for adults and physical disabled persons.Their was many
projects existed in the market for home automations.
Home Automation industry is growing rapidly; this is fuelled by provide
supporting systems for the elderly and the disabled, especially those who live alone.
Coupled with this, the world population is confirmed to be getting older.
1
DEPARTMENT OF ECE, KGRCET
Home

automation systems must comply with the household standards and convenience of usage.
This paper details the overall design of a wireless home automation system (WHAS)
which has been built and implemented. The automation centres on recognition of voice
commands and uses low-power RF Zigbee wireless communication modules which
are relatively cheap.
CHAPTER 2
EMBEDDED SYSTEM
2.1 INTRODUCTION
An embedded system is a system which is going to do a predefined specified task
is the embedded system and is even defined as combination of both software and
hardware. A general-purpose definition of embedded systems is that they are devices used
to control, monitor or assist the operation of equipment, machinery or plant. "Embedded"
reflects the fact that they are an integral part of the system. At the other extreme a generalpurpose computer may be used to control the operation of a large complex processing
plant, and its presence will be obvious. 3
All embedded systems are including computers or microprocessors. Some of these
computers are however very simple systems as compared with a personal computer.
The very simplest embedded systems are capable of performing only a single
function or set of functions to meet a single predetermined purpose. In more complex
systems an application program that enables the embedded system to be used for a
particular purpose in a specific application determines the functioning of the embedded
system. The ability to have programs means that the same embedded system can be used
for a variety of different purposes. In some cases a microprocessor may be designed in
such a way that application software for a particular purpose can be added to the basic
software in a second process, after which it is not possible to make further changes. The
applications software on such processors is sometimes referred to as firmware.
The simplest devices consist of a single microprocessor (often called a "chip),
which may itself be packaged with other chips in a hybrid system or Application Specific
Integrated Circuit (ASIC). Its input comes from a detector or sensor and its output goes to
a switc or activator which (for example) may start or stop the operation of a machine or,
by operating a valve, may control the flow of fuel to an engine.
As the embedded system is the combination of both software and hardware
Embedded
System
Software
1.
ALP
2.
3.
VB
Hardware
1.
Process
or
2.
Periphe
Etc.,
rals
3.
memor
y System
Figure:2.1 Block diagram of Embedded
Software deals with the languages like ALP, C, and VB etc., and Hardware deals with
Processors, Peripherals, and Memory.
Memory: It is used to store data or address.
Peripherals: These are the external devices connected
Processor: It is an IC which is used to perform some task
Applications of embedded systems
Manufacturing and process control
Construction industry
Transport
Buildings and premises
Domestic service
Communications
Office systems and mobile equipment
Banking, finance and commercial
Medical diagnostics, monitoring and life support
Testing, monitoring and diagnostic systems
Processors are classified into four types like:
Micro Processor (p)
Micro controller (c)
Digital Signal Processor (DSP)

4
Application Specific Integrated Circuits (ASIC)
Micro Processor (p):

A silicon chip that contains a CPU. In the world of personal computers, the terms
microprocessor and CPU are used interchangeably. At the heart of all personal computers
and most workstations sits a microprocessor. Microprocessors also control the logic of
almost all digital devices, from clock radios to fuel-injection systems for automobiles.
Three basic characteristics differentiate microprocessors:
Instruction set: The set of instructions that the microprocessor can execute.
Bandwidth : The number of bits processed in a single instruction.
Clock speed : Given in megahertz (MHz), the clock speed determines how many
instructions per second the processor can execute.
Fig: 2.2 elements of microprocessor

Three Basic Elements of a Microprocessor
Micro Controller (c):
A microcontroller is a small computer on a single integrated circuit containing a
processor core, memory, and programmable input/output peripherals. Program memory
in the form of NOR flash or OTP ROM is also often included on chip, as well as a
typically small amount of RAM. Microcontrollers are designed for embedded
applications, in contrast to the microprocessors used in personal computers or other
general purpose applications.
ALU
CU
Memory
Figure:2.3
Timer, Counter, serial

communication ROM,
ADC, DAC, Timers,
BlockUSART,
Diagram
of Micro
Oscillators
Controller (c)
Digital Signal Processors (DSPs):

Etc.,
Digital Signal Processors is one which performs scientific and mathematical
operation.Digital Signal Processor chips - specialized microprocessors with architectures
designedspecifically for the types of operations required in digital signal processing.
Application Specific Integrated Circuit (ASIC)
ASIC is a combination of digital and analog circuits packed into an IC to achieve
the desired control/computation function
ASIC typically contains
CPU cores for computation and control
Peripherals to control timing critical functions
Memories to store data and program
Analog circuits to provide clocks and interface to the real world which is analog in
nature
I/Os to connect to external components like LEDs, memories, monitors etc.
Computer Instruction Set

There are two different types of computer instruction set there are:
1. RISC (Reduced Instruction Set Computer) and
2. CISC (Complex Instruction Set computer)
Reduced Instruction Set Computer (RISC)

A RISC (reduced instruction set computer) is a microprocessor that is designed to
perform a smaller number of types of computer instruction so that it can operate at a
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higher speed (perform more million instructions per second, or millions of instructions per
second). Since each instruction type that a computer must perform requires additional
transistors and circuitry, a larger list or set of computer instructions tends to make the
microprocessor more complicated and slower in operation.
Complex Instruction Set Computer (CISC)
CISC, which stands for Complex Instruction Set Computer, is a philosophy for
designing chips that are easy to program and which make efficient use of memory. Each
instruction in a CISC instruction set might perform a series of operations inside the
processor. This reduces the number of instructions required to implement a given
program, and allows the programmer to learn a small but flexible set of instructions.
Memory Architecture
There two different types memory architectures there are:
Harvard Architecture
Von-Neumann Architecture
Harvard Architecture
o Computers have separate memory areas for program instructions and data.
There are two or more internal data buses, which allow simultaneous
access to both instructions and data. The CPU fetches program instructions
on the program memory bus.
Von-Neumann Architecture
o A computer has a single, common memory space in which both program
instructions and data are stored. There is a single internal data bus that
fetches both instructions and data. They cannot be performed at the same
time
o The von Neumann architecture is a design model for a stored-program
digital computer that uses a central processing unit (CPU) and a single
separate storage structure ("memory") to hold both instructions and data. It
is named after the mathematician and early computer scientist John von
Neumann. Such computers implement a universal Turing machine and
have a sequential architecture.
CHAPTER 3
HARDWARE DIAGRAM
Fig: 3.1 Block diagram describing connections line following robot
3.1 WORKING
OPERATION:
The input voltage to the diodes 1 and 2 is supplied from a transformer and is equal
to the peak AC voltage of the secondary winding of the transformer as shown in
graph 1.
The circuit consisting of the combination of the two diodes is called full wave
rectifier.
These diodes combined with a capacitor are known as full wave rectifier with a
capacitor. This capacitor is known as filtering capacitor improves the output of the
rectifier and the efficiency of this rectifier is 81.2%.
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The resistor is used to limit the voltage and current those are supplied to the
regulator in order to avoid the regulator from getting damaged.
The diode 3 is used to protect the diodes 1 and 2 from the back current discharged
by the capacitor.
The output at this point is not completely regulated since there is still some
amount of ripple present in the rectified voltage.
Therefore a regulator is used to ensure low voltage ripple and excellent load and
line voltage regulation.
The resistor after the regulator is used to limit the current supplied to the LED.
When the voltage supplied is greater than 3.8V, the LED will glow. The regulated
DC voltage output is taken across the capacitor and is further supplied to other
applications.
CHAPTER 4
ARM MICROPROCESSOR
4.1. Introduction
System-on-chip solutions based on ARM embedded processors address many
different market segments including enterprise applications, automotive systems, home
networking and wireless technologies. The ARM Cortex family of processors provides
a standard architecture to address the broad performance spectrum required by these
diverse technologies. The ARM Cortex family includes processors based on the three
distinct profiles of the ARMv7 architecture; the A profile for sophisticated, high-end
applications running open and complex operating systems,the R profile for real-time
systems; and the M profile optimized for cost-sensitive and microcontroller applications.
The Cortex-M3 processor is the first ARM processor based on the ARMv7-M
architecture and has been specifically designed to achieve high system performance in
power- and cost-sensitive embedded applications, such as microcontrollers, automotive
body systems, industrial control systems and wireless networking, while significantly
simplifying programmability to make the ARM architecture an option for even the
simplest applications.
4.2 The History of ARM

The British computer manufacturer Acorn Computers first developed ARM in the
1980s to use in its personal computers. Its first ARM-based products were coprocessor
modules for the BBC Micro series of computers. After the successful BBC Micro
computer, Acorn Computers considered how to move on from the relatively simple MOS
Technology 6502 processor to address business markets like the one that was soon
dominated by the IBM PC, launched in 1981. The Acorn Business Computer (ABC) plan
required that a number of second processors be made to work with the BBC Micro
platform, but processors such as the Motorola 68000 and National Semiconductor
32016 were considered unsuitable, and the 6502 was not powerful enough for a graphics
based user interface.
After testing all available processors and finding them lacking, Acorn decided it
needed a new architecture. Inspired by white papers on the Berkeley RISC project, Acorn
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considered designing its own processor.A visit to the Western Design Center in Phoenix,
where the 6502 was being updated by what was effectively a single-person company,
showed Acorn engineers Steve Furber and Sophie Wilson they did not need massive
resources and state-of-the-art research and development facilities.
Wilson developed the instruction set, writing a simulation of the processor in BBC
Basic that ran on a BBC Micro with a second 6502 processor. This convinced Acorn engineers
they were on the right track. Wilson approached Acorn's CEO, Hermann Hauser, and requested
more resources. Once he had approval, he assembled a small team to implement Wilson's model
in hardware Developed at Acorn Computers Limited,of Cambridge, England,between 1983
and 1985
Problems with CISC:
Slower then memory parts
Clock cycles per instruction
4.3 Migration from the ARM7 processor family for better

performance and power efficiency
Over the last decade, the ARM7 family of processors has been widely adopted for
many applications. The Cortex-M3 processor builds on this success to present the logical
migration path for ARM7 processor-based systems. The central core offers higher
efficiency; a simpler programming model and excellent deterministic interrupt behaviour,
whilst the integrated peripherals offer enhanced performance at low cost.
Table 4.1 ARM7TDMI-S and Cortex-M3 comparison (100MHz frequency on TSMC

0.18G)
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4.4 ARM and Thumb Performance
4.5 The Thumb-2 instruction set
Variable-length instructions
ARM instructions are a fixed length of 32 bits
Thumb instructions are a fixed length of 16 bits
Thumb-2 instructions can be either 16-bit or 32-bit
Thumb-2 gives approximately 26%
improvement in code density over ARM
Thumb-2 gives approximately 25% improvement in performance over Thumb
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4.6 Pipeline Organization

Increases speed
most instructions executed in single cycle
Versions:
3-stage (ARM7TDMI and earlier)
5-stage (ARMS, ARM9TDMI)
6-stage (ARM10TDMI)
3-stage pipeline: Fetch Decode - Execute
Three-cycle latency,
one instruction per cycle throughput
5-stage pipeline:
Reduces work per cycle =>
allows higher clock frequency
Separates data and instruction memory => reduction of CPI (average number of
clock Cycles Per Instruction)
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4.7 Operating Modes

Except in the M-profile, the 32-bit ARM architecture specifies several CPU modes,
depending on the implemented architecture features. At any moment in time, the CPU
can be in only one mode, but it can switch modes due to external events (interrupts) or
programmatically.
User mode: The only non-privileged mode.
FIQ mode: A privileged mode that is entered whenever the processor accepts an
FIQ interrupt.
IRQ mode: A privileged mode that is entered whenever the processor accepts an
IRQ interrupt.
Supervisor (svc) mode: A privileged mode entered whenever the CPU is reset or
when an SVC instruction is executed.
Abort mode: A privileged mode that is entered whenever a prefetch abort or data
abort exception occurs.
Undefined mode: A privileged mode that is entered whenever an undefined
instruction exception occurs.
System mode (ARMv4 and above): The only privileged mode that is not entered
by an exception. It can only be entered by executing an instruction that explicitly
writes to the mode bits of the CPSR.
4.8 ARM Registers

Registers R0 through R7 are the same across all CPU modes; they are never
banked.R13 and R14 are banked across all privileged CPU modes except system mode.
That is, each mode that can be entered because of an exception has its own R13 and R14.
These registers generally contain the stack pointer and the return address from function
calls, respectively.
Aliases:
R13 is also referred to as SP, the Stack Pointer.
R14 is also referred to as LR, the Link Register.
R15 is also referred to as PC, the Program Counter.
14
Fig: 4.1 ARM Registers description
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CHAPTER 5
HARDWARE REQUIERMENT
5.1 MICRO CONTROLLER
The LPC1768 is a ARM Cortex-M3 based microcontroller for embedded
applications featuring a high level of integration and low power consumption.The ARM
Cortex-M3 is a next generation core that offers system enhancements such as enhanced
debug
features
and
higher
level
of
support
block
integration.The
LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz.
The LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM CortexM3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate
local instruction and data buses as well as a third bus for peripherals. The ARM CortexM3 CPU also includes an internal prefetch unit that supports speculative branching.
The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x
ARM7-based microcontroller series.
5.2 Features and benefits
ARM Cortex-M3 processor, running at frequencies of up to 100 MHz

(LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769).
Up to 512 kB on-chip flash programming memory. Enhanced flash memory

accelerator enables high-speed 120 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.
On-chip SRAM includes:

32/16 kB of SRAM on the CPU with local code/data bus for high-performance
CPU access.
Two/one 16 kB SRAM blocks with separate access paths for higher
throughput.These SRAM blocks may be used for Ethernet, USB, and DMA
memory, as well as for general purpose CPU instruction and data storage.
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Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and Digitalto-Analog converter peripherals, timer match signals, and for memory-to-memory
transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB
master.AHB masters include the CPU, General Purpose DMA controller, Ethernet
MAC, and the USB interface. This interconnect provides communication with no
arbitration delays.
Split APB bus allows high throughput with few stalls between the CPU and DMA.
5.3 Serial interfaces:
Ethernet MAC with RMII interface and dedicated DMA controller.
USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller

and onchip PHY for device, Host, and OTG functions.
Four UARTs with fractional baud rate generation, internal FIFO, and DMA
support.One UART has modem control I/O and RS-485/EIA-485 support, and one
UART has IrDA support.
CAN 2.0B controller with two channels.
SPI controller with synchronous, serial, full duplex communication and

programmable data length.
Two SSP controllers with FIFO and multi-protocol capabilities. The SSP
interfaces can be used with the GPDMA controller.
Three enhanced I2C bus interfaces, one with an open-drain output supporting full
I2C specification and Fast mode plus with data rates of 1 Mbit/s, two with
standard port pins. Enhancements include multiple address recognition and
monitor mode.
70 (100 pin package) General Purpose I/O (GPIO) pins with configurable pullup/down resistors. All GPIOs support a new, configurable open-drain operating
mode. The GPIO block is accessed through the AHB multilayer bus for fast access
and located in memory such that it supports Cortex-M3 bit banding and use by the
General Purpose DMA Controller.
17
12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight

pins,conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC
can be used with the GPDMA controller.
10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and

DMA support.
Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.One motor control PWM with
support for three-phase motor control.
o Quadrature encoder interface that can monitor one external quadrature
encoder.
o One standard PWM/timer block with external count input.
o RTC with a separate power domain and dedicated RTC oscillator. The
RTC block includes 20 bytes of battery-powered backup registers.
WatchDog Timer (WDT). The WDT can be clocked from the internal RC
oscillator,the RTC oscillator, or the APB clock.
ARM Cortex-M3 system tick timer, including an external clock input option.
Repetitive interrupt timer provides programmable and repeating timed interrupts.
Each peripheral has its own clock divider for further power savings.
Standard JTAG test/debug interface for compatibility with existing tools. Serial
Wire Debug and Serial Wire Trace Port options.
Emulation trace module enables non-intrusive, high-speed real-time tracing of

instruction execution.
Integrated PMU (Power Management Unit) automatically adjusts internal

regulators to minimize power consumption during Sleep, Deep sleep, Powerdown, and Deep power-down modes.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep powerdown.
Single 3.3 V power supply (2.4 V to 3.6 V).
Four external interrupt inputs configurable as edge/level sensitive. All pins on

Port 0 and Port 2 can be used as edge sensitive interrupt sources.
Non-maskable Interrupt (NMI) input.

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Clock output function that can reflect the main oscillator clock, IRC clock, RTC
clock,CPU clock, and the USB clock.
The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake
up from any priority interrupt that can occur while the clocks are stopped in deep
sleep,Power-down, and Deep power-down modes.
Processor wake-up from Power-down mode via any interrupt able to operate
during Power-down mode (includes external interrupts, RTC interrupt, USB
activity, Ethernet wake-up interrupt, CAN bus activity, Port 0/2 pin interrupt, and
NMI).
Brownout detect with separate threshold for interrupt and forced reset.
Power-On Reset (POR).
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used

as a system clock.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the main oscillator, the internal RC
oscillator, or the RTC oscillator.
USB PLL for added flexibility.
Code Read Protection (CRP) with different security levels.
Unique device serial number for identification purposes.
FUNCTIONAL DESCRIPTION
5.4
Architectural Overview
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code
bus, and the D-code bus. The I-code and D-code core buses are faster than the system bus
and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code)
and one bus for data access (D-code). The use of two core buses allows for simultaneous
operations if concurrent operations target different devices.
The LPC1768 use a multi-layer AHB matrix to connect the ARM Cortex-M3
buses and other bus masters to peripherals in a flexible manner that optimizes
19

performance by allowing peripherals that are on different slaves ports of the matrix to be
accessed simultaneously by different bus masters
5.5
ARM Cortex-M3 processor
Fig 5.1 Arm cortex-M3 Processor

20

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers
high performance and very low power consumption. The ARM Cortex-M3 offers many
new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptible / continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wake-up interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory
systems can operate continuously. Typically, while one instruction is being executed, its
successor is being decoded, and a third instruction is being fetched from memory.
5.6
On-Chip Flash Program Memory

The LPC1768 contain up to 512 kB of on-chip flash memory. A new two-port
flash accelerator maximizes performance for use with the two fast AHB-Lite buses.
5.7
On-chip SRAM
The LPC1768 contain a total of 64 kB on-chip static RAM memory. This includes
the main 32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed
bus, and two additional 16 kB each SRAM blocks situated on a separate slave port on the
AHB multilayer matrix.
This architecture allows CPU and DMA accesses to be spread over three separate
RAMs that can be accessed simultaneously.
5.8
Memory Protection Unit (Mpu)

The LPC 1768 have a Memory Protection Unit (MPU) which can be used to
improve the reliability of an embedded system by protecting critical data within

The user application. The MPU allows separating processing tasks by disallowing
access to each other's data, disabling access to memory regions, allowing memory regions
to be defined as read-only and detecting unexpected memory accesses that could
potentially break the system.
The MPU separates the memory into distinct regions and implements protection
by preventing disallowed accesses. The MPU supports up to 8 regions each of which can
be divided into 8 sub regions. Accesses to memory locations that are not defined in the
21

MPU regions, or not permitted by the region setting, will cause the Memory Management
Fault exception to take place.
5.9
Memory Map
The LPC1768 incorporates several distinct memory regions, shown in the
following figures. Figure 4 shows the overall map of the entire address space from the
user program viewpoint following reset. The interrupt vector area supports address
remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128
peripherals. The APB peripheral area is 1 MB in size and is divided to allow for up to 64
peripherals. Each peripheral of either type is allocated 16 kB of space. This allows
simplifying the address decoding for each peripheral.
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5.10 Nested Vectored Interrupt Controller (Nvic)

The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU
allows for low interrupt latency and efficient processing of late arriving interrupts.
Features
Controls system exceptions and peripheral interrupts
In the LPC17xx, the NVIC supports 33 vectored interrupts
32 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table
Non-Maskable Interrupt (NMI)
Software interrupt generation
Interrupt Sources
Each peripheral device has one interrupt line connected to the NVIC but may have
several interrupt flags. Individual interrupt flags may also represent more than one
interrupt source.
Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function,
can be programmed to generate an interrupt on a rising edge, a falling edge, or both.
5.11 Pin Connect Block

The pin connect block allows selected pins of the microcontroller to have more
than one function. Configuration registers control the multiplexers to allow connection
between the pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated
and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral
function that is not mapped to a related pin should be considered undefined. Most pins
can also be configured as open-drain outputs or to have a pull-up, pull-down, or no
resistor enabled.
5.12
General Purpose DMA Controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected
peripherals to have DMA support.

23

The GPDMA enables peripheral-to-memory, memory-to-peripheral,peripheral-toperipheral, and memory-to-memory transactions. The source and destination areas can
each be either a memory region or a peripheral, and can be accessed through the AHB
master. The GPDMA controller allows data transfers between the USB and Ethernet
controllers and the various on-chip SRAM areas. The supported APB peripherals are
SSP0/1, for each timer can be used to trigger DMA transfers.
Features
Eight DMA channels. Each channel can support an unidirectional transfer.
16 DMA request lines.
Single DMA and burst DMA request signals. Each peripheral connected to the
DMA Controller can assert either a burst DMA request or a single DMA request.
The DMA burst size is set by programming the DMA Controller.
Memory-to-memory,
memory-to-peripheral,
peripheral-to-memory,
and
peripheral-to-peripheral transfers are supported.
Scatter or gather DMA is supported through the use of linked lists. This means
that the source and destination areas do not have to occupy contiguous areas of
memory.
Hardware DMA channel priority.
AHB slave DMA programming interface. The DMA Controller is programmed by

writing to the DMA control registers over the AHB slave interface.
One AHB bus master for transferring data. The interface transfers data when a
DMA request goes active.
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
Internal four-word FIFO per channel.
Supports 8, 16, and 32-bit wide transactions.
Big-endian and little-endian support. The DMA Controller defaults to little-endian

mode on reset.
An interrupt to the processor can be generated on a DMA completion or when a

DMA error has occurred.
24
Raw interrupt status. The DMA error and DMA count raw interrupt status can be
read prior to masking.
5.13 Fast General Purpose Parallel I/O

Device pins that are not connected to a specific peripheral function are controlled
by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
LPC17xx use accelerated GPIO functions:
GPIO registers are accessed through the AHB multilayer bus so that the fastest
possible I/O timing can be achieved.
Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
All GPIO registers are byte and half-word addressable.
Entire port value can be written in one instruction.
Support for Cortex-M3 bit banding.

Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital
function can be programmed to generate an interrupt on a rising edge, a falling edge, or

both. The edge detection is asynchronous, so it may operate when clocks are not present
such as during Power-down mode. Each enabled interrupt can be used to wake up the chip
from Power-down mode.
Features
Bit level set and clear registers allow a single instruction to set or clear any
number of bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
Pull-up/pull-down resistor configuration and open-drain configuration can be

programmed through the pin connect block for each GPIO pin.
5.14 Ethernet
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
25

designed to provide optimized performance through the use of DMA hardware
acceleration.Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry,
receive packet filtering and wake-up on LAN activity. Automatic frame transmission
and reception with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share the ARM Cortex-M3 D-code and
system bus through the AHB-multilayer matrix to access the various on-chip SRAM
blocks for Ethernet data, control, and status information.
The Ethernet block interfaces between an off-chip Ethernet PHY using the
Reduced MII (RMII) protocol and the on-chip Media Independent Interface
Management (MIIM) serial bus.
Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry,
receive packet filtering and wake-up on LAN activity. Automatic frame transmission
and reception with scatter-gather DMA off-loads many operations from the CPU.
Features
Ethernet standards support:
Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 BaseTX,100 Base-FX, and 100 Base-T4.
Fully compliant with IEEE standard 802.3.
Fully compliant with 802.3x full duplex flow control and half duplex back
pressure.
Flexible transmit and receive frame options.
Virtual Local Area Network (VLAN) frame support.
Memory management:
o Independent transmit and receive buffers memory mapped to shared
SRAM
o DMA managers with scatter/gather DMA and arrays of frame descriptors.
o Memory traffic optimized by buffering and pre-fetching.
Enhanced Ethernet features:

o Receive filtering.
26

o Multicast and broadcast frame support for both transmit and receive.
o Optional automatic Frame Check Sequence (FCS) insertion with
Cyclic Redundancy Check (CRC) for transmit.
o Selectable automatic transmit frame padding.
o Over-length frame support for both transmit and receive allows any
length frames.
o Promiscuous receive mode.
o Automatic collision back-off and frame retransmission.
o Includes power management by clock switching.
o Wake-on-LAN power management support allows system wake-up:
using the receive filters or a magic frame detection filter.
Physical interfacing:
o Attachment of external PHY chip through standard RMII interface.
o PHY register access is available via the MIIM interface.
5.15 USB Interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication
between a host and one or more (up to 127) peripherals. The host controller allocates the
USB bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The USB interface includes a device, Host, and OTG controller with on-chip PHY
for device and Host functions. The OTG switching protocol is supported through the use
of an external controller.
5.16 USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host
controller. It consists of a register interface, serial interface engine, endpoint buffer
memory, and a DMA controller. The serial interface engine decodes the USB data stream
and writes data to the appropriate endpoint buffer. The status of a completed USB transfer
or error condition is indicated via status registers. An interrupt is also generated if
enabled. When enabled, the DMA controller transfers data between the endpoint buffer
and the on-chip SRAM.
27

Features
Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by

software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mode, the part can enter one of the reduced power
modes and wake up on USB activity.
Supports DMA transfers with all on-chip SRAM blocks on all non-control
endpoints.
Allows dynamic switching between CPU-controlled slave and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
5.17 USB host controller

The host controller enables full and low-speed data exchange with USB devices
attached to the bus. It consists of a register interface, a serial interface engine,and a DMA
controller. The register interface complies with the OHCI specification.
Features
OHCI compliant.
One downstream port.
Supports port power switching.
5.18 USB OTG controller
USB OTG is a supplement to the USB 2.0 specification that augments the
capability of existing mobile devices and USB peripherals by adding host functionality
for connection to USB peripherals.
The OTG Controller integrates the host controller, device controller, and a masteronly I2C-bus interface to implement OTG dual-role device functionality. The dedicated
I2C-bus interface controls an external OTG transceiver.
Features
Fully compliant with On-The-Go supplement to the USB 2.0 Specification,

28
Hardware support for Host Negotiation Protocol (HNP).
Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011)
5.19 CAN Controller And Acceptance Filters

The Controller Area Network (CAN) is a serial communications protocol which
efficiently supports distributed real-time control with a very high level of security. Its
domain of application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously,
allowing the device to be used as a gateway, switch, or router among a number of CAN
buses in industrial or automotive applications.
Features
Two CAN controllers and buses.
Data rates to 1 Mbit/s on each bus.
32-bit register and RAM access.
Compatible with CAN specification 2.0B, ISO 11898-1.
Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit)

receive identifiers for all CAN buses.
Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard Identifiers.
FullCAN messages can generate interrupts.
12-Bit ADC
The LPC17xx contain a single 12-bit successive approximation ADC with eight
channels and DMA support.
Features
12-bit successive approximation ADC.
Input multiplexing among 8 pins.
29
Power-down mode.
Measurement range VREFN to VREFP.
12-bit conversion rate: 200 kHz.
Individual channels can be selected for conversion.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or Timer Match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
DMA support.
20-bit DAC
The DAC allows to generate a variable analog output. The maximum output value
of the DAC is VREFP.
Features
10-bit DAC
Resistor string architecture
Buffered output
Power-down mode
Selectable output drive
Dedicated conversion timer
DMA support
5.20 UART
The LPC1768 each contain four UARTs. In addition to standard transmit and
receive data lines, UART1 also provides a full modem control handshake interface and
support for RS-485/9-bit mode allowing both software address detection and automatic
address detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
Features
Maximum UART data bit rate of 6.25 Mbit/s.
16 B Receive and Transmit FIFOs.
30
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Auto baud capabilities and FIFO control mechanism that enables software flow
Control implementation.
UART1 equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
Support for RS-485/9-bit/EIA-485 mode (UART1).
UART3 includes an IrDA mode to support infrared communication.
All UARTs have DMA support.
5.21 SPI Serial I/O Controller

The LPC17xx contain one SPI controller. SPI is a full duplex serial interface
designed to handle multiple masters and slaves connected to a given bus. Only a single
master and a single slave can communicate on the interface during a given data transfer.
During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and
the slave always sends 8 bits to 16 bits of data to the master.
Features
Maximum SPI data bit rate of 12.5 Mbit/s
Compliant with SPI specification
Synchronous, serial, full duplex communication
Combined SPI master and slave
Maximum data bit rate of one eighth of the input clock rate
8 bits to 16 bits per transfer
5.22 SSP serial I/O controller

The LPC17xx contain two SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters
and slaves on the bus. Only a single master and a single slave can communicate on the
bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4
31

bits to 16 bits of data flowing from the master to the slave and from the slave to the
master. In practice, often only one of these data flows carries meaningful data.
Features
Maximum SSP speed of 50 Mbit/s (master) or 8 Mbit/s (slave)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
DMA transfers supported by GPDMA
5.23 I2C-Bus Serial I/O Controllers

The LPC1768 each contain three I2C-bus controllers.The I2C-bus is bidirectional
for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial DAta line
(SDA). Each device is recognized by a unique address and can operate as either a
receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both
receive and send information (such as memory). Transmitters and/or receivers can operate
in either master or slave mode, depending on whether the chip has to initiate a data
transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more
than one bus master connected to it.
Features
I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also
supports Fast mode plus with bit rates up to 1 Mbit/s.
I2C1 and I2C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2Cbus).
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).

32
Arbitration between simultaneously transmitting masters without corruption of

seria data on the bus.
Serial clock synchronization allows devices with different bit rates to

communicate via one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend

and resume serial transfer.
The I2C-bus can be used for test and diagnostic purposes.
All I2C-bus controllers support multiple address recognition and a bus monitor
mode.
5.24 I2S-bus serial I/O controllers

The I2S-bus provides a standard communication interface for digital audio
applications.
The I2S-bus specification defines a 3-wire serial bus using one data line, one clock
line,and one word select signal. The basic I2S-bus connection has one master, which is
always the master, and one slave. The I2S-bus interface provides a separate transmit and
receive channel, each of which can operate as either a master or a slave.
Features
The interface has separate input/output channels each of which can operate in
master or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 96 kHz (16,22.05,32,44.1,

48,96) kHz.
Support for an audio master clock.
Configurable word select period in master mode (separately for I2S-bus input and
output).
Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are

connected to the GPDMA block.
33
Controls include reset, stop and mute options separately for I2S-bus input and I2Sbus output.
5.25 General purpose 32-bit timers/external event counters

The LPC17xx include four 32-bit timer/counters. The timer/counter is designed to
count cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts, generate timed DMA requests, or perform other actions at specified
timer values, based on four match registers. Each timer/counter also includes two capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
Features
A 32-bit timer/counter with a programmable 32-bit prescaler.
Counter or timer operation.
Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
Four 32-bit match registers that allow:

o Continuous operation with optional interrupt generation on match.
o Stop timer on match with optional interrupt generation.
o Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following

capabilities:
o Set LOW on match.
o Set HIGH on match.
o Toggle on match.
o Do nothing on match.
o Up to two match registers can be used to generate timed DMA requests.
5.26 Pulse Width Modulator

The PWM is based on the standard Timer block and inherits all of its features,
although only the PWM function is pinned out on the LPC1768. The Timer is designed to
count cycles of the system derived clock and optionally switch pins, generate interrupts or
perform other actions when specified timer values occur, based on seven match
34

registers.The PWM function is in addition to these features, and is based on match
register events.
The ability to separately control rising and falling edge locations allows the PWM
to be used for more applications. For instance, multi-phase motor control typically
requires three non-overlapping PWM outputs with individual control of all three pulse
widths and positions.
Two match registers can be used to provide a single edge controlled PWM output.
One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have
a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges
controlled.Again, the PWMMR0 match register controls the PWM cycle rate. The other
match registers control the two PWM edge positions. Additional double edge controlled
PWM outputs require only two match registers each, since the repetition rate is the same
for all PWM outputs.
With double edge controlled PWM outputs, specific match registers control the
rising and falling edge of the output. This allows both positive going PWM pulses (when
the rising edge occurs prior to the falling edge), and negative going PWM pulses (when
the falling edge occurs prior to the rising edge).
Features
Tracks encoder position.
Increments/decrements depending on direction.
Programmable for 24x or 4x position counting.
Velocity capture using built-in timer.
Velocity compare function with less than interrupt.
Uses 32-bit registers for position and velocity.
Three position compare registers with interrupts.
Index counter for revolution counting.
Index compare register with interrupts.

35
Can combine index and position interrupts to produce an interrupt

for whole and partial revolution displacement.
5.27
Digital filter with programmable delays for encoder input signals.
Can accept decoded signal inputs (clk and direction).
Connected to APB.
Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable
amount of time if it enters an erroneous state. When enabled, the watchdog will generate a
system reset if the user
program fails to feed (or reload) the watchdog within a
predetermined amount of time.
5.28 LIGHT DEPENDENT RESISTOR

A photoresistor or light dependent resistor or cadmium sulfide (CdS) cell is
a resistor whose resistance decreases with increasing incident light intensity. It can also be
referred to as a photoconductor.
A photo resistor is made of a high resistance semiconductor. If light falling on the
device is of high enough frequency, photons absorbed by the semiconductor give
bound electrons enough energy to jump into the conduction band. The resulting free
electron (and its hole partner) conduct electricity, there by lowering resistance.
A photoelectric device can be either intrinsic or extrinsic. An intrinsic
semiconductor has its own charge carriers and is not an efficient semiconductor, e.g.
silicon. In intrinsic devices the only available electrons are in the valence band, and hence
the photon must have enough energy to excite the electron across the entire bandgap.
Extrinsic devices have impurities, also called dopants, added whose ground state energy is
closer to the conduction band; since the electrons do not have as far to jump, lower energy
photons (i.e., longer wavelengths and lower frequencies) are sufficient to trigger the
device. If a sample of silicon has some of its atoms replaced by phosphorus atoms
(impurities), there will be extra electrons available for conduction. This is an example of
an extrinsic semiconductor. An intrinsic semiconductor has its own charge carriers and is
not an efficient semiconductor.
36
The symbol for a photoresistor
5.29 Applications:
Photoresistors come in many different types. Inexpensive cadmium sulfide cells
can be found in many consumer items such as camera light meters, street lights, clock
radios, alarms, and outdoor clocks.
They
are
also
used
in
some dynamic
compressors together
with
small incandescent lamp or light emitting diode to control gain reduction.

Lead sulfide (PbS) and indium antimonide (InSb) LDRs (light dependent resistor)
are used for the mid infrared spectral region. Ge:Cu photoconductors are among the best
far-infrared detectors available, and are used for infrared astronomy and infrared
spectroscopy.
Transducers are used for changing energy types.
A light dependent resistor is a small, round semiconductor. Light dependent

resistors are used to re-charge a light during different changes in the light, or they are
made to turn a light on during certain changes in lights. One of the most common uses for
light dependent resistors is in traffic lights. The light dependent resistor controls a built in
heater inside the traffic light, and causes it to recharge over night so that the light never
37

dies. Other common places to find light dependent resistors are in: infrared detectors,
clocks and security alarms.
LDRs or Light Dependent Resistors are very useful especially in light/dark sensor
circuits. Normally the resistance of an LDR is very high, sometimes as high as 1000 000
ohms, but when they are illuminated with light resistance drops dramatically.
The animation opposite shows that when the torch is turned on, the resistance of the
LDR falls, allowing current to pass through it.
Circuit Wizard software has been used to display, the range of values of
aORP12,LDR. When a light level of 1000 lux (bright light) is directed towards it, the
resistanceis
400R(ohms).
When a light level of 10 lux (very low light level) is directed towards it, the resistance has
risen dramatically to 10.43M (10430000 ohms).
38
Basic structure:
Fig: 5.3 LDR basic structure

This is an example of a light sensor circuit :
Although there are many ways in which LDRs or photo resistors can be
manufactured, ther are naturally a few more common methods that are seen. Essentially
the LDR or photo resistor consists of a resistive material sensitive to light that is exposed
to light. The photo resistive element comprises section of material with contacts at either
end. Although many of the material used for light dependent resistors are semiconductors,
when used as photo resistors, they are used only as a resistive element and there are no pn junctions. Accordingly the devices purely passive.
5.30 Operation:
Light Dependent Resistor made of a high resistance semiconductor, if light falling
on the is of high enough efficiently, photon absorbed by the semiconductor give bound
electrons enough energy to jump into the conduction band. The resulting free electron
(and its hole partner) conduct electricity, thereby lowering resistance.
In intrinsic devices, the only available electrons are in the valence band, and hence
the photon must have enough energy to excite the electrons across the entire band gap.
Extrinsic devices have impurities added , which have a ground state energy closer to the
39

conduction band, since the electrons dont have so far to jump, lower energy photons ( i.e.
longer wavelengths and lower frequencies ) will suffice to trigger the device.
5.31 Characteristics of LDR:

The characteristics of LDR are shown below. Here the resistance variations are
shown as a function of illumination. The resistance of LDR decreases with increasing
incident light intensity
1000
100
Res.
10
0.1
1.0
10
100
( Ftc )*
*1 Ftc = 10.764 lumens
Fig 3.3.2: - Characteristics of LDR
5.32 LDR Applications:
40

LDRs are very useful especially in light/dark sensor circuits. Normally the
resistance of LDR is very high, sometimes as high as 1000k ohms,but when they are
illuminated with light, resistance drops immediately.
1
Camera light meters.
Clock radios.
Security alarms.
Optical switches.
Far infrared detector.
Streetlights.
5.33 DC MOTOR
DC motors are configured in many types and sizes, including brush less, servo,
and gear motor types. A motor consists of a rotor and a permanent magnetic field stator.
The magnetic field is maintained using either permanent magnets or electromagnetic
windings. DC motors are most commonly used in variable speed and torque.
Motion and controls cover a wide range of components that in some way are used
to generate and/or control motion. Areas within this category include bearings and
bushings, clutches and brakes, controls and drives, drive components, encoders and
resolves, Integrated motion control, limit switches, linear actuators, linear and rotary
motion components, linear position sensing, motors (both AC and DC motors),
orientation position sensing, pneumatics and pneumatic components, positioning stages,
slides and guides, power transmission (mechanical), seals, slip rings, solenoids springs.
Motors are the devices that provide the actual speed and torque in a drive system.
This family includes AC motor types (single and multiphase motors, universal, servo
motors, induction, synchronous, and gear motor) and DC motors (brush less, servo motor,
and gear motor) as well as linear, stepper and air motors, and motor contactors and
starters.
In any electric motor, operation is based on simple electromagnetism. A currentcarrying conductor generates a magnetic field; when this is then placed in an external
magnetic field, it will experience a force proportional to the current in the conductor, and
to the strength of the external magnetic field. As you are well aware of from playing with
41

magnets as a kid, opposite (North and South) polarities attract, while like polarities (North
and North, South and South) repel.
The internal configuration of a DC motor is designed to harness the magnetic
interaction between a current-carrying conductor and an external magnetic field to
generate rotational motion.
Let's start by looking at a simple 2-pole DC electric motor (here red represents a
magnet or winding with a "North" polarization, while green represents a magnet or
winding with a "South" polarization).
Fig 5.2 dc motor construction

Every DC motor has six basic parts -- axle, rotor (a.k.a., armature), stator,
commutator, field magnet(s), and brushes. In most common DC motors (and all that
Beamers will see), the external magnetic field is produced by high-strength permanent
magnets1. The stator is the stationary part of the motor -- this includes the motor casing,
as well as two or more permanent magnet pole pieces. The rotor (together with the axle
and attached commutator) rotates with respect to the stator. The rotor consists of windings
(generally on a core), the windings being electrically connected to the commutator. The
above diagram shows a common motor layout -- with the rotor inside the stator (field)
magnets.
The geometry of the brushes, commutator contacts, and rotor windings are such
that when power is applied, the polarities of the energized winding and the stator
magnet(s) are misaligned, and the rotor will rotate until it is almost aligned with the
stator's field magnets. As the rotor reaches alignment, the brushes move to the next
commutator contacts, and energize the next winding.
42

Given our example two-pole motor, the rotation reverses the direction of current
through the rotor winding, leading to a "flip" of the rotor's magnetic field, and driving it to
continue rotating.
In real life, though, DC motors will always have more than two poles (three is a
very common number). In particular, this avoids "dead spots" in the commutator. You can
imagine how with our example two-pole motor, if the rotor is exactly at the middle of its
rotation (perfectly aligned with the field magnets), it will get "stuck" there. Meanwhile,
with a two-pole motor, there is a moment where the commutator shorts out the power
supply (i.e., both brushes touch both commutator contacts simultaneously). This would be
bad for the power supply, waste energy, and damage motor components as well. Yet
another disadvantage of such a simple motor is that it would exhibit a high amount of
torque ripple" (the amount of torque it could produce is cyclic with the position of the
rotor).
Fig 5.3 Two pole design

So since most small DC motors are of a three-pole design, let's tinker with the workings
of one via an interactive animation (JavaScript required)
Fig 5.4 Three pole design
43

You'll notice a few things from this -- namely, one pole is fully energized at a time
(but two others are "partially" energized). As each brush transitions from one commutator
contact to the next, one coil's field will rapidly collapse, as the next coil's field will rapidly
charge up (this occurs within a few microsecond). We'll see more about the effects of this
later, but in the meantime you can see that this is a direct result of the coil windings' series
wiring:
Fig 5.5 coil windings

There's probably no better way to see how an average dc motor is put together,
than by just opening one up. Unfortunately this is tedious work, as well as requiring the
destruction of a perfectly good motor.
This is a basic 3-pole dcmotor, with 2 brushes and three commutator contacts.
5.34 PWM TECHNIQUE:

A pulse width modulator (PWM) is a device that may be used as an efficient light
dimmer or DC motor speed controller. A PWM works by making a square wave with a
variable on-to-off ratio; the average on time may be varied from 0 to 100 percent. In this
manner, a variable amount of power is transferred to the load.
The main advantage of a PWM circuit over a resistive power controller is the
efficiency, at a 50% level, the PWM will use about 50% of full power, almost all of which
is transferred to the load, a resistive controller at 50% load power would consume about
71% of full power, 50% of the power goes to the load and the other 21% is wasted heating
the series resistor. Load efficiency is almost always a critical factor in solar powered and
44

other alternative energy systems. One additional advantage of pulse width modulation is
that the pulses reach the full supply voltage and will produce more torque in a motor by
being able to overcome the internal motor resistances more easily. Finally, in a PWM
circuits, common small potentiometers may be used to control a wide variety of loads
whereas large and expensive high power variable resistors are needed for resistive
controllers.
Pulse width modulation consists of three signals, which are modulated by a square
wave. The duty cycle or high time is proportional to the amplitude of the square wave.
The effective average voltage over one cycle is the duty cycle times the peak-to-peak
voltage. Thus, the average voltage follows a square wave. In fact, this method depends on
the motor inductance to integrate out the PWM frequency.
Fig 8.1.4 output wave forms

A very simply off line motor drive can be built using a TRIAC and a control IC.
This circuit can control the speed of a universal motor. A universal motor is a series
wound DC motor. The circuit uses phase angle control to vary the effective motor
voltage.
Fig 8.1.5 dc motor circuitary

A micro controller can also be used to control a triac. A PNP of transistor may be
used to drive the triac. As shown, the MCU ground is connected to the AC line. The gate
45

trigger current is lower if instead the MCU 5V supply is connected to the AC line. The
MCU must have some means of detecting zero crossing and a timer, which can control
the triac firing. A general-purpose timer with one input capture and one output compare
makes an ideal phase angle control.
5.35 L293D IC (DC MOTOR DRIVER)
Fig:5.6 L293D Driver ICs

46

The L293 and L293D are quadruple high-current half-H drivers. The L293 is
designed to provide bidirectional drive currents of up to 1 A at voltages from 4.5 V to 36
V. The L293D is designed to provide bidirectional drive currents of up to 600-mA at
voltages from 4.5 V to 36 V. Both devices are designed to drive inductive loads such as
relays, solenoids, dc and bipolar stepping motors, as well as other high-current/highvoltage loads in positive-supply applications. All inputs are TTL compatible. Each output
is a complete totem-pole drive circuit, with a Darlington transistor sink and a pseudoDarlington source. Drivers are enabled in pairs, with drivers 1 and 2 enabled by 1,2EN
and drivers 3 and 4 enabled by 3,4EN.
When an enable input is high, the associated drivers are enabled and their outputs
are active and in phase with their inputs. When the enable input is low, those drivers are
disabled and their outputs are off and in the high-impedance state. With the proper data
inputs, each pair of drivers forms a full-H (or bridge) reversible drive suitable for solenoid
or motor applications. On the L293, external high-speed output clamp diodes should be
used for inductive transient suppression. A VCC1 terminal, separate from VCC2, is
provided for the logic inputs to minimize device power dissipation. The L293and L293D
are characterized for operation from 0C to 70C.
Fig 5.7 conrolling of dc motor
47
Fig 4.8.2.3 Truth table for dc motor

RESISTORS: A Resistor is a heat-dissipating element and in the electronic circuits it is mostly
used for either controlling the current in the circuit or developing a voltage drop across it,
which could be utilized for many applications. There are various types of resistors, which
can be classified according to a number of factors depending upon:
Material used for fabrication
Wattage and physical size
Intended application
Ambient temperature rating
Cost
Basically the resistor can be split in to the following four parts from the construction view
point.
(1) Base
(2) Resistance element
48

(3) Terminals
(4) Protective means.
The following characteristics are inherent in all resistors and may be controlled by
design considerations and choice of material i.e. Temperature coefficient of resistance,
Voltage coefficient of resistance, high frequency characteristics, power rating, tolerance
& voltage rating of resistors. Resistors may be classified as
Fixed
Semi variable
Variable resistor.
CAPACITORS
The fundamental relation for the capacitance between two flat plates separated by
a dielectric material is given by:C=0.08854KA/D
Where,
C= capacitance in pf.
K= dielectric constant
A=Area per plate in square cm.
D=Distance between two plates in cm
Design of capacitor depends on the proper dielectric material with particular type
of application. The dielectric material used for capacitors may be grouped in various
classes like Mica, Glass, air, ceramic, paper, Aluminum, electrolyte etc. The value of
capacitance never remains constant. It changes with temperature, frequency and aging.
The capacitance value marked on the capacitor strictly applies only at specified
temperature and at low frequencies.
49
CHAPTER 6
SOFTWARE REQUIREMENT
6.1 Software Components:
a) ABOUT SOFTWARE
Softwares used are:
*Keil software for c programming
*Express PCB for lay out design
*Express SCH for schematic design
What's New in Vision3?
Vision3 adds many new features to the Editor like Text Templates, Quick
Function Navigation, and Syntax Coloring with brace high lighting Configuration Wizard
for dialog based startup and debugger setup. Vision3 is fully compatible to Vision2 and
can be used in parallel with Vision2.
What is Vision3?
Vision3 is an IDE (Integrated Development Environment) that helps you write,
compile, and debug embedded programs. It encapsulates the following components:
A project manager.
A make facility.
Tool configuration.
Editor.
To help you get started, several example programs (located in the \C51\Examples,
\C251\Examples, \C166\Examples, and \ARM\...\Examples) are provided.

HELLO is a simple program that prints the string "Hello World" using the Serial
Interface.
MEASURE is a data acquisition system for analog and digital systems.
TRAFFIC is a traffic light controller with the RTX Tiny operating system.
SIEVE is the SIEVE Benchmark.
DHRY is the Dhrystone Benchmark.
50

WHETS is the Single-Precision Whetstone Benchmark.
Additional example programs not listed here are provided for each device
architecture.
Building an Application in Vision2

To build (compile, assemble, and link) an application in Vision2, you must:
1
Select Project -(forexample,166\EXAMPLES\HELLO\HELLO.UV2).
Select Project - Rebuild all target files or Build target.

Vision2 compiles, assembles, and links the files in your project.
Creating Your Own Application in Vision2

To create a new project in Vision2, you must:
Select Project - New Project.
Select a directory and enter the name of the project file.
Select Project - Select Device and select an 8051, 251, or C16x/ST10 device from
the Device Database.
Create source files to add to the project.
Select Project - Targets, Groups, Files. Add/Files, select Source Group1, and add
the source files to the project.
Select Project - Options and set the tool options. Note when you select the target
device from the Device Database all special options are set automatically. You
typically only need to configure the memory map of your target hardware. Default
memory model settings are optimal for most applications.
Select Project - Rebuild all target files or Build target.
Debugging an Application in Vision2

To debug an application created using Vision2, you must:
Select Debug - Start/Stop Debug Session.
Use the Step toolbar buttons to single-step through your program. You may enter
G, main in the Output Window to execute to the main C function.
Open the Serial Window using the Serial #1 button on the toolbar.
51
CPU Simulation
Vision2 simulates up to 16 Mbytes of memory from which areas can be mapped
for read, write, or code execution access. The Vision2 simulator traps and reports illegal
memory accesses.
In addition to memory mapping, the simulator also provides support for the
integrated peripherals of the various 8051 derivatives. The on-chip peripherals of the CPU
you have selected are configured from the Device
Database selection
you have made when you create your project target. Refer to page 58 for more
Information about selecting a device. You may select and display the on-chip peripheral
components using the Debug menu. You can also change the aspects of each peripheral
using the controls in the dialog boxes.
Start Debugging
You start the debug mode of Vision2 with the Debug Start/Stop Debug Session
command. Depending on the Options for Target Debug Configuration, Vision2 will
load the application program and run the startup code Vision2 saves the editor screen
layout and restores the screen layout of the last debug session. If the program execution
stops, Vision2 opens an editor window with the source text or shows CPU instructions
in the disassembly window. The next executable statement is marked with a yellow arrow.
During debugging, most editor features are still available.
For example, you can use the find command or correct program errors. Program
source text of your application is shown in the same windows. The Vision2 debug mode
differs from the edit mode in the following aspects:
_ The Debug Menu and Debug Commands described on page 28 are
Available. The additional debug windows are discussed in the following.
_ The project structure or tool parameters cannot be modified. All build
Commands are disabled.
52
Disassembly Window
The Disassembly window shows your target program as mixed source and
assembly program or just assembly code. A trace history of previously executed
instructions may be displayed with Debug View Trace Records. To enable the trace
history, set Debug Enable/Disable Trace Recording.
If you select the Disassembly Window as the active window all program step
commands work on CPU instruction level rather than program source lines. You can
select a text line and set or modify code breakpoints using toolbar buttons or the context
menu commands.
You may use the dialog Debug Inline Assembly to modify the CPU
instructions. That allows you to correct mistakes or to make temporary changes to the
target program you are debugging.
B) Keil Software
Installing the Keil software on a Windows PC
Insert the CD-ROM in your computers CD drive
On most computers, the CD will auto run, and you will see the Keil installation
menu. If the menu does not appear, manually double click on the Setup icon, in
the root directory: you will then see the Keil menu.
On the Keil menu, please select Install Evaluation Software. (You will not
require a license number to install this software).
Follow the installation instructions as they appear.
Loading the Projects

The example projects for this book are NOT loaded automatically when you install the
Keil compiler.
These files are stored on the CD in a directory /Pont. The files are arranged by chapter:
for example, the project discussed in Chapter 3 is in the directory /Pont/Ch03_00-Hello.
Rather than using the projects on the CD (where changes cannot be saved), please copy
the files from CD onto an appropriate directory on your hard disk.
53
Note: you will need to change the file properties after copying: file transferred from the
CD will be read only.
Configuring the Simulator
Open the Keil Vision2
go to Project Open Project and browse for Hello in Ch03_00 in Pont and open it.
6.2 KEIL SOFTWARE TOOL(STEPS)

Click on the Keil uVision Icon on DeskTop
1. The following fig will appear
2. Click on the Project menu from the title bar

3. Then Click on New Project
54
4. Save the Project by typing suitable project name with no extension in u r own
folder sited in either C:\ or D:\
5. Then Click on Save button above.

6. Select the component for u r project. i.e. Atmel
7. Click on the + Symbol beside of Atmel
55
8. Select AT89C52 as shown below
9. Then Click on OK
10. The Following fig will appear
56
11. Then Click either YES or NOmostly NO

12. Now your project is ready to USE
13. Now double click on the Target1, you would get another option Source group 1
as shown in next page.
14. Click on the file option from menu bar and select new
57
15. The next screen will be as shown in next page, and just maximize it by double
clicking on its blue boarder.
16.
17. Now start writing program in either in C or ASM
18. For a program written in Assembly, then save it with extension . asm and for
C based program save it with extension .C
58
19. Now right click on Source group 1 and click on Add files to Group Source
20. Now you will get another window, on which by default C files will appear.
59
21. Now select as per your file extension given while saving the file
22. Click only one time on option ADD
23. Now Press function key F7 to compile. Any error will appear if so happen.
24. If the file contains no error, then press Control+F5 simultaneously.

25. The new window is as follows
60
26. Then Click OK

27. Now Click on the Peripherals from menu bar, and check your required port as
shown in fig below
28. Drag the port a side and click in the program file.
61
29. Now keep Pressing function key F11 slowly and observe.
30. You are running your program successfully
6.3 CREATE A PROJECT:

Vision3 includes a project manager which makes it easy to design applications
for an ARM based microcontroller. We need to perform the following steps to create a
new project:
Create Project file and Select CPU
Project Workspace-Books
Create New Source Files
Add Source Files to the Project
Create Files Groups
Set tool Options for Target Hardware
Configure the CPU Start-up Code
Build Project and Generate Application Program Code
Create a HEX File for PROM Programming
6.4 DEBUG FUNCTIONS:

We use Debug Functions to:
Extend the capabilities of the Vision3 Debugger.

62
Generate external interrupts,
Log memory contents to a file,
Update analog input values periodically,
Input serial data to an on-chip serial port.
SIMULATION:
The Vision3 Debugger incorporates a C script language you can use to create
Signal Functions. Signal functions let us simulate analog and digital input to the
microcontroller. Signal functions run in the background while Vision3 simulates our
target program.
The Vision3 simulator simulates the timing and logical behaviour of serial
communication protocols like UART, IC, SPI, and CAN. But Vision3 does not simulate
the I/O port toggling of the physical communication pins on the I/O port.
To provide fast simulation speed and optimum access to communication
peripherals, the logic behaviour of communication peripherals is reflected in virtual
registers that are listed with the DIR VTREG command. This has the benefit that we can
easily write debug functions that stimulate complex peripherals.
DIALOGS:
The Vision3 IDE/Debugger provides several dialog pages that are grouped into the
following categories:
File-Device Database: review and modify the microcontroller device list.
File-License Management: manage software licenses.
Edit-Find in Files: text search across multiple files.
Edit Configuration: configure editor, colour & fonts, user keywords, shortcut keys,
and text templates.
View-Symbol Window: list current debug symbols and debug information.
Project Components, Environment, and Books: manage source files, tool
environment, and documentation.
Project-Select Device: select the microcontroller device for the project.
63

Project-Options: configure the toolchain.
Debug-Breakpoints: manage execution, access, and conditional breakpoints.
Debug-Debug Settings: configure access traps for simulation.
Debug-Logic Analyzer: configure signal recording for the logic analyzer.
Debug-Memory Map: configure memory regions and memory access types.
Debug-Performance Analyzer: setup address ranges for statistic collection.
Debug-Function Editor: create debug functions or debugger .INI files.
Flash-Configure Flash Tools: configure the tools used for Flash programming.
Tools-Setup PC-Lint: configure Gimpel PC-Lint.
Tools-Customize Tools Menu: add external command-line tools.
SVCS-Configure Version Control: setup external Software Version Control System
6.5 COOCOX DEBUGGER

CoLinkEx is a hardware debugging adapter which supports SW debugging and
supports both ARM Cortex M3 and Cortex M0 devices, it supports debugging in
CooCox software and Keil Realview MDK.
Features:
Free
Supports Cortex M0 and Cortex M3 devices
Supports SW debugging
Supports CoFlash, CoIDE, MDK and IAR
Supports JTAG debugging
64
Requirements:
Hardware:
512MB memory
20MB Disk space
Operating Systems:
Windows XP / Windows Vista / Windows 7
Support Software
Keil RealView MDK v4.03 or higher
CooCox CoIDE v1.4.0 or higher
Support Series:
Atmel ATSAM3U Series
Energy Micro EFM32 Series
TI LM3S Series
Nuvoton Numicro Series
NXP LPC17xx LPC13xx LPC12xx LPC11xx Series
ST STM32F10x STM32F4x Series
Holtek HT32 Series
Connection Figure:
Preparation:
Before you use this development kit, you need to install CoLinkEx Driver first.
The CoLinkEx USB drivers are different according to the OS of your PC, please
visit http://www.coocox.org/Colinkex.html to download the right one and install it as
below: 1. Double Click the EXE file, enter the installation interface, click Next. The
CoLinkEx USB drivers are different according to the OS of your PC to download the
65

right one and install it as below
2. Select the installation location, click Next.
66

3.Click Install.
4. Click Finish.
After that, you can use it in MDK or CoIDE environment.

67
Configuration:
CooCox CoIDE
68

Keil Realview MDK
Before you use it in MDK, you need to download and install CoMDKPlugin first, please
visit http://www.coocox.org/CoLinkGuide/CoMDKPlugin.html to get the details. Just
install it with the following simple steps:
1. Double Click the EXE file, enter the installation interface, click Next.
2. Select the installation location, click Next.
69

3. Click Install.
4. Click Finish.
70

Now you need to do the following configurations while use it in MDK:
1. Debug -> Use of the configuration selects "CooCox Debugger
2. Click Settings, select "ColinkEx" for the Adapter
71
Multi-colored line following robot
6.6 HYPERTERMINAL
USING HYPERTERMINAL
Most Spectracom products have an RS-232 Com port to configure selectable

parameters and retrieve operational status and performance logs. Connect the
Spectracom RS-232 Com (Setup) port to a computer using a one to one pinned DB9
serial cable. This cable has a DB9 male on one end and a DB9 female on the other
end. Do not try to use a null modem cable with gender changers to get the correct
pin configuration. A null modem cable reverses transmit and receive lines and
therefore will not work in this application. To allow communication the computer
must be running a terminal emulation program such as HyperTerminal.
HyperTerminal is included with Windows 95/98/NT/ME/2000/XP computers. To
start a HyperTerminal session left click on the START button and follow the path of
Programs
HyperTerminal as shown in Figure 1.
NOTE:
The sample screen snapshots are from a Windows 2000 computer.

Screens may vary slightly on other versions of Windows.
Figure Starting HyperTerminal
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DEPT OF ECE, KGRCET
Double click on HyperTerminal. You will then be prompted to name the

HyperTerminal session and select an icon. Figure 2 shows an example session named
Spectracom.
Figure 2. New Connection Screen On the Connect To screen skip past the
Country/region, Area code and Phone number configuration selections. In the
Connect using box select the desired RS-232 port, COM 1 or COM 2 as shown in
Figure 3. Click on the OK box to continue.
Next you will be prompted to enter the port properties. Select 9600 baud, 8 data bits,
no parity, 1 stop bit and XON/XOFF flow control as shown in Figure 4. Click on the
OK box to continue.
FIGURE 4. Port Properties
The HyperTerminal Session is now ready for use. Enter the GPS Signal Status
command GSS<enter> , to view the satellites currently tracked by the GPS receiver.
Figure 5 shows a typical response from a Model 8195A GPS Disciplined Oscillator.
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DEPT OF ECE, KGRCET
FIGURE 5. Typical Configuration Response

When exiting HyperTerminal you will be given the option to save the session.
Select yes to save for future use. If there was no response from the GPS receiver try
the following:
1. Refresh the HyperTerminal port settings by clicking on CALL of the menu bar then
select Disconnect.
To enable HyperTerminal click on CALL again and this time select Call or
Connect.
2. Verify that a one to one pinned DB9 serial cable is used. The cable should have a
DB9 male on end and a DB9 female on the other. Do not use a cable having gender
changers to get the correct
connector combination. These cables are typically null modem cables and are
not pinned one to one as required and will have DB9 males on both ends of the cable.
The RS-232 cable requires a minimum 3 wires; RXD (pin 2), TXD (pin 3) and
Ground (pin 5).
3. Verify the serial port is operational. Simply shorting the RXD and TXD lines
together on the cable end that plugs into the receiver can do this. Using a small flat
bladed screwdriver short pin 2 to pin 3 while typing characters on the keyboard. If the
port is working you will see whatever you type.
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DEPT OF ECE, KGRCET
CHAPTER 7
RESULT
Fig: Working Kit with an LDR connected below the robot
RESULT ANALYSIS:
The main principal behind the working of this prototype is LDR.LDR gives
the output of variable resistance in Voltage which is then converted to digital values
by ADC in ARM board. Each colour has a unique voltage value in various light
condtions.This prototype is calibrated under different conditions.
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DEPT OF ECE, KGRCET
7.1 ADDVANTAGES
Can be used as robotic vehicles for warehousing
Defense applications
Cost effective
No external operating need
7.2 APPLICATIONS
Guidance system for industrial robots moving on shop floor etc.
Automobile industries
Used in home & industrial automation systems
Defense applications
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DEPT OF ECE, KGRCET
CONCLUSION
The project is aimed at providing complete automated robot which can operate
by itself and can move automatically.This is a prototype which can be implemented in
real time by using components such as logistics,industries,etc.Development can also
be made in the number of sensors incorporated in the robot
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DEPT OF ECE, KGRCET
FUTURE SCOPE
The CPU must merely poll the speech circuits recognition lines occasionally
to check if a command has been issued to the robot.We can even improve upon this
by connecting the recognition line to one of the robots CPU interrupt lines.In future
this can be developed by the use of camera with digital image processing techique so
that it can travel for a greater distance and can be fully automated.Various other
sensors like LDR sensor can be added or IR sensor for avoiding obstacles can also be
added.
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DEPT OF ECE, KGRCET
APPENDIX
CODING:
#include <lpc17xx.h>
void Delay_m(unsigned int x)
{
int k,l;
for(k=0;k<=x;k++)
for(l=0;l<=1500;l++);
}
void Delay(unsigned int x)
{
int y;
for(y=0;y<=x;y++);
}
void init_adc()
{
LPC_PINCON->PINSEL1=0x00550000; // in PINSEL1 we are usinng 17:16 AD0.1
with Function 01
LPC_SC->PCONP|=(1<<12); // in PCONP register we are using 12th bit PCADC
LPC_ADC->ADCR=0x00200B02; // in this AD 0.1 is SEL B==>5.5 Mhz PDN mode
}
unsigned char read_adc(unsigned char ch)
{
long val;
LPC_ADC->ADCR=0x00200B00|(1<<ch);
LPC_ADC->ADCR|=0x01000000;
Delay(150000);
while(!(LPC_ADC->ADGDR&0x80000000)); // ADCGDR 31-bit is DONE bit,this
loop executes untill conversion is completed
val=LPC_ADC->ADGDR;
val=(val>>4)&(0xfff);
return val;
}
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DEPT OF ECE, KGRCET
int main(void)
{
float a,b,c;
LPC_GPIO0->FIODIR=0x000000f0;
init_adc();
a = read_adc(1);
b = read_adc(2);
c = read_adc(3);
a = a*5;
b = b*5;
c = c*5;
while(1)
{
if(a<135 || (b>190 && b<210)|| c<135 ) //black detected at sensor 2
{
LPC_GPIO0->FIOSET = 0x000000A0; // straight
Delay_m(5000);
LPC_GPIO0->FIOCLR = 0x000000A0;
}
if((a>140 && a<160) || ((b>190 && b<210) || (b>140 && b<160))
&& c<130) //yellow detected
{
LPC_GPIO0->FIOSET = 0x00000020; // left
Delay_m(7000);
LPC_GPIO0->FIOCLR = 0x00000020;
}
if(a<135 && ((b>190 && b<210) || (b>140 && b<160)) || (a>140 &&
a<160)) //yellow detected
{
LPC_GPIO0->FIOSET = 0x00000080; // right
Delay_m(7000);
LPC_GPIO0->FIOCLR = 0x00000080;
}
}
}
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DEPT OF ECE, KGRCET
ADC PROGRAMMING
#include "lpc17xx.h"
#define en_high() LPC_GPIO0->FIOSET|=(1<<5)
#define en_low() LPC_GPIO0->FIOCLR|=(1<<5)
#define rs_dat() LPC_GPIO0->FIOSET|=(1<<6)
#define rs_cmd() LPC_GPIO0->FIOCLR|=(1<<6)
#define rw() LPC_GPIO0->FIOCLR|=(1<<7)
void lcd_cmd(unsigned char cmd);
void Delay(unsigned int x)
{
int y;
for(y=0;y<=x;y++);
}
void lcd_init()
{
lcd_cmd(0x28);
lcd_cmd(0x06);
lcd_cmd(0x0c);
lcd_cmd(0x02);
lcd_cmd(0x80);
lcd_cmd(0x01);
}
void lcd_dat(unsigned char dat)
{
rs_dat();
rw();
en_high();
LPC_GPIO1->FIOSET|=(((dat >>4)<<20));
LPC_GPIO1->FIOCLR=~(((dat >>4)<<20));
Delay(90);
en_low() ;
en_high();
LPC_GPIO1->FIOSET|=(((dat )<<20));
LPC_GPIO1->FIOCLR=~(((dat )<<20));
Delay(90);
en_low() ;
LPC_GPIO1->FIOCLR=0x0fffffff;
}
void lcd_cmd(unsigned char cmd)
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DEPT OF ECE, KGRCET

{
rs_cmd();
rw();
en_high();
LPC_GPIO1->FIOSET|=(((cmd >>4)<<20));
LPC_GPIO1->FIOCLR=~(((cmd >>4)<<20));
Delay(90);
en_low() ;
en_high();
LPC_GPIO1->FIOSET|=(((cmd )<<20));
LPC_GPIO1->FIOCLR=~(((cmd )<<20));
Delay(90);
en_low() ;
}
void init_adc()
{
LPC_PINCON->PINSEL1=0x00010000; // in PINSEL1 we are usinng 17:16 AD0.1
with Function 01
LPC_SC->PCONP|=(1<<12); // in PCONP register we are using 12th bit PCADC
LPC_ADC->ADCR=0x00200B02; // in this AD 0.1 is SEL B==>5.5 Mhz PDN mode
}
unsigned char read_adc(unsigned char ch)
{
long val;
LPC_ADC->ADCR=0x00200B00|(1<<ch);
LPC_ADC->ADCR|=0x01000000;
Delay(150000);
while(!(LPC_ADC->ADGDR&0x80000000)); // ADCGDR 31-bit is DONE bit,this
loop executes untill conversion is completed
val=LPC_ADC->ADGDR;
val=(val>>4)&(0xfff);
return val;
}
void lcd_int(unsigned int num)
{
char str[5]={0,0,0,0,0};
int i=4,j=0;
while(num)
{
str[i]=num%10;
num=num/10;
i--;
}
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DEPT OF ECE, KGRCET

for(i=j;i<5;i++)
{
lcd_dat(48+str[i]);
}
}
void lcd_str(unsigned char *r)

{
while(*r)
{
lcd_dat(*r++);
}
}
int main(void)
{
unsigned char x;
LPC_GPIO0->FIODIR=0xffffffff;
lcd_cmd(0x80);
lcd_str("hai");
Delay(1000000);
lcd_cmd(0x01);
lcd_init();
init_adc();
while(1)
{
x=read_adc(1);
lcd_cmd(0xc0);
lcd_int(x);
}
}
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DEPT OF ECE, KGRCET
LCD Programming:
#include"LPC17xx.h"
#define en_high() LPC_GPIO0->FIOSET=0X00000004
#define en_low() LPC_GPIO0->FIOCLR=0X00000004
#define rs_dat() LPC_GPIO0->FIOSET=0X00000001
#define rs_cmd() LPC_GPIO0->FIOCLR=0X00000001
#define rw() LPC_GPIO0->FIOCLR=0X00000002
void lcd_cmd(unsigned char cmd);
void delay(unsigned int x)
{
int y;
for(y=0;y<=x;y++);
}
void lcd_init()
{
lcd_cmd(0X28);
lcd_cmd(0X06);
lcd_cmd(0X0C);
lcd_cmd(0X02);
lcd_cmd(0X80);
lcd_cmd(0X01);
}
void lcd_dat(unsigned char dat)
{
rs_dat();
rw();
en_high();
LPC_GPIO1->FIOSET=((dat>>4)<<20);
delay(100000);
en_low();
LPC_GPIO1->FIOCLR=0X0FFFFFFF;
}
void lcd_cmd(unsigned char cmd)
{
rs_cmd();
rw();
en_high();
LPC_GPIO1->FIOSET=(cmd<<20);
delay(100000);
en_low();
LPC_GPIO1->FIOCLR=0X0FFFFFFF;
}
void lcd_str(unsigned char *r)
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DEPT OF ECE, KGRCET

{
while(*r)
{
lcd_dat(*r);
r++;
}
}
int main (void)
{
LPC_GPIO0->FIODIR=0XFFFFFFFF;
LPC_GPIO1->FIODIR=0XFFFFFFFF;
lcd_init();
while(1)
{
lcd_cmd(0x80);
lcd_str("sammy");
}
}
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DEPT OF ECE, KGRCET
Wheels Programming:
#include<lpc17xx.h>
int main (void)
{
LPC_GPIO0->FIODIR=0XFFFFFF0F;
LPC_PINCON->PINMODE0=0x00000c00;
while (1)
{
if((LPC_GPIO0->FIOPIN0&0X00000020)==(0X00000020))
{
LPC_GPIO0->FIOSET=0X00000001;
}
else
{
LPC_GPIO0->FIOCLR=0X00000001;
}
}
}
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DEPT OF ECE, KGRCET
Alternate Wheel Drive Programm:

#include<LPC17xx.h>
void delay_ms(unsigned int);
int main (void)
{
while(1)
{
LPC_GPIO0->FIOSET=0xffffffff;
delay_ms(5);
LPC_GPIO0->FIOCLR=0xffffffff;
delay_ms(5);
}
}
void delay_ms(unsigned int ms)
{
unsigned int i,j;
for(i=0;i<ms;i++)
for(j=0;j<120000;j++);
}
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DEPT OF ECE, KGRCET
Switch:
#include<LPC17xx.h>
void main()
{
if((LPC_FIOPIN0 & 0X00000020)==00000000)
{
LPC_GPIO0->FIOSET=0X00000001;
else
}
}
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DEPT OF ECE, KGRCET
Keyboard config:
#include<LPC17xx.h>
void main()
{
if((LPC_FIOPIN0 & 0X00000020)==00000000)
{
LPC_GPIO->FIOSET=0X00000001;
else
}
}
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DEPT OF ECE, KGRCET
REFERRENCES
1.The 8051 microcontroller-Kenneth Ayala,3rd reprint,2005;Thomson
2.Asia Ltd.,Singapore; Chapter 3,6,7&8. For programming 89S51
3.ARM7TDMI datasheet
4.L293D motor driver IC datasheet.
5.The ARM Cortex-M3 processor datasheet.
6.LPC1769/68/67/66/65/64/63
http://www.arm.com
http://www.lpc2000.com
www.nxp.com
90
DEPT OF ECE, KGRCET

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Multi-Colour Line following Robot

DEPARTMENT OF ECE, KGRCET

Multi-Colour Line following Robot

DEPARTMENT OF ECE, KGRCET

Multi-Colour Line following Robot

DEPARTMENT OF ECE, KGRCET

Multi-Colour Line following Robot

Processors are classified into four types like:

Micro Processor (p)

Micro controller (c)

Digital Signal Processor (DSP)

DEPARTMENT OF ECE, KGRCET

Multi-Colour Line following Robot

Application Specific Integrated Circuits (ASIC)

Micro Processor (p):

Bandwidth : The number of bits processed in a single instruction.

instructions per second the processor can execute.

Fig: 2.2 elements of microprocessor

DEPARTMENT OF ECE, KGRCET

Multi-Colour Line following Robot

Timer, Counter, serial

Digital Signal Processors (DSPs):

CPU cores for computation and control

Peripherals to control timing critical functions

Memories to store data and program

I/Os to connect to external components like LEDs, memories, monitors etc.

Computer Instruction Set

Reduced Instruction Set Computer (RISC)

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Fig: 3.1 Block diagram describing connections line following robot

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4.2 The History of ARM

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4.3 Migration from the ARM7 processor family for better

Table 4.1 ARM7TDMI-S and Cortex-M3 comparison (100MHz frequency on TSMC

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4.4 ARM and Thumb Performance

4.5 The Thumb-2 instruction set

ARM instructions are a fixed length of 32 bits

Thumb instructions are a fixed length of 16 bits

Thumb-2 instructions can be either 16-bit or 32-bit

Thumb-2 gives approximately 26%

improvement in code density over ARM

Thumb-2 gives approximately 25% improvement in performance over Thumb

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4.6 Pipeline Organization

allows higher clock frequency

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4.7 Operating Modes

User mode: The only non-privileged mode.

4.8 ARM Registers

R13 is also referred to as SP, the Stack Pointer.

R14 is also referred to as LR, the Link Register.

R15 is also referred to as PC, the Program Counter.