EE505 Final Project: A 6-bit Flash ADC

Andy Burkland, Karl Peterson, Yanheng Zhang

Top Level Schematic

Comparator Architecture Selection

Two potential architectures considered

Uyttenhove et al. (JSSC July 2003)

Yukawa (JSSC June 1985)

Track and Latch Comparator

Comparator Architecture Selection

Yukawa (JSSC June 1985)

Comparator Architecture Selection

Uyttenhove et al. (JSSC July 2003)

Preamp Architecture Selection

Criteria for selection of preamp architecture

Preamp unity gain bandwidth

Common-mode input and output
DC gain
Suitability for target technology

Preamp Architecture Selection

Maximum speed of operation

Need to maximize unity gain bandwidth of preamp to

achieve maximum dynamic gain

Therefore, maximize gm and minimize capacitance

Preamp Architecture Selection

Preamp Common-Mode Considerations

Lower common-mode input is 12mV

Upper common-mode input is 1.6mV
Must have common-mode output compatible with latch-stage

Preamp Architecture Selection

Selected Preamp Architecture of Uyttenhove

(with PMOS inputs)

Resistors offer lower capacitance

Resistors offer design flexibility for common-mode input

design

Takes advantage of poly resistors available in process

Yukawa employed NMOS transistors with lower Vth than used for
logic

Flipped Uyttenhove architecture from NMOS input to PMOS

for common-mode input considerations

Using PMOS input lowers gm of preamp

Latch Circuit Architectural

Considerations

...

(Uyttenhove, 2003) features

a different latch reset
mechanism
Other structures pre-charge
internal nodes to VDD or
GND
In this structure, internal
nodes are pre-charged to an
intermediate value
The required V during the
latch phase is smaller

LATCH

...

Latch Circuit Architectural

Considerations

This settles to the inverter

threshold voltage

...

During track phase, latch is

resetting and the differential
nodes are essentially
shorted (more on this later)
Rearranged, the circuit looks
like this:

LATCH

...

Preamp Schematic
Common-mode
input range
12mV to 1.6V

Maximize gm using
allowed tail current

Resistors set DC
gain and CMR

Common-mode
output cant be too
low for latch stage

Preamp DC Performance Characterization

Preamp AC Performance Characterization

Preamp Noise Performance Characterization

Reference Ladder

Resistor Ladder Sizing

Used for initial resistor sizing
Resistors further adjusted during full-chip simulations
Unit R = 1.5 ohms (96 ohm ladder - 16 mA ladder
current)

Latch Circuit Implementation

Latch Circuit Sizing & Bias Details

P0 provides 120 A to
input diff-pair
VDSAT is 286 mV
With ICM = 1.25V,
VDS - VDSAT in tracking
mode is 261 mV
When the common mode
is 400 mV, VDS - VDSAT is
increased to a 952 mV.

Latch Circuit Sizing & Bias Details

Diff pair is sized to

balance transconductance
and gate capacitance at
Also affect Vo at latch
nodes right before latching
We decided on a
minimum Vo of 5 mV
(based on thermal noise &
predicted mismatch)
Cg of100 fF was targeted
Overdrive voltage of 125
mV and a gm of 800 S.

Latch Circuit Sizing & Bias Details

Saturation condition of
the input pair is easily met
for large common-mode
voltages at output of the
pre-amp
Difficult for low CM
At 400 mV (which is the
expected minimum from
the preamp),VDS - VDSAT is
192 mV

Latch Circuit Sizing & Bias Details

Switches N5, N4 and N6

are implemented as n-type
devices for lower rdson
N5 and N4 block kickback
Sizing is a tradeoff
between switch resistance
and charge injection
These switches play a part
in determining the drain
voltage of the input-pair
saturation of input pair

On-resistance of 595
and CGD of 4.7 fF.

Latch Circuit Sizing & Bias Details

N6 probably the most

difficult device to size
Contributes to charge
injection (want smaller)
Switch on-resistance
determines reset time
constant (want bigger)
Has a part in determining
Vo right before latching
(want smaller)

The on-resistance with

the size shown is 580
and CGD is 5.2 fF.

Latch Circuit Sizing & Bias Details

Inverter sizing does not

change latch time constant
much (Johns & Martin)
However, during reset, the
time constant is the onresistance of N6 and the
latch node capacitances
Bigger devices = more
dynamic power cons. But
better immunity to charge
injection

Latch Circuit Sizing & Bias Details

Ratio between p-type and

n-type devices determines
threshold value
This effects saturation of
input pair need to make
widths of N1 and N2
larger compared to the
widths of P5 and P6
But this results in
asymmetric latching times
and larger maximum
voltage swings

Latch Circuit Sizing & Bias Details

Inverters of the latch were

characterized in open
loop:

Latch Circuit Sizing & Bias Details

Output buffer: make it

small, because it loads the
latch
Threshold voltage may
also be of interest, but
was not found to be super
important in our design

Latch Circuit Characterization

Transient sim for 3 differential inputs (6 mV comparator input with

pre-amp gain of by 8 dB, 14 dB, 20 dB, and 26 dB)

Latch Circuit Characterization

Latch settling time as a function of differential input voltage (V)

Latch Circuit Characterization

Transient sim showing buffered output

Design of decoder

Decoder design

The performance of Flash ADC is affected by choice of

decoder
The evaluation is based on ease of design and speed

Available architectures

Ones-Counter
Multiplexer based
ROM based
Direct Logic

Ones-Counter Decoder

E. Sall and M.Vesterbacka Comparison of Two Thermometer-to-Binary

Decoders for High-Performance Flash ADC
Pros: Decoder depends on ADCs speed, wont be a limiting factor
Cons: Hard to implement

Multiplexer based Decoder

Pros: Easy for implementation, Consists only of multiplexers

Cons: Critical Path limits the speed of decoder (x0)

Implementation of Multiplexer based Decoder

We have implemented this architecture, but it fails at 800MHz simulation

ROM-based Decoder

K. Uyttenhove and M. S. Steyaert A 1.8-V 6-Bit 1.3-GHz Flash ADC in

0.25-um CMOS
Each row is one bit with bubble error correction logic
Each column is the output bit
If output bit should be 0 for certain input, we add transistor at the
crossing point to bring to 0.
Two coding schemes: Binary coding or Gray coding

Logic based Decoder

Direct Logic

Separate the bubble error logic and decoder logic

Use 6 32-OR gate, each OR gate is the corresponding output
bit
Easy for implementation
Achieves reasonably good performance

Bubble-Error correction Logic

Decoder Logic

32-OR gate

TestBench

Simulation Results with 1GHz Clock

Full ADC Results

Partial results (Still working on it now)

Working frequency of ADC: 500MHz

FFTCoherent Sampling

Characterizing : THD, SNR SFDR, SFDR

4093 bin

Characters
THD

-49.07

SFDR

49.07

SNR

27.92

SNDR

27.89

Frequency

125.30MHz

Project Challenges and Issues

Cadence simulations of final design were taking 10 to 13

hours each

Performance not yet what was expected based on

performance of individual blocks