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Practice 2: The Current Mirror

[Prolog] So far we have used resistors and voltage divisions for amplifier biasing. But
this method only works for circuits with discrete components. Because both the resistor
and the coupling capacitor needed for such biasing occupy excessive areas, this method is
not suitable for IC circuit design and fabrication. Amplifier biasing in IC circuits mostly
employs directly coupled biasing and constant current sources. Current mirror is one
type of active current source, possessing high internal resistance; and the transistors used
by the current mirror must operate within the linear (i.e. amplification) region. In terms
of applications, current mirror is a core technology for providing linear IC circuits with
biasing for direct coupled amplification stages it can provide biased fixed current to the
amplifier transistors. If we use current mirror as an active load, then its high internal
resistance can enable the amplifier to achieve very large voltage gains.
Constant Current Source
The constant current source is a basic element in circuit design. An ideal constant current
source has an infinitely large internal resistance (Ro), as shown below on the left. In
practice, the constant current source equivalent circuit is as shown on the right, which
includes both a constant current source for DC biasing (I), and an AC internal resistance
(Ro). As you can expect, all the transistors in the current mirror must operate within their
linear regions for the purpose of amplification. For BJT, this means the Active Region.
For FET, this means the Saturation Region.

1. Basic BJT constant current source (NPN or PNP)

(a) resistor biasing-NPN (b) equivalent circuit

(c) resistor biasing-PNP

(d) diode biasing-NPN

(e) diode biasing-PNP

For example, in (b) which is equivalent to (a), if * RE >> RB, then the voltage drop
across RB is negligible. Then IO = IC IE = (VBB VBE) / RE, where VBE = VBIAS. There
is one drawback, however, in that this circuit is affected by the supply voltage VBB, and
that the circuit does not have a large enough internal resistance.
Whereas in (d) and (e) with diode biasing, typically IO = IC IE = (N * VD VBE) / RE.
2. Bootstrap (power-supply independent) current source
(1) As shown below, this is probably the simplest high-internal-impedance current
source. IR2 = VEB / R2. If we choose R2 such that IR2 >> IB, then IO IR2 thus we have a
constant current. The BJT here is an emitter follower, thus RO . (Why?)

(2) On the other hand, if we connect the BJTs base and collector, then VEC can be used
as a constant voltage source. This is also called VBE multiplier and is often seen in
classes A and B power amplification biasing. In this case VEC = (1+R3/R2) VEB. (Why?)

3. Bootstrap active feedback current source

(1) As shown in (a), the emitter couplers E is connected to an inverter and is fed back to
the Base. The actual circuit is shown in (b). (b) is a simplified version of the well-known
Wilson current mirror, shown in (c), which contains active negative feedback.




Here in (b) we have IO = VBE / R2.

(2) This type of circuits often is used as current limiters, because the current is not
affected by changes in the supply voltage.
4. A constant current source using diodes

IO = VBE / R2
RO = rO

5. A constant current source using an op-amp

RO = A rO
Principles of Current Mirror
Current mirror is a type of current source capable of replicating current. Load currents
(IL) provided through current mirrors essentially do not depend on the load, but are only
proportional to the reference current (IREF), i.e. ILK = KIREF. IREF can be adjusted using
an independent resistor R. Current mirrors must use transistors whose properties match
their own properties. All transistors inside a current mirror have to work in their
operational regions. For BJT its the active region; and for FET its the saturation region,
where the base/gate current/voltage is used to control the amplified current/voltage.
BJT in active region: ICE = IS eV

/V T


ICE1/ICE2 = (IS1/IS2) (eV

When Q1 is the same as Q2: ICE1/ICE2 = e (V

/V T


/ eV

/V T




When biasing is the same: ICE1/ICE2 = IS1/IS2 if Q1 = Q2 then ICE1 = ICE2

FET in saturation region: IDS = K(VGS VT)2
IDS1/IDS2 = (K1/K2)((VGS1 VT)/(VGS2 VT))2
When FET1 is the same as FET2: Sqrt (IDS1/IDS2) = (VGS1 VT)/(VGS2 VT)
When biasing is the same: IDS1/IDS2 = K1/K2 if FET1 = FET2 then IDS1 = IDS2
Alpha () and Beta () are vendor-provided parameters related to a BJTs efficiency, i.e.
the proportion of electrons able to cross the base and reach the collector.
Typically, F and F (the F stands for forward) are defined as follows:

F = F / (1 F) F = F / (F + 1) since IE = IB + IC for active mode NPN/PNP.
Basic Current Mirror Circuit

Note: Q1 and Q2 should have large enough and similar values. Both Q1 and Q2 must
be working in the forward active region.
Example: VCC = 12 V, IREF = 2 mA. Assume we use 2SC1815.
RREF = (VCC 0.7) / IREF = 5.65 K.
Since Q2 must work in the active region, we have:
VCE2 = VC2 = VCC IL RL 0.3 V RL (VCC 0.3) / IREF = RL(max)
Current Mirror Variations
1. Current replication

2. Current repeater

3. Current mirror with current gain

4. Wilson current mirror

Current Mirror Analysis

Consider the basic BJT current mirror below:

If we also take into account , then the following circuit shows the analysis:

The above figure shows a more realistic current analysis considering the effect of .
Ideally IO = IREF. But with , we write a nodal current equation at the collector of Q1 to
get IREF = IC + 2IC/ = IC(1+2/), since IB = IC/ for both Q1 and Q2. Because IO = IC, we
hence obtain IO/IREF = 1/(1+2/). Furthermore, if IO = m IREF = due to Q2 = m Q1 (area),
then IO/IREF = m / (1+(m+1)/ ).
The following figure shows an N-output current mirror, with all the transistors matched,
finite , and ignoring the effect of finite output resistance RO, we get:
I1 = I2 = = IN = IREF / (1 + (N+1)/)

In fact, we can mirror currents at different levels by having multiple mirror circuits.
See the circuit below as an example. Here IREF is generated in the branch consisting of
Q1 (diode-connected a.k.a. BC-shorted), R and Q2 (also diode-connected). Thus,
Now, assume all transistors have high = IC/IB. This means the base currents are
negligible. We also neglect the Early effect. Then, Q1 & Q3 form a current mirror Q3
supplies I1 = IREF. Q3 can supply this current to any load as long as its collector voltage is
VCC 0.3V; otherwise Q3 will be in saturation (i.e. not active).
Q5 & Q6, each matched to Q1, are connected in parallel. The Q5-Q6 pair along with Q1
form another current mirror, producing I3 = 2IREF. The parallel configuration of Q5 & Q6
is equivalent to a transistor with an EBJ area 2X that of Q1.
Q4 & Q2 form another mirror; thus I2 = IREF.
I4 = 3IREF, is generated by connecting Q7, Q8, Q9 (all matched to Q2) in parallel. The Q7Q8-Q9 group combined with Q2 to form another mirror. This is equivalent to using a
transistor with a 3X EBJ area.
BTW, Early voltage is measures as follows. Even when a FET is in saturation, Ids is
actually in proportion to Vds and can increase. If we plot the I-V curves for several Vgs,
all these curves will intersect the x-axis at one point. That points value is Early voltage.
Similar to the MOS current mirrors, we can also derive the output resistance RO for the
BJT mirror:
RO = VO/IO = rO2 = VA2/IO, where VA2 is the Early voltage of Q2.
IO, the output current, will only equal IREF when Q2 has the same VCE as Q1, i.e. when VO
= VBE. As soon as VO increases, IO will also increase.

If we consider both and RO, which have finite values (non-ideal), then:
IO = IREF (m / (1+(m+1)/))(1+(VO-VBE)/VA2)
For MOS mirrors, we have:
IO = IREF ((W/L)2/(W/L)1)( 1+(VO-VGS)/VA2)
Dont they look similar?
The following figure shows a simple BJT current source, done in a similar way to the
MOS mirror. Here we have:
IREF = (VCC - VBE) / R
IO = IREF (1 / (1+2/))(1+(VO-VBE)/VA)

We will consider the Wilson current mirror, a slightly modified version of the basic BJT
current mirror. 2 types of analyses can be performed on the Wilson mirror. The first is to
determine the current transfer ratio (left). The second is to determine the output
resistance (right).

The question for (a) above is how do we get IB for Q3? This is because all the Qs are
matched, i.e. identical, and we have = IC/IE = /(+1) and = IC/IB. Hence
(IC/IB)/(+1) = IC/IE. 1/(IB(+1)) = 1/IE IE = IB(+1). However, since IE is also
equal to IC(1+2/), we finally arrive at IB for Q3 as IB = (IC(1+2/))/(+1).
(a) shows the circuit analysis of the Wilson current mirror for reducing dependence and
increasing output resistance. From (a) we see that IO/IREF = 1 / (1 + 2/((+2))) which is
approximately 1 / (1+2/2). Note that we assume Q1 and Q2 to have the same collector
current IC.
(b) shows the analysis to determine the output resistance RO. This is done by setting IREF
= 0 and then apply a test voltage vx to the output node, i.e. the collector of Q3. The
purpose here is to find current ix such that RO = vx/ix. ix = i1 + i2, using Q3 as a super
node, and Q1-Q2 is a current mirror, forcing i2 i1 = ix/2. So, how will we write a nodal
current equation at the collector of Q3?
Now lets take a look at the MOS circuits. The figure below shows a simple MOS
constant-current source. Here Q1s drain is connected (shorted) to its own gate. This is
called diode connected. This forces Q1 to be in the saturation region, thus:
ID1 = (1/2)Kn(W/L)1(VGS-Vtn)2

(Eq. 1)

Note that we neglect the channel-length modulation. Thus ID1 = IREF = (VDD VGS)/R,
and we can determine the value for R using this equality.
Now, for Q2, if we assume Q2 is also in saturation, then:

IO = ID2 = (1/2)Kn(W/L)2(VGS-Vtn)2

(Eq. 2)

Here we also neglect channel-length modulation.

From (Eq. 1) and (Eq. 2), we obtain: IO/IREF = (W/L)2/(W/L)1. If IO/IREF = 1 then we have
a current mirror. Also, because Q2 must operate in saturation, VO must be > VGS Vtn.

The right figure above shows a current mirror, where VO is usually a few tenths of a volt.
The I-V curve below shows the effect VO has on IO, when Q2 is matched to Q1. In this
curve, VOV, i.e. the overdrive voltage, is = VGS Vtn. As long as VO is kept at VGS, IO
will be equal to IREF, because at this point both Q1 and Q2 have the same VDS. But if VO
keeps increasing, then IO will also increase at a rate of VO/IO = rO2, the incremental
output resistance measured at Q2. RO, the output resistance, is defined to be VO/IO =
rO2 = VA2/IO, where VA2 is the Early voltage of Q2, in proportion to the channel length.
Given this, IO can be expressed as
IO = (W/L)2/(W/L)1 IREF (1 + (VO VGS)/VA2)

As a comparison, the following figure shows the MOS version of the Wilson mirror,
where (a) shows the circuit, (b) is the analysis to determine output resistance, and (c) is a
modified circuit for improved current transfer ratio.

The following is the Widlar current source (or mirror), which is the basic mirror with a
resistor RE connected to the emitter of Q2. Can you perform a current analysis on this
Widlar mirror similar to what we did for the basic BJT mirror?

Likewise, we can perform similar yet different current analysis on the basic MOS mirror:

The following is a list of useful equations for MOS current mirrors:

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