Advanced Information: 4GS Active Matrix EPD 128 X 180 Display Driver With Controller

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1606
Advanced information
4GS Active Matrix EPD 128 x 180
Display Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change
without notice.
http://www.solomon-systech.com
SSD1606
Rev 1.1
P 1/56
Oct 2011
Copyright 2011 Solomon Systech Limited
Appendix: IC Revision history of SSD1606 Specification

Revision
1.0
1.1
SSD1606
Change Items
Advanced information Release
Change ordering information
Rev 1.1
P 2/56
Oct 2011
Effective Date
11-May-11
17-Oct-11
Solomon Systech
CONTENTS
1
GENERAL DESCRIPTION ....................................................................................................... 5
FEATURES................................................................................................................................... 5
ORDERING INFORMATION ................................................................................................... 6
BLOCK DIAGRAM .................................................................................................................... 6
DIE PAD FLOOR PLAN ............................................................................................................ 7
PIN DESCRIPTION .................................................................................................................. 10
FUNCTIONAL BLOCK DESCRIPTION............................................................................... 14

7.1
MCU INTERFACE .................................................................................................................................................14
7.1.1
MCU Interface selection .............................................................................................................................14
7.1.2
MCU Parallel 6800-series Interface...........................................................................................................14
7.1.3
MCU Parallel 8080-series Interface...........................................................................................................15
7.1.4
MCU Serial Interface (4-wire SPI) .............................................................................................................17
7.1.5
MCU Serial Interface (3-wire SPI) .............................................................................................................18
7.2
RAM ...................................................................................................................................................................19
7.3
OSCILLATOR....................................................................................................................................................19
7.4
BOOSTER & REGULATOR .....................................................................................................................................19
7.5
PANEL DRIVING WAVEFORM ...............................................................................................................................21
7.6
VCOM FUNCTIONAL ...........................................................................................................................................21
7.6.1
VCOM regulation........................................................................................................................................21
7.6.2
VCOM Sensing............................................................................................................................................21
7.7
GATE AND PROGRAMMABLE SOURCE WAVEFORM ..............................................................................................22
7.8
WAVEFORM LOOK UP TABLE (LUT)...................................................................................................................23
7.9
OTP.....................................................................................................................................................................23
7.10 TEMPERATURE SEARCHING MECHANISM ............................................................................................................25
7.11 EXTERNAL TEMPERATURE SENSOR I2C SINGLE MASTER INTERFACE .................................................................26
COMMAND TABLE ................................................................................................................. 27
COMMAND DESCRIPTION................................................................................................... 38
9.1
FUNDAMENTAL COMMAND DESCRIPTION.............................................................................................................38
9.1.1
Driver Output Control (01h).......................................................................................................................38
9.1.2
Gate Scan Start Position (0Fh) ...................................................................................................................40
9.1.3
Data Entry Mode Setting (11h) ...................................................................................................................40
9.1.4
Set RAM X - Address Start / End Position (44h).........................................................................................42
9.1.5
Set RAM Y - Address Start / End Position (45h) .........................................................................................42
9.1.6
Reserve (46-4Dh) ........................................................................................................................................42
9.1.7
Set RAM Address Counter (4Eh-4Fh).........................................................................................................42
10
TYPICAL OPERATING SEQUENCE ................................................................................ 43
10.1
10.2
10.3
NORMAL DISPLAY ...............................................................................................................................................43

VCOM OTP PROGRAM .......................................................................................................................................44
WS OTP PROGRAM .............................................................................................................................................45
11
ABSOLUTE MAXIMUM RATING ..................................................................................... 46
12
ELECTRICAL CHARACTERISTICS ................................................................................ 46
13
AC CHARACTERISTICS..................................................................................................... 49
SSD1606
Rev 1.1
P 3/56
Oct 2011
Solomon Systech
INTERFACE TIMING ..............................................................................................................................................50
13.1
14
APPLICATION....................................................................................................................... 53
TABLES
TABLE 3-1 : ORDERING INFORMATION .................................................................................................................................6
TABLE 5-1 : SSD1606Z0 BUMP DIE PAD COORDINATES ..................................................................................................8
TABLE 6-1 : BUS INTERFACE SELECTION ...........................................................................................................................11
TABLE 7-1 : MCU INTERFACE ASSIGNMENT UNDER DIFFERENT BUS INTERFACE MODE ...................................................14
TABLE 7-2 : CONTROL PINS OF 6800 INTERFACE ..............................................................................................................14
TABLE 7-3 : CONTROL PINS OF 8080 INTERFACE (FORM 1) .............................................................................................16
TABLE 7-4 : CONTROL PINS OF 8080 INTERFACE (FORM 2) .............................................................................................16
TABLE 7-5 : CONTROL PINS OF SERIAL INTERFACE ...........................................................................................................17
TABLE 7-6 : CONTROL PINS OF 3-WIRE SERIAL INTERFACE ..............................................................................................18
TABLE 7-7 : RAM ADDRESS MAP .......................................................................................................................................19
TABLE 8-1: COMMAND TABLE ............................................................................................................................................27
TABLE 11-1: MAXIMUM RATINGS .......................................................................................................................................46
TABLE 12-1: DC CHARACTERISTICS..................................................................................................................................46
TABLE 12-2: REGULATORS CHARACTERISTICS .................................................................................................................48
TABLE 13-1: AC CHARACTERISTICS ..................................................................................................................................49
TABLE 13-2 : 6800-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS .....................................................50
TABLE 13-3 : 8080-SERIES MCU PARALLEL INTERFACE TIMING CHARACTERISTICS .....................................................51
TABLE 13-4 : SERIAL INTERFACE TIMING CHARACTERISTICS ...........................................................................................52
TABLE 14-1 : REFERENCE COMPONENT VALUE ................................................................................................................55
FIGURES
FIGURE 4-1 : SSD1606 BLOCK DIAGRAM ...........................................................................................................................6
FIGURE 5-1 - SSD1606Z0 DIE FLOOR PLAN (BUMP FACE UP)..........................................................................................7
FIGURE 7-1 : DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ.....................................................................15
FIGURE 7-2 : EXAMPLE OF WRITE PROCEDURE IN 8080 PARALLEL INTERFACE MODE ....................................................15
FIGURE 7-3 : EXAMPLE OF READ PROCEDURE IN 8080 PARALLEL INTERFACE MODE ......................................................15
FIGURE 7-4 : DISPLAY DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ ......................................................16
FIGURE 7-5 : W RITE PROCEDURE IN SPI MODE ................................................................................................................17
FIGURE 7-6 : W RITE PROCEDURE IN 3-WIRE SERIAL INTERFACE MODE ...........................................................................18
FIGURE 7-7 : INPUT AND OUTPUT VOLTAGE RELATION CHART ..........................................................................................20
FIGURE 7-8 : VPIXEL DEFINITION .......................................................................................................................................21
FIGURE 7-9 : THE RELATION OF VPIXEL W AVEFORM WITH GATE AND SOURCE ..............................................................21
FIGURE 7-10 : PROGRAMMABLE SOURCE AND GATE WAVEFORM ILLUSTRATION ............................................................22
FIGURE 7-11 : VS[N-XY] AND TP[N] MAPPING IN LUT......................................................................................................23
FIGURE 7-12 : OTP CONTENT AND ADDRESS MAPPING ..................................................................................................24
FIGURE 7-13 : W AVEFORM SETTING AND TEMPERATURE RANGE # MAPPING .................................................................25
FIGURE 9-1: OUTPUT PIN ASSIGNMENT ON DIFFERENT SCAN MODE SETTING.................................................................39
FIGURE 9-2: EXAMPLE OF SET DISPLAY START LINE WITH NO REMAPPING ....................................................................40
FIGURE 13-1 : 6800-SERIES MCU PARALLEL INTERFACE CHARACTERISTICS..................................................................50
FIGURE 13-2 : 8080-SERIES PARALLEL INTERFACE CHARACTERISTICS (FORM 1) ...........................................................51
FIGURE 13-3 : 8080-SERIES PARALLEL INTERFACE CHARACTERISTICS (FORM 2) ...........................................................51
FIGURE 13-4 : SERIAL INTERFACE CHARACTERISTICS ......................................................................................................52
FIGURE 14-1 : BOOSTER CONNECTION DIAGRAM .............................................................................................................53
FIGURE 14-2 : TYPICAL APPLICATION DIAGRAM WITH SPI INTERFACE..............................................................................54
SSD1606
Rev 1.1
P 4/56
Oct 2011
Solomon Systech
GENERAL DESCRIPTION
SSD1606 is a CMOS active matrix bistable display driver with controller. It consists of 128
source outputs plus 180 gate outputs, 1 VCOM and 1 VBD for border that can support a
maximum display resolution 128x180.
SSD1606 embeds booster, regulators and oscillator. Data/Commands are sent from general
MCU through the hardware selectable 6800-/8080-series compatible Parallel Interface or Serial
Peripheral Interface.
FEATURES
Design for dot matrix type active matrix EPD display

Resolution: 128 source outputs; 180 gate outputs; 1 VCOM; 1VBD for border
Power supply
z
VCI:
2.4 to 3.3V
z
VDDIO: Connect to VCI
z
VDD:
1.8V, regulate from VCI supply
Gate driving output voltage:

2 levels output (VGH, VGL)
Max 42Vp-p
VGH: 15V to 22V;
VGL: -20V to -15V
Voltage adjustment in steps of 500mV.
Source / VBD driving output voltage:

3 levels output (VSH, VSS, VSL)
VSH: 10V to 17V
VSL: -10V to -17V
Voltage adjustment in steps of 500mV
VCOM output voltage

-4V to 0.2V in 20mV resolution
8 bits Non-volatile memory (OTP) for VCOM adjustment
Source and gate scan direction control

Low current deep sleep mode
On chip display RAM of 11520 bytes [(128x180) x 2 x 2 / 8] with double display buffer
11 set of waveform settings can be programmed and stored in On-chip OTP
Programmable output waveform allowing flexibility for different applications / environments.
Built in VCOM sensing
8-bits Parallel (6800 & 8080), Serial peripheral interface available
On-chip oscillator.
On-chip booster and regulator control for generating VCOM, Gate and Source driving
voltage.
I2C Single Master Interface to read external temperature sensor reading
Available in COG package, IC thickness 250um
SSD1606
Rev 1.1
P 5/56
Oct 2011
Solomon Systech
ORDERING INFORMATION
Table 3-1 : Ordering Information
Ordering Part Number

SSD1606Z0
Package Form
Gold bump die
BLOCK DIAGRAM
VCOM
VBD
VCOM
128 Source Buffer
VBD
180 Gate Buffer
S1
S0
S127
S126
G1
G0
G179
G178
Figure 4-1 : SSD1606 Block Diagram
GDR
RESE
FB
PREVGH
PREVGL
VGH
VGL
VSH
VSL
VCI/AVCI/
VCIBG
VDD
EX TVDD
Waveform
Selection
Booster
&
Regulator
VCOM
OTP
VPP
Waveform
Setting
[WS]
LUT
LOGIC
Temperature
Range [TR]
VDD
Regulator
I2C MASTER
CLS
MCU Interface
Mode
Selection
BUSY
D7
D6
D5
D4
D3
D2
D1
D0
CS#
D/C#
E
R/W#
RES#
BS[2:0]
CL
Rev 1.1
TSCL,
TSDA
RAM
Oscillator
SSD1606
VCOM
Control
P 6/56
Oct 2011
VDDIO
VSS/VSSA/
VSSBG/
VSSGS
Solomon Systech
DIE PAD FLOOR PLAN
Figure 5-1 - SSD1606Z0 Die Floor Plan (Bump face up)
Pin539
Die Information:
Die Size: [After sawing]
X = 12.7 +/- 0.1 mm
Y = 1.3 +/- 0.1 mm
Output pad:
Source output pad:
2
20x100 = 2000 m
Gate output pad:
2
18x112 = 2016 m
I/O pad:
2
40x70 = 2800 m
Output Pad Pitch:
Output Pad Pitch: 34 m
Bump area: 2000 um2 min
Bump gap 16m min
Alignment Marks:
Pin205
SSD1606
Pin206
Rev 1.1
P 7/56
Oct 2011
Solomon Systech
Table 5-1 : SSD1606Z0 Bump Die Pad Coordinates

PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
NAME
NC
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VSS
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
PREVGL
VSS
VSL
VSL
VSL
VSL
VSL
VSL
VSL
VSL
VSL
VSL
VSS
PREVGH
PREVGH
PREVGH
PREVGH
PREVGH
PREVGH
PREVGH
PREVGH
PREVGH
PREVGH
PREVGH
PREVGH
VSS
VSH
VSH
VSH
VSH
VSH
VSH
VSH
VSH
VSH
VSH
VSS
VPP
VPP
VPP
VPP
VPP
VPP
VPP
VPP
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SSD1606
X
-6120
-6060
-6000
-5940
-5880
-5820
-5760
-5700
-5640
-5580
-5520
-5460
-5400
-5340
-5280
-5220
-5160
-5100
-5040
-4980
-4920
-4860
-4800
-4740
-4680
-4620
-4560
-4500
-4440
-4380
-4320
-4260
-4200
-4140
-4080
-4020
-3960
-3900
-3840
-3780
-3720
-3660
-3600
-3540
-3480
-3420
-3360
-3300
-3240
-3180
-3120
-3060
-3000
-2940
-2880
-2820
-2760
-2700
-2640
-2580
-2520
-2460
-2400
-2340
-2280
-2220
-2160
-2100
-2040
-1980
-1920
-1860
-1800
-1740
-1680
-1620
-1560
-1500
-1440
-1380
Y
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
Rev 1.1
PIN
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
NAME
VSS
VSS
VSS
VSS
VSSGS
VSSGS
VSSGS
VSSGS
VSSGS
VSSGS
VSSGS
VSSGS
VSSA
VSSA
VSSA
VSSA
VSSA
VSSBG
VSSBG
VSSBG
VSSBG
VSSBG
VCIBG
VCIBG
VCIBG
VCIBG
VCIBG
VCIA
VCIA
VCIA
VCIA
VCIA
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
D7
D6
D5
D4
D3
D2
D1
D0
VSS
CS#
VDDIO
R/W#
VSS
D/C#
VDDIO
E
VSS
RES#
BUSY
CL
VDDIO
CLS
VSS
BS2
VDDIO
BS1
VSS
BS0
VDDIO
EXTVDD
VSS
TSDA
TSDA
TSCL
TSCL
P 8/56
X
-1320
-1260
-1200
-1140
-1080
-1020
-960
-900
-840
-780
-720
-660
-600
-540
-480
-420
-360
-300
-240
-180
-120
-60
0
60
120
180
240
300
360
420
480
540
600
660
720
780
840
900
960
1020
1080
1140
1200
1260
1320
1380
1440
1500
1560
1620
1680
1740
1800
1860
1920
1980
2040
2100
2160
2220
2280
2340
2400
2460
2520
2580
2640
2700
2760
2820
2880
2940
3000
3060
3120
3180
3240
3300
3360
3420
Y
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
Oct 2011
PIN
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
NAME
TPA
TPC
TPD
TPB
VGH
VGH
VGH
VGH
VGH
VGH
VGH
VGH
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VSS
FB
FB
VSS
RESE
RESE
VSS
GDR
GDR
GDR
GDR
GDR
GDR
GDR
GDR
VSS
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
NC
NC
NC
NC
NC
NC
NC
G0
G2
G4
G6
G8
G10
G12
G14
G16
G18
G20
G22
G24
G26
G28
G30
G32
G34
G36
G38
G40
G42
G44
G46
G48
G50
G52
G54
G56
X
3480
3540
3600
3660
3720
3780
3840
3900
3960
4020
4080
4140
4200
4260
4320
4380
4440
4500
4560
4620
4680
4740
4800
4860
4920
4980
5040
5100
5160
5220
5280
5340
5400
5460
5520
5580
5640
5700
5760
5820
5880
5940
6000
6060
6120
6089
6055
6021
5987
5953
5919
5885
5851
5817
5783
5749
5715
5681
5647
5613
5579
5545
5511
5477
5443
5409
5375
5341
5307
5273
5239
5205
5171
5137
5103
5069
5035
5001
4967
4933
Y
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
-552
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
PIN
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
NAME
G58
G60
G62
G64
G66
G68
G70
G72
G74
G76
G78
G80
G82
G84
G86
G88
G90
G92
G94
G96
G98
G100
G102
G104
G106
G108
G110
G112
G114
G116
G118
G120
G122
G124
G126
G128
G130
G132
G134
G136
G138
G140
G142
G144
G146
G148
G150
G152
G154
G156
G158
G160
G162
G164
G166
G168
G170
G172
G174
G176
G178
NC
NC
NC
NC
NC
NC
VBD
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
X
4899
4865
4831
4797
4763
4729
4695
4661
4627
4593
4559
4525
4491
4457
4423
4389
4355
4321
4287
4253
4219
4185
4151
4117
4083
4049
4015
3981
3947
3913
3879
3845
3811
3777
3743
3709
3675
3641
3607
3573
3539
3505
3471
3437
3403
3369
3335
3301
3267
3233
3199
3165
3131
3097
3063
3029
2995
2961
2927
2893
2859
2820
2780
2740
2700
2660
2620
2580
2540
2500
2460
2420
2380
2340
2300
2260
2220
2180
2140
2100
Y
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
Solomon Systech
PIN
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
NAME
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
SSD1606
X
2060
2020
1980
1940
1900
1860
1820
1780
1740
1700
1660
1620
1580
1540
1500
1460
1420
1380
1340
1300
1260
1220
1180
1140
1100
1060
1020
980
940
900
860
820
780
740
700
660
620
580
540
500
460
420
380
340
300
260
220
180
140
100
60
20
-20
-60
-100
-140
-180
-220
-260
-300
-340
-380
-420
-460
-500
-540
-580
-620
-660
-700
-740
-780
-820
-860
-900
-940
-980
-1020
-1060
-1100
Y
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
Rev 1.1
PIN
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
NAME
S92
S93
S94
S95
S96
S97
S98
S99
S100
S101
S102
S103
S104
S105
S106
S107
S108
S109
S110
S111
S112
S113
S114
S115
S116
S117
S118
S119
S120
S121
S122
S123
S124
S125
S126
S127
VBD
NC
NC
NC
NC
NC
NC
G179
G177
G175
G173
G171
G169
G167
G165
G163
G161
G159
G157
G155
G153
G151
G149
G147
G145
G143
G141
G139
G137
G135
G133
G131
G129
G127
G125
G123
G121
G119
G117
G115
G113
G111
G109
G107
P 9/56
X
-1140
-1180
-1220
-1260
-1300
-1340
-1380
-1420
-1460
-1500
-1540
-1580
-1620
-1660
-1700
-1740
-1780
-1820
-1860
-1900
-1940
-1980
-2020
-2060
-2100
-2140
-2180
-2220
-2260
-2300
-2340
-2380
-2420
-2460
-2500
-2540
-2580
-2620
-2660
-2700
-2740
-2780
-2820
-2859
-2893
-2927
-2961
-2995
-3029
-3063
-3097
-3131
-3165
-3199
-3233
-3267
-3301
-3335
-3369
-3403
-3437
-3471
-3505
-3539
-3573
-3607
-3641
-3675
-3709
-3743
-3777
-3811
-3845
-3879
-3913
-3947
-3981
-4015
-4049
-4083
Y
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
537
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
Oct 2011
PIN
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
NAME
G105
G103
G101
G99
G97
G95
G93
G91
G89
G87
G85
G83
G81
G79
G77
G75
G73
G71
G69
G67
G65
G63
G61
G59
G57
G55
G53
G51
G49
G47
G45
G43
G41
G39
G37
G35
G33
G31
G29
G27
G25
G23
G21
G19
G17
G15
G13
G11
G9
G7
G5
G3
G1
NC
NC
NC
NC
NC
NC
X
-4117
-4151
-4185
-4219
-4253
-4287
-4321
-4355
-4389
-4423
-4457
-4491
-4525
-4559
-4593
-4627
-4661
-4695
-4729
-4763
-4797
-4831
-4865
-4899
-4933
-4967
-5001
-5035
-5069
-5103
-5137
-5171
-5205
-5239
-5273
-5307
-5341
-5375
-5409
-5443
-5477
-5511
-5545
-5579
-5613
-5647
-5681
-5715
-5749
-5783
-5817
-5851
-5885
-5919
-5953
-5987
-6021
-6055
-6089
Y
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
531
Y
X
Pad 1,2,3,>> 205

Gold Bumps face up
Unit in um
Die height
Bump height
250 +/- 25
12
Bump size
Pad
1-205
Pad
206-301
Pad
302-443
Pad
444-539
X
40
18
20
18
Y
70
112
100
112
X
6185
-6185
Y
498
498
Alignment mark
'+ shape
+' shape
Solomon Systech
Pin Description
Key:
I = Input, O =Output, IO = Bi-directional (input/output), P = Power pin, C = Capacitor Pin

NC = Not Connected, Pull L =connect to VSS, Pull H = connect to VDDIO
Pin
name
Type Connect to
Input power
VCI
P
Function
Description
When
not in
use
Power
Supply
Power
Supply
Power Supply Power Supply for the chip
Power Supply Power input for the chip,

Connected with VCI
VCIA
VCIBG
Power
Supply
Power Supply Power input for the chip (Reference),

Connected with VCI
VDDIO
Power
Supply
Power for
Power Supply for the Interface
interface logic It should be connected with VCI
pins
VDD
Capacitor
Regulator
output
Core logic power pin

VDD can be regulated internally from VCI. A capacitor
should be connected between VDD and VSS under all
circumstances.
EXTVDD I
VDDIO/VSS Reserve for

Testing
This pin is VDD regulator enable pin.

It should be connected with VSS.
VSS
VSSA
P
P
VSS
VSS
GND
GND
VSSBG
VSS
GND
VSSGS
VSS
GND
Ground (Digital)
Ground (Analog)
It should be connected with VSS.
Ground (Reference)
Connected with VSS
Ground (Output)
Connected with VSS
VPP
Power
Supply
OTP power
Power Supply for OTP Programming
Open
MPU
Data Bus
These pins are bi-directional data bus connecting to

the MCU data bus.
D[2] :
OPEN
SPI mode:
D0: SCLK
D1: SDIN
Other:
VDDIO
or VSS
Digital I/O
D [7:0]
I/O
CS#
SSD1606
MPU
Rev 1.1
Logic Control This pin is the chip select input connecting to the MCU. VDDIO
The chip is enabled for MCU communication only
or VSS
when CS# is pulled LOW in parallel interface.
P 10/56
Oct 2011
Solomon Systech
Pin
name
Type Connect to
Function
Description
R/W#
(WR#)
MPU
MPU
System
Reset
This pin is read / write control input pin connecting to

the MCU interface.
When 6800 interface mode is selected, this pin will be
used as Read/Write (R/W#) selection input. Read
mode will be carried out when this pin is pulled HIGH
and write mode when LOW.
the Write (WR#) input. Data write operation is initiated
when this pin is pulled LOW and the chip is selected.
When serial interface is selected, this pin R/W (WR#)
can be connected to either VDDIO or VSS.
This pin is Data/Command control pin connecting to
the MCU.
When the pin is pulled HIGH, the data at D [7:0] will be
interpreted as data.
When the pin is pulled LOW, the data at D [7:0] will be
interpreted as command.
This pin is MCU interface input.
used as the Enable (E) signal. Read/write operation is
initiated when this pin is pulled HIGH and the chip is
selected.
When 8080 interface mode is selected, this pin
receives the Read (RD#) signal. Read operation is
initiated when this pin is pulled LOW and the chip is
selected.
When serial interface is selected, this pin E (RD#)
should be connected to either VDDIO or VSS
This pin is reset signal input.
Active Low.
D/C#
MPU
E (RD#) I
MPU
RES#
BUSY
MPU
Device Busy This pin is Busy state output pin

Signal
When Busy is High, the operation of the chip should
not be interrupted, command should not be sent.
When
not in
use
VDDIO
or VSS
VDDIO
or VSS
VDDIO
or VSS
Open
e.g., The chip would put Busy pin High when

- Outputting display waveform; or
- Programming with OTP
- Communicating with digital temperature sensor
CLS
VDDIO/VSS Mode
Selection
This pin is internal clock enable pin.

It should be connected with VDDIO.
CL
I/O
NC
Open
BS [2:0]
This pin is Reserved for production testing. Keep it

open.
These pins are for selecting different bus interface.
BS2 should be connected to VSS.
Reserve for
Testing
VDDIO/VSS Mode
Selection
Table 6-1 : Bus Interface selection
SSD1606
Rev 1.1
P 11/56
BS1
L
L
H
BS0
L
H
L
Oct 2011
MPU Interface
4-lines serial peripheral interface (SPI)
8-bit 8080 parallel interface
3-lines serial peripheral interface (SPI)
9 bits SPI
8-bit 6800 parallel interface
Solomon Systech
Pin
name
Type Connect to
TSDA
I/O
TSCL
Function
Description
When
not in
use
Open
Temperature Interface to
sensor SDA Digital
Temperature
Sensor
Temperature Interface to
sensor SCL Digital
Temperature
Sensor
This pin is I C Interface to digital temperature sensor

Data pin
External pull up resistor is required when connecting to
2
I C slave
2
This pin is I C Interface to digital temperature sensor Open
Clock pin
External pull up resistor is required when connecting to
2
I C slave
PREVGH &
POWER
PREVGL
MOSFET
Generation
Driver
Control
Booster
Control Input
This pin is N-Channel MOSFET Gate Drive Control.
This pin is the Current Sense Input for the Control

Loop
Booster
Control Input
This pin is the Feedback Input for the Control

Loop
PREVGH C
Stabilizing
capacitor
PREVGL C
Stabilizing
capacitor
This pin is the Power Supply pin for VGH and VSH.
A stabilizing capacitor should be connected between
PREVGH and VSS.
This pin is the Power Supply pin for VCOM, VGL and
VSL.
PREVGL and VSS.
VGH
Stabilizing
capacitor
VGH, VGL
Generation
VGL
Stabilizing
capacitor
VGL
Generation
VSH
Stabilizing
capacitor
VSH, VSL
Generation
VSL
Stabilizing
capacitor
VCOM
Panel/
Stabilizing
capacitor
Analog Pin
GDR
RESE
FB
Panel Driving
S [127:0] O
Panel
G [179:0] O
Panel
VBD
Panel
SSD1606
Rev 1.1
VCOM
Positive Gate driving voltage.

VGH and VSS.
This pin is Negative Gate driving voltage.
VGL and VSS.
This pin is Positive Source driving voltage.

VSH and VSS.
This pin is Negative Source driving voltage.
VSL and VSS.
This pin is VCOM driving voltage

VCOM and VSS.
Source
Source output pin
driving signal
Gate driving Gate output pin
signal
Border
Border output pin
driving signal
P 12/56
Oct 2011
Open
Open
Open
Solomon Systech
Pin
name
Type Connect to
Function
Description
When
not in
use
Others
NC
NC
NC
Keep open. Do not connect with other NC pins
Open
TPA
NC
NC
Keep open.
Open
TPB
NC
NC
Keep open.
Open
TPC
NC
NC
Keep open.
Open
TPD
NC
NC
Not
Connected
Reserve for
Testing
Reserve for
Testing
Reserve for
Testing
Reserve for
Testing
Keep open.
Open
SSD1606
Rev 1.1
P 13/56
Oct 2011
Solomon Systech
FUNCTIONAL BLOCK DESCRIPTION
The device can drive an active matrix TFT EPD panel. It composes of 128 source outputs, 180 gate
outputs, 1 VBD and 1 VCOM. It contains flexible built-in waveforms to drive the EPD panel.
7.1
MCU Interface
Note
(1)
L is connected to VSS
(2)
H is connected to VDDIO
7.1.1 MCU Interface selection

SSD1606 MCU interface consist of 8 data pins and 5 control pins. The pin assignment at different
interface mode is summarized in Table 7-1. Different MCU mode can be set by hardware selection
on BS [2:0] pins.
Table 7-1 : MCU interface assignment under different bus interface mode
Pin Name
Bus
Interface
SPI4
Data/Command Interface
D7
D6
D5
D4
D3
8-bit 8080
D2
D1
D0
NC
SDin
SCLK
D [7:0]
SPI3
RD#
NC
8-bit 6800
E
(RD#)
L
SDin
SCLK
D [7:0]
Control Signal
R/W#
CS#
D/C#
(WR#)
L
CS#
D/C#
WR#
CS#
R/W#
RES#
RES#
D/C#
RES#
CS#
RES#
CS#
D/C#
RES#
7.1.2 MCU Parallel 6800-series Interface

The parallel interface consists of 8 bi-directional data pins (D[7:0]), R/W#, D/C#, E and CS#.
A LOW in R/W# indicates WRITE operation and HIGH in R/W# indicates READ operation.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
The E input serves as data latch signal while CS# is LOW. Data is latched at the falling edge of E
signal.
Table 7-2 : Control pins of 6800 interface
Function
R/W#
CS#
D/C#
Write data
Read data
Write
command
Read status
Note
(1)
stands for falling edge of signal
In order to match the operating frequency of display RAM with that of the microprocessor, some
pipeline processing is internally performed which requires the insertion of a dummy read before the
first actual display data read. This is shown in Figure 7-1.
SSD1606
Rev 1.1
P 14/56
Oct 2011
Solomon Systech
Figure 7-1 : Data read back procedure - insertion of dummy read

R/W#
Databus
Write column
address
Dummy read
n+1
Read 1st data
Read 2nd data
n+2
Read 3rd data
7.1.3 MCU Parallel 8080-series Interface

The parallel interface consists of 8 bi-directional data pins (D[7:0]), RD#, WR#, D/C# and CS#.
A LOW in D/C# indicates COMMAND read/write and HIGH in D/C# indicates DATA read/write.
A rising edge of RD# input serves as a data READ latch signal while CS# is kept LOW.
A rising edge of WR# input serves as a data/command WRITE latch signal while CS# is kept LOW.
Figure 7-2 : Example of Write procedure in 8080 parallel interface mode
CS#
WR#
D[7:0]
D/C#
high
RD#
low
Figure 7-3 : Example of Read procedure in 8080 parallel interface mode
CS#
RD#
D[7:0]
D/C#
WR#
high
low
SSD1606
Rev 1.1
P 15/56
Oct 2011
Solomon Systech
Table 7-3 : Control pins of 8080 interface (Form 1)
Function
Write command
Read status
Write data
Read data
RD#
H
WR#
CS#
L
L
L
L
D/C#
L
L
H
H
Note
(1)
stands for rising edge of signal
(2)
Refer to Figure 13-2 for Form 1 8080-Series MPU Parallel Interface Timing Characteristics
Alternatively, RD# and WR# can be keep stable while CS# serves as the data/command latch
signal.
Table 7-4 : Control pins of 8080 interface (Form 2)
Function
Write command
Read status
Write data
Read data
RD#
H
L
H
L
WR#
CS#
L
H
L
H
D/C#
L
L
H
H
Note
(1)
(2)
Refer to Figure 13-3 for Form 2 8080-Series MPU Parallel Interface Timing Characteristics
In order to match the operating frequency of display RAM with that of the microprocessor, some
pipeline processing is internally performed which requires the insertion of a dummy read before the
first actual display data read. This is shown in Figure 7-4.
Figure 7-4 : Display data read back procedure - insertion of dummy read
WR#
RD#
Databus
N
Write column
address
SSD1606
Rev 1.1
Dummy read
P 16/56
Oct 2011
n+1
Read 1st data
Read 2nd data
n+2
Read 3rd data
Solomon Systech
7.1.4 MCU Serial Interface (4-wire SPI)

The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In SPI mode, D0
acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from
D3 to D7, E and R/W# can be connected to an external ground.
Table 7-5 : Control pins of Serial interface
Function
E(RD#)
R/W#(WR#)
CS#
D/C#
SCLK
Write command
Tie LOW
Tie LOW
Write data
Tie LOW
Tie LOW
Note
(1)
SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0.
D/C# is sampled on every eighth clock and the data byte in the shift register is written to the
Graphic Display Data RAM (RAM) or command register in the same clock.
Under serial mode, only write operations are allowed.
Figure 7-5 : Write procedure in SPI mode
CS#
D/C#
SDIN/
SCLK
DB1
DB2
DBn
SCLK(D0)
SDIN(D1)
SSD1606
Rev 1.1
D7
P 17/56
D6
D5
Oct 2011
D4
D3
D2
D1
D0
Solomon Systech
7.1.5 MCU Serial Interface (3-wire SPI)

The 3-wire serial interface consists of serial clock SCLK, serial data SDIN and CS#.
In 3-wire SPI mode, D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be
left open. The pins from D3 to D7, R/W# (WR#)#, E and D/C# can be connected to an external
ground.
The operation is similar to 4-wire serial interface while D/C# pin is not used. There are altogether 9bits will be shifted into the shift register on every ninth clock in sequence: D/C# bit, D7 to D0 bit.
The D/C# bit (first bit of the sequential data) will determine the following data byte in the shift
register is written to the Display Data RAM (D/C# bit = 1) or the command register (D/C# bit = 0).
Under serial mode, only write operations are allowed.
Table 7-6 : Control pins of 3-wire Serial interface
Function
Write command
Write data
E(RD#)
Tie LOW
Tie LOW
R/W#(WR#)
Tie LOW
Tie LOW
CS#
L
L
D/C#
Tie LOW
Tie LOW
SCLK
Note
(1)
Figure 7-6 : Write procedure in 3-wire Serial interface mode

CS#
SDIN/
SCLK
DB1
DB2
DBn
SCLK
(D0)
SDIN(D1)
SSD1606
D/C#
Rev 1.1
D7
P 18/56
D6
D5
Oct 2011
D4
D3
D2
D1
D0
Solomon Systech
7.2
RAM
The On chip display RAM is holding the image data. 1 set of RAM is built for historical data and the
other set is built for the current image data. The size of each RAM is 128x180x2 bits.
Table 7-7 shows the RAM map under the following condition:
Command Data Entry Mode R11h is set to:

Address Counter update in X direction
X: Increment
Y: Increment
Command Driver Output Control R01h is set to
180 Mux
Select G0 as 1st gate
Left and Right gate Interlaced
Scan From G0 to G179
Command Gate Start Position R0Fh is set to:
Set the Start Position of Gate = G0
Data byte sequence: DB0, DB1, DB2 DB5759
AM=0
ID[1:0] =11
MUX = B3h
GD = 0
SM = 0
TB = 0
SCN=0
Table 7-7 : RAM address map

S0
S1
S2
S3
S4
S5
DB0
[7:6]
DB32
[7:6]
S6
S7
DB0
[5:4]
DB32
[5:4]
DB0
[3:2]
DB32
[3:2]
DB0
[1:0]
DB32
[1:0]
DB1
[7:6]
DB33
[7:6]
DB1
[5:4]
DB33
[5:4]
DB1
[3:2]
DB33
[3:2]
DB1
[1:0]
DB33
[1:0]
DB5696
[7:6]
DB5728
[7:6]
DB5696
[5:4]
DB5728
[5:4]
DB5696
[3:2]
DB5728
[3:2]
DB5696
[1:0]
DB5728
[1:0]
DB5697
[7:6]
DB5729
[7:6]
DB5697
[5:4]
DB5729
[5:4]
DB5697
[3:2]
DB5729
[3:2]
DB5697
[1:0]
DB5729
[1:0]
00h
G0
00h
G1
01h
G178
B2h
G179
B3h
GATE
Y-ADDR
7.3
S124
S125
DB31
[7:6]
DB63
[7:6]
01h
S126
S127
DB31
[5:4]
DB63
[5:4]
DB31
[3:2]
DB63
[3:2]
DB31
[1:0]
DB63
[1:0]
DB5727
[7:6]
DB5759
[7:6]
DB5727
[5:4]
DB5759
[5:4]
DB5727
[3:2]
DB5759
[3:2]
DB5727
[1:0]
DB5759
[1:0]
1Fh
Source
XADDR
OSCILLATOR
On-chip oscillator is included for the use on waveform timing and Booster operations.
7.4
Booster & Regulator
A voltage generation system is included in the driver. It provides all necessary driving voltage
required for an AMEPD panel.
SSD1606
Rev 1.1
P 19/56
Oct 2011
Solomon Systech
Figure 7-7 : Input and output voltage relation chart
PREVGH
VGH
VGH
Gate
driving
VSH
VSH
Source
driving
VCI
VSS
VCOM
PREVGL
VCOM
VSL
VSL
VGL
VGL
Source
driving
Gate
driving
Max voltage difference between VGH and VGL is 42V.
SSD1606
Rev 1.1
P 20/56
Oct 2011
Solomon Systech
7.5
Panel Driving Waveform

Figure 7-8 : Vpixel Definition
Gate
Vpixel
Source
Vcom
The Vpixel is defined as Figure 7-8, and its relations with GATE, SOURCE are shown below figure.
Figure 7-9 : The Relation of Vpixel Waveform with Gate and Source
VSH
VSS
VSL
Vpixel
Busy
...
VDDIO
VSS
Frame count of
phase 1
...
VSH
Border
VSL
VSH
Source
...
VSL
VGH
G0
VGL
VGH
G1
VGL
VGH
G2
VGL
VGH
G179
VGL
Scanning period
G0
Dummy line
period
VSH
Source
G1
TP[n]
VSL
VGH
VGL
VGH
VGL
R0Bh
R0Bh
Non-overlap between
source and gate
7.6
7.6.1
VCOM Functional
VCOM regulation
This functional block generates the voltage of VCOM, which are necessary for operating an AMEPD.
7.6.2
VCOM Sensing
This functional block provides the scheme to select the optimal VCOM DC level and programmed the setting
into OTP.
SSD1606
Rev 1.1
P 21/56
Oct 2011
Solomon Systech
7.7
Gate and Programmable Source waveform
Figure 7-10 : Programmable Source and Gate waveform illustration
DATA
VSH
GS0 to GS0
VSS
VS[n-00]
VS[(n-1)00]
VS[6-00]
VS[5-00]
VS[4-00]
VS[3-00]
VS[2-00]
VS[1-00]
VS[0-00]
VSL
VSH
GS0 to GS1
VSS
VS[n-01]
VS[(n-1)01]
VS[6-01]
VS[5-01]
VS[4-01]
VS[3-01]
VS[2-01]
VS[1-01]
VS[0-01]
VSL
VSH
GS3 to GS3
VSS
VS[n-33]
VS[(n-1)33]
VS[6-33]
VS[5-33]
VS[4-33]
VS[3-33]
VS[2-33]
VS[1-33]
VS[0-33]
VSL
VGH
Gate
Signal
VGL
TP[0]
TP[1]
TP[2]
TP[n]
There are totally 20 phases for programmable Source waveform of different phase length.
The phase period defined as TP [n] * TFRAME, where TP [n] range from 0 to 15.
TP [n] = 0 indicates phase skipped
Source Voltage Level: VS [n-XY] is constant in each phase
VS [n-XY] indicates the voltage in phase n for transition from GS X to GS Y
00 VSS
01 VSH
10 VSL
11 HiZ
VS [n-XY] and TP[n] are stored in waveform lookup table register [LUT].
SSD1606
Rev 1.1
P 22/56
Oct 2011
Solomon Systech
7.8
Waveform Look Up Table (LUT)
LUT contains 720bits, which define the display driving waveform settings. They are arranged in
following format
Figure 7-11 : VS[n-XY] and TP[n] mapping in LUT
in Decimal
1
2
3
4
5
6
7
8
77
78
79
80
81
82
90
7.9
D7
D6
D5
D4
VS[0-03]
VS[0-02]
VS[0-13]
VS[0-12]
VS[0-23]
VS[0-22]
VS[0-33]
VS[0-32]
VS[1-03]
VS[1-02]
VS[1-13]
VS[1-12]
VS[1-23]
VS[1-22]
VS[1-33]
VS[1-32]
VS[19-03]
VS[19-02]
VS[19-13]
VS[19-12]
VS[19-23]
VS[19-22]
VS[19-33]
VS[19-32]
TP[1]
TP[3]
TP[19]
D3
D2
D1
D0
VS[0-01]
VS[0-00]
VS[0-11]
VS[0-10]
VS[0-21]
VS[0-20]
VS[0-31]
VS[0-30]
VS[1-01]
VS[1-00]
VS[1-11]
VS[1-10]
VS[1-21]
VS[1-20]
VS[1-31]
VS[1-30]
VS[19-01]
VS[19-00]
VS[19-11]
VS[19-10]
VS[19-21]
VS[19-20]
VS[19-31]
VS[19-30]
TP[0]
TP[2]
TP[18]
OTP
The OTP is the non-volatile memory and stored the information of:
OTP Selection Option
VCOM value
11 set of WAVEFORM SETTING (WS) [720bits x 11]
10 set of TEMPERATURE RANGE (TR) [24bits x 10]
For Programming the WS and TR, Write RAM is required, and the configurations should be
Command: Data Entry mode
C11,
D03
Command: X RAM address

start /end
C44,
D00,
D1F
C45,
D00,
DB3
C4E,
D00
C4F,
D00
Command: Y RAM address

start /end
Command: RAM X address
counter
Command: RAM Y address
counter
SSD1606
Rev 1.1
P 23/56
Set Address automatic increment setting =

X increment and Y increment
Set Address counter update in X direction
Set RAM Address for S0 to S127
Set RAM Address for G0 to G179
Set RAM X AC as 0
Set RAM Y AC as 0
Oct 2011
Solomon Systech
The mapping table of OTP is shown in below figure,

Figure 7-12 : OTP Content and Address Mapping
WRITE RAM ADDRESS
X
NA
0
1
2
3
4
14
15
16
17
25
26
19
29
30
31
0
1
2
3
22
23
24
25
26
27
Y
NA
0
0
0
0
0
2
2
2
2
2
2
28
30
30
30
31
31
31
31
31
31
31
31
31
31
D7
D6
D5
D4
D3
D2
D1
D0
VCOM
VS[0-03]
VS[0-13]
VS[0-23]
VS[0-33]
VS[1-03]
VS[19-23]
VS[19-33]
VS[0-02]
VS[0-12]
VS[0-22]
VS[0-32]
VS[1-02]
VS[19-22]
VS[19-32]
VS[0-01]
VS[0-11]
VS[0-21]
VS[0-31]
VS[1-01]
VS[19-21]
VS[19-31]
TP[1]
TP[3]
TP[19]
VS[0-00]
VS[0-10]
VS[0-20]
VS[0-30]
VS[1-00]
VS[19-20]
VS[19-30]
WS [0]
TP[0]
TP[2]
TP[18]
WS[1]
WS[10]
TEMP[1-L][7:0]
TEMP[1-H][3:0]
TEMP[1-L][11:8]
TEMP[1-H][11:4]
TEMP[2-L][11:0]
TEMP[2-H][11:0]
TEMP[9-L][11:0]
TEMP[9-H][11:0]
TEMP[10-L][11:0]
TEMP[10-H][11:0]
Remark:
WS [m] means the waveform setting of temperature set m, the configuration are same as
the definition in LUT. The corresponding low temperature range of WS[m] defined as TEMP
[m-L] and high range defined as TEMP [m-H]
Load WS [m] from OTP for LUT if Temp [m-L] < Temperature Register <= Temp [m-H]
SSD1606
Rev 1.1
P 24/56
Oct 2011
Solomon Systech
7.10 Temperature Searching Mechanism

Legend:
WS#
Waveform Setting no. #
TR#
Temperature Range no. #
LUT
720 bit register storing the waveform setting (volatile)
Temperature register
12bit Register storing reading from temperature sensor (volatile)
OTP
A non-volatile storing 11 sets of waveform setting and 10 set of temperature range
WS_sel_address
an address pointer indicating the selected WS#
Figure 7-13 : Waveform Setting and Temperature Range # mapping
OTP (non-volatile)
WS0
WS1
TR1
WS2
TR2
WS3
TR3
WS4
TR4
WS5
TR5
WS6
TR6
WS7
TR7
WS8
TR8
WS9
TR9
WS10
TR10
IC implementation requirement
1
Default selection is WS0
Compare temperature register from TR1 to TR10, in sequence. The last match will be recorded
i.e. If the temperature register fall in both TR5 and TR7. WS7 will be selected
If none of the range TR1 to TR10 is match, WS0 will be selected.
User application
1
The default waveform should be programmed as WS0
There is no restriction on the sequence of TR1, TR2. TR10.
SSD1606
Rev 1.1
P 25/56
Oct 2011
Solomon Systech
7.11 External Temperature Sensor I2C Single Master Interface

The chip provides two I/O lines [TSDA and TSCL] for connecting digital temperature sensor for
temperature reading sensing.
TSDA will treat as SDA line and TSCL will treat as SCL line. They are required connecting with
external pull-up resistor.
1. If the Temperature value MSByte bit D11 = 0, then
The temperature is positive and value (DegC) = + (Temperature value) / 16
2. If the Temperature value MSByte bit D11 = 1, then
The temperature is negative and value (DegC) = ~ (2s complement of Temperature value) / 16
12-bit binary
(2's complement)
0111 1111 0000
0111 1110 1110
0111 1110 0010
0111 1101 0000
0001 1001 0000
0000 0000 0010
0000 0000 0000
1111 1111 1110
1110 0111 0000
1100 1001 0010
1100 1001 0000
SSD1606
Rev 1.1
Hexadecimal
Value
7F0
7EE
7E2
7D0
190
002
000
FFE
E70
C92
C90
P 26/56
Oct 2011
Decimal
Value
2032
2030
2018
2000
400
2
0
-2
-400
-878
-880
Value
[DegC]
127
126.875
126.125
125
25
0.125
0
-0.125
-25
-54.875
-55
Solomon Systech
COMMAND TABLE
Table 8-1: Command Table
(D/C#=0, R/W#(WR#) = 0, E(RD#=1) unless specific setting is stated)

Fundamental Command Table
R/W# D/C# Hex
D7
D6
D5
D4
D3
D2
D1
A2
A1
0
0
0
0
1
1
01
0
A7
0
0
A6
0
0
A5
0
0
A4
0
0
A3
0
0
A2
B2
0
A1
B1
Command
A0 Status Read
D0
Description
Read Driver status on
A2: BUSY flag
A1,A0: Chip ID (01 as default)
1 Driver Output control Gate setting

A[7:0]: MUX setting as A[7:0] + 1
A0
POR = B3h + 1 MUX
B0
B[2:0]: Gate scanning sequence and
direction
B[2]: GD
Selects the 1st output Gate
GD=0, G0 is the 1st gate output
channel, gate output sequence is
G0,G1, G2, G3,
[POR]
GD=1, G1 is the 1st gate output
channel, gate output sequence is G1,
G0, G3, G2,
B[1]: SM
Change scanning order of gate driver.
SM=0, G0, G1, G2, G3G179 (left and
right gate interlaced) [POR]
SM=1, G0, G2, G4 G178, G1,
G3, G179
B[0]: TB
TB = 0, scan from G0 to G179 [POR]
TB = 1, scan from G179 to G0
0
0
0
0
0
1
02
03
SSD1606
0
0
A7
0
0
A6
0
0
A5
Rev 1.1
0
0
A4
0
0
A3
P 27/56
0
0
A2
1
1
A1
0 Reserve
1 Gate Driving voltage Set Gate related driving voltage
A[7:4]: VGH, 15 to 22V in 0.5V step
A0 Control
Oct 2011
Solomon Systech

R/W# D/C# Hex
D7
D6
D5
D4
D3
D2
D1
D0
Command
Description
VGH
0000 15.0
0001 15.5
0010 16.0
0011 16.5
0100 17.0
0101 17.5
0110 18.0
0111 18.5
1000 19.0
1001 19.5
1010 20.0
1011 20.5
1100 21.0
1101 21.5
1110 22.0
Others N/A
[POR]
A[3:0]: VGL, -15 to -20V in 0.5V step

VGL default at -20V
04
A3
A2
A1
0 Source Driving
voltage Control
A0
VGL
0000 -15.0
0001 -15.5
0010 -16.0
0011 -16.5
0100 -17.0
0101 -17.5
0110 -18.0
0111 -18.5
1000 -19.0
1001 -19.5
1010 -20.0 [POR]
Others N/A
Set Source output voltage magnitude
A[3:0]: VSH/VSL 10V to 17V in 0.5V
step
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
Others
05
SSD1606
Rev 1.1
P 28/56
VSH/VSL
10.0
10.5
11.0
11.5
12.0
12.5
13.0
13.5
14.0
14.5
15.0 [POR]
15.5
16.0
16.5
17.0
N/A
1 Reserve
Oct 2011
Solomon Systech

R/W# D/C# Hex
0
0
0
0
0
1
06
07
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
A5
0
0
A4
0
0
0
1
1
0
1
1
0
Command
0 Reserve
1 Display Control
A0
D0
Description
Display control setting
A[0]: Grey Scale (GS) mode (1bit)
Mono vs 4 GS
A[0] = 0: 4GS [POR]
A[0] = 1: Mono
In mono mode,
Data 00, 01 will be treat as 0,
Data 10,11 will be treat as 1
Only use transition between
GS0 to GS0 or GS3
GS3 to GS0 or GS3
A[4]
1
A[5]
1
Description
All Gate output voltage level
as VGH
All Gate output voltage level
as VGL
Selected gate output as VGL,
non-selected gate output as
VGH
Selected gate output as VGH,
non-selected gate output as
VGL
[POR]
0
0
0
0
0
0
0
0
08
09
0A
0B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
A3
A2
A1
A0
Reserve
Reserve
Reserve
Gate and Source non Set Delay of gate and source non
overlap period
overlap period
Gate falling edge to source output
Control
change
Source change to Gate rising edge
Delay Duration in terms of Oscillator
clock [1/FOSC]
A [3:0]
Delay Duration
0000
0
0001
2
0010
4
0101
1110
1111
0
0
0
0
0
0
0
0
0C
0D
0E
0F
SSD1606
0
0
0
0
0
0
0
0
0
0
0
0
Rev 1.1
0
0
0
0
1
1
1
1
P 29/56
1
1
1
1
0
0
1
1
0
1
0
1
Oct 2011
Reserve
Reserve
Reserve
Gate scan start
10
[POR]
28
30
Set the scanning start position of the
Solomon Systech

R/W# D/C# Hex
0
0
0
1
10
0
0
0
1
11
Command
position
D7
D6
D5
D4
D3
D2
D1
D0
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0 Deep Sleep mode

A0
0
0
0
0
0
0
1
0
0
0
0
A2
0
A1
1 Data Entry mode

A0 setting
Description
gate driver. The valid range is from 0 to
179.
TB=0:
SCN [7:0] = A[7:0]
00h [POR]
TB=1:
SCN [7:0] = 179 - A[7:0] 00h [POR]
Deep Sleep mode Control
A[0] :
0
1
Description
[POR]
Enter Deep Sleep Mode
Define data entry sequence

A [1:0]: Address automatic increment /
decrement setting
The setting of incrementing or
decrementing of the address counter
can be made independently in each
upper and lower bit of the address.
00 Y decrement, X decrement,
01 Y decrement, X increment,
10 Y increment, X decrement,
11 Y increment, X increment [POR]
A[2]: Set the direction in which the
address counter is updated
automatically after data are written to the
RAM.
A[2] = 0, the address counter is updated
in the X direction. [POR]
A[2] = 1, the address counter is updated
in the Y direction.
12
0 SWRESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
13
14
15
16
17
18
19
1A
0
0
0
0
0
0
0
0
A7
B7
0
0
0
0
0
0
0
0
A6
B6
0
0
0
0
0
0
0
0
A5
B5
1
1
1
1
1
1
1
1
A4
B4
0
0
0
0
0
1
1
1
A3
0
0
1
1
1
1
0
0
0
A2
0
1
0
0
1
1
0
0
1
A1
0
1
0
1
0
1
0
1
0
A0
0
0
1
0
1
1B
0
X7
0
X6
0
X5
1
X4
1
X3
1
X2
0
X1
SSD1606
Rev 1.1
P 30/56
It resets the commands and parameters

to their S/W Reset default values except
R10h-Deep Sleep Mode
Note: RAM are unaffected by this
command
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Temperature Sensor Write to temperature register.
Control (Write to
temperature register) A[7:0] MSByte 01111111[POR]
B[7:0] LSByte 11110000[POR]
1 Temperature Sensor Read from temperature register.
X0 Control (Read from X[7:0] MSByte
Oct 2011
Solomon Systech

R/W# D/C# Hex
1
0
0
0
0
1
0
1
1
1
1C
D7
D6
D5
D4
D3
D2
D1
Y7
0
A7
B7
C7
Y6
0
A6
B6
C6
Y5
0
A5
B5
C5
Y4
1
A4
B4
C4
0
1
A3
B3
C3
0
1
A2
B2
C2
0
0
A1
B1
C1
Command
0 temperature register)
0 Temperature Sensor
A0 Control (Write
Command to
B0 temperature sensor
C0 )
D0
Description
Y[7:4] LSByte
Write Command to temperature sensor
A[7:6] Select no of byte to be sent
00 Address + pointer
st
01 Address + pointer + 1 parameter
st
10 Address + pointer + 1 parameter
nd
+ 2 pointer
11 Address
A[5:0] Pointer Setting
st
B[7:0] 1 parameter
nd
C[7:0] 2 parameter
1D
0
0
0
0
0
0
1E
1F
20
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
1
1
0
1
1
0
The command required CLKEN=1.

1 Temperature Sensor Load temperature register with
temperature sensor reading
Control (Load
temperature register
BUSY=H for whole loading period
with temperature
sensor reading)
0 Reserve
1 Reserve
0 Master Activation
Activate Display Update Sequence

The Display Update Sequence Option is
located at R22h
21
SSD1606
Rev 1.1
P 31/56
1 Display Update
Oct 2011
User should not interrupt this operation

to avoid corruption of panel images.
Option for Display Update
Solomon Systech

R/W# D/C# Hex
D7
D6
D5
D4
D3
D2
D1
D0
A7
A5
A4
A3
A2
A1
A0
Command
Control 1
Description
Bypass Option used for Pattern Display,
which is used for display the RAM
content into the Display
OLD RAM Bypass option
A [7]
1
Enable bypass
0
Disable bypass [POR]
A[5:4] value will be used as for bypass
00
[POR]
A[3:0] Initial Update Option - Source
Control
0000
0001
0010
0011
[POR]
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
22
SSD1606
Rev 1.1
P 32/56
0 Display Update
Oct 2011
GSC
A[3:2]
GS0
GS0
GS0
GS0
GSD
A[1:0]
GS0
GS1
GS2
GS3
GS1
GS1
GS1
GS1
GS2
GS2
GS2
GS2
GS3
GS3
GS3
GS3
GS0
GS1
GS2
GS3
GS0
GS1
GS2
GS3
GS0
GS1
GS2
GS3
Display Update Sequence Option:
Solomon Systech

R/W# D/C# Hex
D7
D6
D5
D4
D3
D2
D1
D0
A7
A6
A5
A4
A3
A2
A1
A0
Command
Control 2
Description
Enable the stage for Master Activation
Parameter
(in Hex)
Enable Clock Signal,
Then Enable CP
Then Load Temperature value
Then Load LUT
Then INIITIAL DISPLAY
Then PATTERN DISPLAY
Then Disable CP
Then Disable OSC
Enable Clock Signal,
Then Enable CP
Then Load Temperature value
Then Load LUT
Then PATTERN DISPLAY
Then Disable CP
Then Disable OSC
To Enable Clock Signal
(CLKEN=1)
To Enable Clock Signal,
then Enable CP
(CLKEN=1, CPEN=1)
To INITIAL DISPLAY + PATTEN
DISPLAY
FF
[POR]
F7
80
C0
0C
To INITIAL DISPLAY
08
To DISPLAY PATTEN
To Disable CP,
then Disable Clock Signal
(CLKEN=1, CPEN=1)
To Disable Clock Signal
(CLKEN=1)
04
03
01
Remark:
CLKEN=1:
If CLS=VDDIO then Enable OSC
If CLS=VSS then Enable External Clock
CLKEN=0:
If CLS=VDDIO then Disable OSC
AND
INTERNAL CLOCK Signal = VSS,
0
0
0
0
23
24
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1 Reserve
0 Write RAM
25
1 Read RAM
0
0
0
0
26
27
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0 Reserve
1 Reserve
SSD1606
Rev 1.1
P 33/56
Oct 2011
After this command, data entries will be

written into the RAM until another
command is written. Address pointers
will advance accordingly.
After this command, data read on the
MCU bus will fetch data from RAM, until
another command is written. Address
pointers will advance accordingly.
Solomon Systech

0
28
Command
0 VCOM Sense
0
0
0
1
29
0
0
0
0
1
0
0
0
1
A3
0
A2
0
A1
1 VCOM Sense
A0 Duration
2A
Stabling time between entering VCOM

sensing mode and reading acquired.
VCOM sense duration = Setting + 1
Seconds
0x09(10Seconds) [POR]
0 Program VCOM OTP Program VCOM register into OTP
2B
1 Reserve
0
0
0
1
1
0
1
0
1
1
2C
2D
0
A7
0
A7
B7
0
A6
0
A6
B6
1
A5
1
A5
B5
0
A4
0
A4
B4
1
A3
1
A3
B3
0
A2
1
A2
B2
1
A1
0
A1
B1
1 Write VCOM register

A0
1 Read OTP Registers
A0
B0
0
0
0
0
0
0
2E
2F
30
0
0
0
0
0
0
1
1
1
0
0
1
1
1
0
1
1
0
1
1
0
0 Reserve
1 Reserve
0 Program WS OTP
31
1 Reserve
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
0
0
32
0 Write LUT register
Write LUT register from MCU [720 bits]
1 Read LUT register
Read from LUT register (excluding

temperature data) [720 bits]
34
35
36
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
1
0 Reserve
1 Reserve
0 Program OTP
selection
Program OTP Selection according to the

OTP Selection Control [R36h]
37
1 OTP selection
Write the OTP Selection:
R/W# D/C# Hex
D7
D6
D5
D4
D3
D2
D1
D0
Description
Enter VCOM sensing conditions and
hold for duration defined in 29h before
reading VCOM value.
The sensed VCOM voltage is stored in
register
Write VCOM register from MCU

interface
Read register reading to MCU
A [7:0] Spare OTP Option
B [7:0] VCOM Register
Program OTP of Waveform Setting

The contents should be written into RAM
before sending this command.
LUT
[90 bytes]
33
LUT
[90 bytes]
SSD1606
Rev 1.1
P 34/56
Oct 2011
Solomon Systech

R/W# D/C# Hex
D7
D6
D5
D4
D3
D2
D1
D0
A7
A6
A5
A4
A3
A2
A1
A0
Command
Control
Description
A[7]=1
A[6]
A[5]=1
A[4]
spare VCOM OTP

VCOM_Status
spare WS OTP
WS_Status
A3:A0 are reserved OTP bit. User can

treat the bits as Version Control.
0
0
0
0
0
0
0
1
38
39
3A
0
0
0
1
3B
0
0
0
0
0
0
0
A6
1
1
1
A5
1
1
1
A4
1
1
1
A3
0
0
0
A2
0
0
1
A1
0
1
0
A0
Reserve
Reserve
Set dummy line
period
0
0
0
0
1
0
1
0
1
A3
0
A2
1
A1
1 Set Gate line width

A0
Set number of dummy line period

A[6:0]: Number of dummy line period in
term of TGate
4 [POR]
Available setting 0 to 127.
Set Gate line width (TGate)
A[3:0] Line width in us
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
60
64
68
72
78
84
90
98
108 [POR]
120
136
154
180
216
272
362
Remark: Default value will give 50Hz

Frame frequency under 4 dummy line
pulse setting.
0
3C
SSD1606
Rev 1.1
P 35/56
0 Border Waveform
Oct 2011
Select border waveform for VBD
Solomon Systech

R/W# D/C# Hex
D7
D6
D5
D4
D3
D2
D1
D0
A7
A6
A5
A4
A3
A2
A1
A0
Command
Control
Description
A [7]
Follow Source at Initial Update
Display
A [7]=0: [POR]
A [7]=1: Follow Source at Initial Update
Display for VBD, A [6:0] setting are
being overridden at Initial Display
STAGE.
A [6]
Select GS Transition/ Fix Level
for VBD
A [6]=0: Select GS Transition A[3:0] for
VBD
A [6]=1: Select FIX level Setting A[5:4]
for VBD
[POR]
A [5:4] Fix Level Setting for VBD
VBD
00
VSS
01
VSH
10
VSL
11[POR]
HiZ
A [3:0] GS transition setting for VBD
(Select waveform like data A[3:2] to data
A[1:0])
GSA
GSB
0000
GS0
GS0
0001
GS0
GS1
0010
GS0
GS2
0011
GS0
GS3
[POR]
0100
GS1
GS0
0101
GS1
GS1
0110
GS1
GS2
0111
GS1
GS3
1000
GS2
GS0
1001
GS2
GS1
1010
GS2
GS2
1011
GS2
GS3
1100
GS3
GS0
1101
GS3
GS1
1110
GS3
GS2
1111
GS3
GS3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
3D
3E
3F
40
41
42
43
44
SSD1606
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
Rev 1.1
1
1
1
0
0
0
0
0
A4
1
1
1
0
0
0
0
0
A3
P 36/56
1
1
1
0
0
0
0
1
A2
0
1
1
0
0
1
1
0
A1
1
0
1
0
1
0
1
0
A0
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Set RAM X - address Specify the start/end positions of the
Start / End position window address in the X direction by an
Oct 2011
Solomon Systech

R/W# D/C# Hex
D7
D6
D5
D4
D3
D2
D1
D0
B4
B3
B2
B1
B0
Command
0
0
0
0
1
1
45
0
A7
B7
1
A6
B6
0
A5
B5
0
A4
B4
0
A3
B3
1
A2
B2
0
A1
B1
1 Set Ram Y- address

A0 Start / End position
B0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
46
47
48
49
4A
4B
4C
4D
4E
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A4
0
0
1
1
1
1
1
1
1
A3
1
1
0
0
0
0
1
1
1
A2
1
1
0
0
1
1
0
0
1
A1
0
1
0
1
0
1
0
1
0
A0
0
0
0
1
4F
0
A7
1
A6
0
A5
0
A4
1
A3
1
A2
1
A1
1 Set RAM Y address

A0 counter
0
0
0
1
F0
1
A7
1
A6
1
A5
1
A4
0
A3
0
A2
0
A1
0 Booster Feedback
A0 Selection
FF
1 NOP
SSD1606
Rev 1.1
P 37/56
Oct 2011
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Set RAM X address
counter
Description
address unit
A[7:0]: XStart, POR = 00h
B[7:0]: XEnd, POR = 1Fh
Specify the start/end positions of the
window address in the Y direction by an
address unit
A[7:0]: YStart, POR = 00h
B[7:0]: YEnd, POR = B3h
Make initial settings for the RAM X

address in the address counter (AC)
POR is 0
Make initial settings for the RAM Y
address in the address counter (AC)
POR is 0
Set Booster Feedback selection
0x1F = Internal Feedback is used
POR is 0x1F
This command is an empty command; it
does not have any effect on the display
module.
However it can be used to terminate
Frame Memory Write or Read
Commands.
Solomon Systech
Command DESCRIPTION
9.1
9.1.1
Fundamental command description

Driver Output Control (01h)
This double byte command has multiple configurations and each bit setting is described as follows:
R/W
DC
W
1
POR
W
1
POR
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
MUX7 MUX6 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0
1
0
1
1
0
0
1
1
GD
SM
TB
0
0
0
MUX[7:0]: Specify number of lines for the driver: MUX[7:0] + 1. Multiplex ratio (MUX ratio) from 16 MUX to
180MUX.
GD: Selects the 1st output Gate
This bit is made to match the GATE layout connection on the panel. It defines the first scanning line.
SM: Change scanning order of gate driver.
When SM is set to 0, left and right interlaced is performed.
When SM is set to 1, no splitting odd / even of the GATE signal is performed,
Output pin assignment sequence is shown as below (for 180 MUX ratio):
Driver
G0
G1
G2
G3
:
G88
G89
G90
G91
:
G176
G177
G178
G179
SM=0
GD=0
ROW0
ROW1
ROW2
ROW3
:
ROW88
ROW89
ROW90
ROW91
:
ROW176
ROW177
ROW178
ROW179
SM=0
GD=1
ROW1
ROW0
ROW3
ROW2
:
ROW89
ROW88
ROW91
ROW90
:
ROW177
ROW176
ROW179
ROW178
SM=1
GD=0
ROW0
ROW90
ROW1
ROW91
:
ROW44
ROW134
ROW45
ROW135
:
ROW88
ROW178
ROW89
ROW179
SM=1
GD=1
ROW90
ROW0
ROW91
ROW1
:
ROW134
ROW44
ROW135
ROW45
:
ROW178
ROW88
ROW179
ROW89
See Scan Mode Setting on next page.

TB: Change scanning direction of gate driver.
This bit defines the scanning direction of the gate for flexible layout of signals in module either from
up to down (TB = 0) or from bottom to up (TB = 1).
SSD1606
Rev 1.1
P 38/56
Oct 2011
Solomon Systech
Figure 9-1: Output pin assignment on different Scan Mode Setting
SM = 0
GD = 0
SM = 1
ROW0
ROW1
ROW0
ROW1
ROW2
...
...
...
ROW88
ROW89
ROW89
ROW90
ROW91
...
ROW90
ROW91
ROW92
...
...
ROW178
ROW179
G
1
G G
8 9
9 1
G
1
7
9
G
1
7
8
ROW179
G G
9 8
0 8
G
0
Pad 1, 2, 3,
Gold Bumps face up
GD = 1
G G G
1 3 5
G
1
7
9
G
1
7
8
Pad 1,2,3,
Gold Bumps face up
ROW0
ROW1
ROW0
ROW1
ROW2
...
...
...
ROW88
ROW89
ROW89
ROW90
ROW91
...
ROW90
ROW91
ROW92
...
...
ROW178
ROW179
G
1
G G
8 9
9 1
G
1
7
9
G
1
7
8
ROW179
G G
9 8
0 8
Pad 1,2,3,
Gold Bumps face up
SSD1606
Rev 1.1
P 39/56
G G G
4 2 0
G
0
G G G
1 3 5
G
1
7
9
G
1
7
8
G G G
4 2 0
Pad 1,2,3,
Gold Bumps face up
Oct 2011
Solomon Systech
9.1.2
Gate Scan Start Position (0Fh)

R/W
DC
W
1
POR
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SCN7 SCN6 SCN5 SCN4 SCN3 SCN2 SCN1 SCN0
0
This command is to set Gate Start Position for determining the starting gate of display RAM by
selecting a value from 0 to 179. Figure 9-2 shows an example using this command of this command
when MUX ratio= 180 and MUX ratio= 90 ROW means the graphic display data RAM row.
Figure 9-2: Example of Set Display Start Line with no Remapping
GATE Pin
G0
G1
G2
G3
:
:
G43
G44
G45
G46
:
:
G88
G89
G90
G91
:
G133
G134
G135
G136
:
G176
G177
G178
G179
MUX ratio (01h) = 179

Gate Start Position (0Fh) = 0


ROW0
ROW1
ROW2
ROW3
:
:
:
:
:
:
:
:
ROW88
ROW89
ROW90
ROW91
:
:
:
:
:
:
:
:
ROW176
ROW177
ROW178
ROW179
ROW0
ROW1
ROW2
ROW3
:
:
:
:
:
:
:
:
ROW88
ROW89
:
:
:
:
:
:
:
:
-
:
:
ROW45
ROW46
:
:
:
:
:
:
:
:
ROW133
ROW134
:
:
-
Display
Example
9.1.3
Data Entry Mode Setting (11h)

This command has multiple configurations and each bit setting is described as follows:
SSD1606
Rev 1.1
P 40/56
Oct 2011
Solomon Systech
R/W
DC
W
1
POR
IB7
IB6
IB5
IB4
IB3
IB2
AM
0
IB1
ID1
0
IB0
ID0
0
ID[1:0]: The address counter is automatically incremented by 1, after data are written to the RAM when ID[1:0]
= 1. The address counter is automatically decremented by 1, after data are written to the RAM when ID[1:0]
= 0. The setting of incrementing or decrementing of the address counter can be made independently in each
upper and lower bit of the address. The direction of the address when data are written to the RAM is set with
AM bits.
AM: Set the direction in which the address counter is updated automatically after data are written to the RAM.
When AM = 0, the address counter is updated in the X direction. When AM = 1, the address counter is
updated in the Y direction. When window addresses are selected, data are written to the RAM area specified
by the window addresses in the manner specified with ID1-0 and AM bits.
ID [1:0]="00
X: decrement
Y: decrement
ID [1:0]="01
X: increment
Y: decrement
ID [1:0]="10
X: decrement
Y: increment
ID [1:0]="11
X: increment
Y: increment
00,00h
00,00h
00,00h
00,00h
AM="0
X-mode
1F,B3h
1F,B3h
00,00h
00,00h
1F,B3h
1F,B3h
00,00h
00,00h
AM="1
Y-mode
1F,B3h
1F,B3h
1F,B3h
1F,B3h
The pixel sequence are defined by the ID [0],

ID[1:0]="00
X: decrement
Y: decrement
ID[1:0]="01
X: increment
Y: decrement
00,00h
00,00h
AM="0
X
4, 3, 2, 1
1F,B3h
SSD1606
Rev 1.1
P 41/56
Oct 2011
1, 2, 3, 4
1F,B3h
Solomon Systech
9.1.4
Set RAM X - Address Start / End Position (44h)

R/W DC
W
1
POR
W
1
POR
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
XSA4 XSA3 XSA2 XSA1 XSA0
0
0
0
0
0
XEA4 XEA3 XEA2 XEA1 XEA0
1
1
1
1
1
XSA[4:0]/XEA[4:0]: Specify the start/end positions of the window address in the X direction by 4 times
address unit. Data are written to the RAM within the area determined by the addresses specified by XSA [4:0]
and XEA [4:0]. These addresses must be set before the RAM write.
It allows on XEA [4:0] XSA [4:0]. The settings follow the condition on 00h XSA [4:0], XEA [4:0] 1Fh. The
windows is followed by the control setting of Data Entry Setting (R11h)
9.1.5
Set RAM Y - Address Start / End Position (45h)

R/W DC
W
1
POR
W
1
POR
POR
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
YSA7 YSA6 YSA5 YSA4 YSA3 YSA2 YSA1 YSA0
0
0
0
0
0
0
0
0
YEA7 YEA6 YEA5 YEA4 YEA3 YEA2 YEA1 YEA0
1
1
0
1
0
0
1
1
YSA[7:0]/YEA[7:0]: Specify the start/end positions of the window address in the Y direction by an address
unit. Data are written to the RAM within the area determined by the addresses specified by YSA [7:0] and
YEA [7:0]. These addresses must be set before the RAM write.
It allows YEA [7:0] YSA [7:0]. The settings follow the condition on 00h YSA [7:0], YEA [7:0] B3h. The
windows is followed by the control setting of Data Entry Setting (R11h)
9.1.6
9.1.7
Reserve (46-4Dh)
Set RAM Address Counter (4Eh-4Fh)
Reg# R/W DC
W
1
4Eh
POR
W
1
4Fh
POR
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
XAD4 XAD3 XAD2 XAD1 XAD0
0
0
0
0
0
0
0
0
YAD7 YAD6 YAD5 YAD4 YAD3 YAD2 YAD1 YAD0
0
0
0
0
0
0
0
0
XAD[4:0]: Make initial settings for the RAM X address in the address counter (AC).
YAD[7:0]: Make initial settings for the RAM Y address in the address counter (AC).
After RAM data are written, the address counter is automatically updated according to the settings with AM,
I/D bits and setting for a new RAM address is not required in the address counter. Therefore, data are written
consecutively without setting an address. The address counter is not automatically updated when data are
read out from the RAM. RAM address setting cannot be made during the standby mode. The address setting
should be made within the area designated with window addresses which is controlled by the Data Entry
Setting (R11h) {AD, ID[1:0]} ; RAM Address XStart / XEnd Position (R44h) and RAM Address Ystart /Yend
Position (R45h). Otherwise undesirable image will be displayed on the Panel.
SSD1606
Rev 1.1
P 42/56
Oct 2011
Solomon Systech
10 Typical Operating Sequence

10.1 Normal Display
Sequence Action Command Action Description
by
1 User
Power on (VCI supply);
2 User
HW Reset
IC
After HW reset, the IC will have
Registers load with POR value
Ready for command input
VCOM register loaded with OTP value
IC enter idle mode
3
User
User
User
User
User
User
4
User
User
User
User
User
User
5 User
C 01
Send initial code to driver including setting of

Command: Panel configuration (MUX, Source gate
scanning direction)
C 03
C 04
C 3A
C 3B
C 3C
C 11
C 44
C 45
C 4E
C 4F
C 24
Command: VGH, VGL voltage

Command: VSH / VSL voltage
Command: Set dummy line pulse period
Command: Set Gate line width
Command: Select Border waveform
Data operations
Command: Data Entry mode
Command: X RAM address start /end
Command: Y RAM address start /end
Command: RAM X address counter
Command: RAM Y address counter
6 User
IC
IC
IC
C F0
D 1F
C 20
-
IC
IC
IC
IC
6 User
Remark
Command: write display data to RAM

Ram Content for Display
Command: Set Internal Feedback Selection
Command: Display update
Booster and regulators turn on
Load temperature register with sensor reading
Load LUT register with corresponding waveform
setting stored in OTP)
Send output waveform according initial update option
Send output waveform according to data
Booster and Regulators turn off
Back to idle mode
IC power off;
OTP Selection bit:

Set on R37h, and read from R2Dh, A[7:6] used for VCOM and A[5:4] used for OTP
A[7:6] / [5:4]
Description
00
It indicates fresh device, OTP read and program would be made on Default OTP set
User required setting and programming the bits into 01.
01
It indicates default OTP programmed device, OTP read would be made on Default OTP set.
User require setting and programming the bits into 11
11
It indicates SPARE OTP programmed device, only OTP read would be made on SPARE
SSD1606
Rev 1.1
P 43/56
Oct 2011
Solomon Systech
OTP set.
User should stop the OTP programming if 11 is found at OTP checking stage
10.2 VCOM OTP Program

Sequence Action
by
1 User
2 User
3 User
Command Action Description

C 2D
4 User
5 User
C 37
User
User
6 User
User
User
7
C 22
D 80
C 20
C 36
-
User
C 01
User
User
User
User
C 03
C 04
C 3A
C F0
D 1F
C 32
User
User
User
8 User
IC
IC
IC
IC
IC
User
9 User
User
User
10 User
User
11 User
SSD1606
C 22
D 40
C 20
C 28
C 22
D 02
C 20
C 2A
C 22
Rev 1.1
Remark
Power on (VCI and VPP supply)

HW Reset
Check whether the IC status and determine whether
"default" or "spare" OTP should be used
If the IC had been OTP twice (both default and spare
had been used up). The operation should stop
Proceed OTP sequence.
OTP selection register
Command: Indicate which OTP location to be use
(default or spare)
Command: CLKEN=1
Wait until BUSY = L
Program OTP selection register
Wait until BUSY = L
Power OFF (VPP supply)
Send initial code to driver including setting of (or leave VCOM sensing
as POR)
should have same
setting during
Command: Panel configuration (MUX, Source gate
application
scanning direction)
Command: VGH, VGL voltage
Command: VSH / VSL voltage
Command: Set dummy line pulse period
Command: Set Internal Feedback Selection
VCOM sense required full set of LUT for operation,
USER required writing LUT in register 32h
LUT parameter
Command: Booster on and High voltage ready
Wait until BUSY = L
Command: Enter VCOM sensing mode
VCOM pin in sensing mode
All Source cell have VSS output
All Gate scanning continuously
Wait for 10s
Detect VCOM voltage and store in register
All Gate Stop Scanning.
Wait until BUSY = L
Command: Booster and High voltage disable
According to R29h
Wait until BUSY = L

Power On (VPP supply)
Command: VCOM OTP program
Wait until BUSY = L
Command: CLKEN=0
P 44/56
Oct 2011
Solomon Systech
User
12 User
D 01
C 20
-
Wait until BUSY = L

IC power off (VCI and VPP Supply)
10.3 WS OTP Program

Sequence Action Command Action Description
by
1 User Power on (VCI supply)
2 User Power on (VPP supply)
3 User
4 User
C 2D
5 User
6 User
C 37
User
C 22
D 80
C 20
C 36
C 24
User
7 User
User
8 User
User
9 User
IC
IC
IC
IC
User
10 User
User
11 User
SSD1606
C 4E
D 00
C 4F
D 00
C 30
C 22
D 01
C 20
-
Rev 1.1
HW Reset
Check whether the IC status and determine whether
"default" or "spare" OTP should be used
If the IC had been OTP twice (both default and spare
had been used up). The operation should stop
Proceed OTP sequence.
Command: Indicate which OTP location to be use
(default or spare)
Command: CLKEN=1
Remark
OTP selection
register
Wait BUSY = L
Program OTP selection register
Wait BUSY = L
Write corresponding data into RAM
Following specific format
Write into RAM
Full LUT (11 entries + Temperature range) must be
written at the same time
Command: Initial Ram address counter
Waveform Setting OTP programming

BUSY pin pull H
Check the OTP Selection
IC control OTP programming time, and transfer
data to selected OTP
BUSY pin pull L
Wait BUSY = L
Command: CLKEN=0
Wait BUSY = L
IC power off
P 45/56
Oct 2011
Solomon Systech
11 ABSOLUTE MAXIMUM RATING

Table 11-1: Maximum Ratings
Symbol
VCI
VIN
VOUT
TOPR
TSTG
Parameter
Logic supply voltage
Logic Input voltage
Logic Output voltage
Operation temperature range
Storage temperature range
Rating
-0.5 to +3.6
-0.5 to VDDIO+0.5
-0.5 to VDDIO+0.5
-40 to +85
-65 to +150
Unit
V
V
V
C
C
Maximum ratings are those values beyond which damages to the device may occur. Functional operation should be
restricted to the limits in the Electrical Characteristics tables or Pin Description section
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it
is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to
this high impedance circuit. This device is not radiation protected.
12 ELECTRICAL CHARACTERISTICS
The following specifications apply for: VSS=0V, VCI=3.0V, VDD=1.8V, TOPR=25C.
Table 12-1: DC Characteristics
Symbol
Parameter
VCI
VCI operation
voltage
VDD operation
voltage
VCOM output
voltage
VDD
VCOM
VGATE
VGATE(p-p)
VSH
VSL
VIH
VIL
VOH
VOL
VPP
SSD1606
Test Condition Applicable

pin
VCI
Gate output
voltage
Gate output
peak to peak
voltage
Positive Source
output voltage
Negative Source
output voltage
Min.
Typ.
Max.
2.4
3.0
3.3
VDD
1.7
1.8
1.9
VCOM
-4.0
-0.2
G0-179
-20
+22
42
+17
G0-179
S0-127
S0-127
High level input

voltage
Low level input
voltage
High level output IOH = -100uA
voltage
Low level output IOL = 100uA
voltage
OTP Program
voltage
Rev 1.1
-VSH
0.8VDDIO
0.2VDDIO V
0.9VDDIO
V
0.1VDDIO V
VPP
P 46/56
+10
Unit
Oct 2011
7.5
Solomon Systech
Symbol
Parameter
Idslp_VCI
Deep Sleep
mode current
Islp_VCI
Sleep mode
current

pin
VCI
VCI=3.3V
DC/DC OFF
No clock
No output load
Ram data not
retain
VCI=3.3V
Operating
current
VGH
Operating Mode VCI=3.3V

Output Voltage DC/DC on
VGH=22V
VGL=-20V
VSH=15V
VSL=-15V
VCOM = -2V
No waveform
transitions.
No loading.
Osc on
Bandgap on
VCOM
VSL
VGL
SSD1606
Rev 1.1
VCI
DC/DC OFF
No clock
No output load
Ram data retain
VCI
VCI=3.3V
DC/DC on
VGH=22V
VGL=-20V
VSH=15V
VSL=-15V
VCOM = -2V
No waveform
transitions.
No loading.
No RAM
read/write
No OTP read
/write
Osc on
Bandgap on
Iopr_VCI
VSH
Min.
P 47/56
Oct 2011
Typ.
Max.
uA
35
50
uA
2000
Unit
uA
VGH
21
22
23
VSH
14.5
15
15.5
VCOM
-2.5
-2
-1.5
VSL
-15.5
-15
-14.5
VGL
-21
-20
-19
Solomon Systech
Table 12-2: Regulators Characteristics
Symbol
Parameter
IVGH
IVGL
IVSH
IVSL
IVCOM
VGH current
VGL current
VSH current
VSL current
VCOM current
SSD1606
Rev 1.1

pin
VGH = 22V
VGH
VGL = -20V
VGL
VSH = +15V
VSH
VSL = -15V
VSL
VCOM = -2V
VCOM
P 48/56
Oct 2011
Min.
Typ.
Max.
Unit
400
600
4000
4000
100
uA
uA
uA
uA
uA
Solomon Systech
13 AC CHARACTERISTICS
The following specifications apply for: VSS=0V, VCI=3.0V, VDD=1.8V, TOPR=25C.
Table 13-1: AC Characteristics
Symbol
Parameter
Fosc
Internal
Oscillator
frequency
SSD1606
Rev 1.1

pin
VCI=2.4 to 3.3V CL
P 49/56
Oct 2011
Min.
Typ.
Max.
Unit
0.95
1.05
MHz
Solomon Systech
13.1 Interface Timing

Table 13-2 : 6800-Series MCU Parallel Interface Timing Characteristics
(VDDIO - VSS = 2.4V to 3.3V, TOPR = 25C, CL=20pF)

Symbol Parameter
tcycle
Clock Cycle Time
tAS
Address Setup Time
tAH
Address Hold Time
tDSW
Write Data Setup Time
tDHW
Write Data Hold Time
tDHR
Read Data Hold Time
tOH
Output Disable Time
tACC
Access Time
Chip Select Low Pulse Width (read)
PW CSL
Chip Select Low Pulse Width (write)
Chip Select High Pulse Width (read)
PW CSH
Chip Select High Pulse Width (write)
tR
Rise Time [20% ~ 80%]
tF
Fall Time [20% ~ 80%]
Min
300
0
0
40
7
20
120
60
60
60
-
Typ
-
Max
70
140
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
ns
ns
Figure 13-1 : 6800-series MCU parallel interface characteristics
D/C#
tAS
tAH
R/W#
CS#
tCYCLE
PWCSH
PWCSL
tDHW
tF
tR
tDSW
D[7:0] (1)
(WRITE)
Valid Data
tACC
D[7:0] (1)
(READ)
tDHR
Valid Data
tOH
SSD1606
Rev 1.1
P 50/56
Oct 2011
Solomon Systech
Table 13-3 : 8080-Series MCU Parallel Interface Timing Characteristics

Symbol
tcycle
tAS
tAH
tDSW
tDHW
tDHR
tOH
tACC
tPWLR
tPWLW
tPWHR
tPWHW
tR
tF
tCS
tCSH
tCSF
Parameter
Min
Typ
Max
Unit
300
10
0
40
7
20
120
60
60
60
0
0
20
70
140
15
15
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Cycle Time

Address Setup Time
Address Hold Time
Read Data Hold Time
Output Disable Time
Access Time
Read Low Time
Write Low Time
Read High Time
Write High Time
Rise Time [20% ~ 80%]
Fall Time [20% ~ 80%]
Chip select setup time
Chip select hold time to read signal
Chip select hold time
Figure 13-2 : 8080-series parallel interface characteristics (Form 1)
Write cycle (Form 1)
Read cycle (Form 1)
CS#
tCSH
CS#
tCSF
tCS
tCS
D/C#
D/C#
tAS
tR
tF
tAH
tPWLW
WR#
tDSW
tAS
tcycle
tPWHW
tAH
tR
tF
tcycle
tPWLR
RD#
tDHW
tPWHR
tACC
D[7:0]
tDHR
D[7:0]
tOH
Figure 13-3 : 8080-series parallel interface characteristics (Form 2)
Write cycle (Form 2)
Read cycle (Form 2)
tcycle
tcycle
tR
CS#
tR
tF
CS#
tPWLW
tPWHR
tPWHW
tCS
tF
tPWLR
tCS
D/C#
D/C#
tAS
tAH
tAS
tCSF
WR#
tAH
RD#
tDSW
tDHW
tCSH
tACC
D[7:0]
tDHR
D[7:0]
tOH
SSD1606
Rev 1.1
P 51/56
Oct 2011
Solomon Systech
Table 13-4 : Serial Interface Timing Characteristics

Symbol Parameter
tcycle
Clock Cycle Time
tAS
Address Setup Time
tAH
Address Hold Time
tCSS
Chip Select Setup Time
tCSH
Chip Select Hold Time
tDSW
tDHW
tCLKL
Clock Low Time
tCLKH
Clock High Time
tR
Rise Time [20% ~ 80%]
tF
Fall Time [20% ~ 80%]
Min
250
150
150
120
60
50
15
100
100
-
Typ
-
Max
15
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 13-4 : Serial interface characteristics

D/C#
t AS
t AH
t CSS
CS#
t CSH
t cycle
tCLKL
tCLKH
SCLK(D 0)
tF
tR
t DSW
SDIN(D 1 )
tDHW
Valid Data
CS#
SCLK(D0 )
D7
SDIN(D1)
SSD1606
Rev 1.1
D6
P 52/56
D5
Oct 2011
D4
D3
D2
D1
D0
Solomon Systech
14 Application
Figure 14-1 : Booster Connection Diagram
L1
VCI
GDR
VDDIO
C0
RESE
VDD
C1
VSS
PREVGH
FB
PREVGL
VGH
VCOM
Generator
SSD1606
VCOM
C9
Rev 1.1
P 53/56
C3
Q1
Oct 2011
R1
D1
CFF
C2
D2
D3
PREVGH &
PREVGL
Generator
C4
C5
VGH
Generator
VSH
C6
VSH
Generator
VGL
C7
VGL
Generator
VSL
C8
VSL
Generator
Solomon Systech
Figure 14-2 : Typical application diagram with SPI interface
SSD1606
Rev 1.1
P 54/56
Oct 2011
Solomon Systech
Table 14-1 : Reference Component Value
Part Name
Value
C0
1uF
Max Volt. Rating

[In V]
6
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
1uF
1uF
4.7uF
1uF
1uF
1uF
1uF
1uF
1uF
10uF
4.7uF
6
50
50
50
25
25
25
25
6
6
50
C12
1uF
50
C71
1uF
L1
Q1
D1
D2
D3
R1
R2
R3
10uH
NMOS [Vishay: Si1304BDL]
Diode [OnSemi: MBR0530]
0.47 Ohm
NC
NC
R11
R12
U3
2.2kOhm
2.2kOhm
LM75A
SSD1606
Rev 1.1
P 55/56
Pins Connected
VCI, VDDIO,
VSS
VDD, VSS
PREVGH
L1 and D2/D3
PREVGL
VGH
VSH
VGL
VSL
VCOM
VCI [Booster]
PREVGL
[Booster]
PREVGH
[Booster]
VCI [LM75A]
GDR, RESE
PREVGH
PREVGL, VSS
RESE
PREVGH, FB
FB, VSS
MAX COG ITO

resistance [in Ohm]
5
30
5
NA
5
10
5
10
5
5
NA
NA
NA
NA
5
NA
NA
NA
5
NA
NA
NA
NA
NA
Oct 2011
Solomon Systech
Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without
limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters,
including Typical must be validated for each customer application by the customers technical experts. Solomon Systech does not
convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death
may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims,
costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the
design or manufacture of the part.
The product(s) listed in this datasheet comply with Directive 2002/95/EC of the European Parliament and of the council of 27
January 2004 on the restriction of the use of certain hazardous substances in electrical and electronic equipment and Peoples Republic
of China Electronic Industry Standard SJ/T 11363-2006 Requirements for concentration limits for certain hazardous substances in
electronic information products (). Hazardous Substances test report is available upon request.
http://www.solomon-systech.com
SSD1606
Rev 1.1
P 56/56
Oct 2011
Solomon Systech

Advanced Information: 4GS Active Matrix EPD 128 X 180 Display Driver With Controller

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Advanced Information: 4GS Active Matrix EPD 128 X 180 Display Driver With Controller

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SOLOMON SYSTECH

SEMICONDUCTOR TECHNICAL DATA

Copyright 2011 Solomon Systech Limited

Appendix: IC Revision history of SSD1606 Specification

GENERAL DESCRIPTION ....................................................................................................... 5

ORDERING INFORMATION ................................................................................................... 6

BLOCK DIAGRAM .................................................................................................................... 6

DIE PAD FLOOR PLAN ............................................................................................................ 7

PIN DESCRIPTION .................................................................................................................. 10

FUNCTIONAL BLOCK DESCRIPTION............................................................................... 14

COMMAND TABLE ................................................................................................................. 27

TYPICAL OPERATING SEQUENCE ................................................................................ 43

NORMAL DISPLAY ...............................................................................................................................................43

ABSOLUTE MAXIMUM RATING ..................................................................................... 46

ELECTRICAL CHARACTERISTICS ................................................................................ 46

INTERFACE TIMING ..............................................................................................................................................50

Design for dot matrix type active matrix EPD display

Gate driving output voltage:

Source / VBD driving output voltage:

VCOM output voltage

Source and gate scan direction control

Ordering Part Number

128 Source Buffer

180 Gate Buffer

Figure 4-1 : SSD1606 Block Diagram

DIE PAD FLOOR PLAN

Figure 5-1 - SSD1606Z0 Die Floor Plan (Bump face up)

Bump gap 16m min

Table 5-1 : SSD1606Z0 Bump Die Pad Coordinates

Pad 1,2,3,>> 205

I = Input, O =Output, IO = Bi-directional (input/output), P = Power pin, C = Capacitor Pin

Power Supply Power Supply for the chip

Power Supply Power input for the chip,

Power Supply Power input for the chip (Reference),

Core logic power pin

VDDIO/VSS Reserve for

This pin is VDD regulator enable pin.

Power Supply for OTP Programming

These pins are bi-directional data bus connecting to

This pin is read / write control input pin connecting to

Device Busy This pin is Busy state output pin

e.g., The chip would put Busy pin High when

This pin is internal clock enable pin.

This pin is Reserved for production testing. Keep it

Table 6-1 : Bus Interface selection

This pin is I C Interface to digital temperature sensor

This pin is N-Channel MOSFET Gate Drive Control.

This pin is the Current Sense Input for the Control

This pin is the Feedback Input for the Control

Positive Gate driving voltage.

This pin is Positive Source driving voltage.

This pin is VCOM driving voltage

Keep open. Do not connect with other NC pins

FUNCTIONAL BLOCK DESCRIPTION

7.1.1 MCU Interface selection

7.1.2 MCU Parallel 6800-series Interface

Figure 7-1 : Data read back procedure - insertion of dummy read

Read 1st data

Read 2nd data

7.1.3 MCU Parallel 8080-series Interface

Figure 7-3 : Example of Read procedure in 8080 parallel interface mode

Table 7-3 : Control pins of 8080 interface (Form 1)

Read 1st data