Synchronous counter

=========================================================================
*

Final Report

=========================================================================
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: binsync

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: NO

Design Statistics
# IOs

:6

Cell Usage :
# BELS

:4

INV

:1

LUT2

:1

LUT3

:1

LUT4

:1

# FlipFlops/Latches
#

FDC

# Clock Buffers
#

BUFGP

: binsync.ngr

:4
:4
:1
:1

# IO Buffers
#

IBUF

OBUF

:5
:1
:4

=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s400tq144-4

Number of Slices:

2 out of 3584

0%

Number of Slice Flip Flops:

4 out of 7168

0%

Number of 4 input LUTs:

4 out of 7168

0%

Number of IOs:
Number of bonded IOBs:
Number of GCLKs:

6
6 out of
1 out of

97

6%

8 12%

--------------------------Partition Resource Summary:

---------------------------

No Partitions were found in this design.

---------------------------

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal

| Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+
clk

| BUFGP

|4

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

--------------------------------------------------------------------------+------------------------+-------+
Control Signal

| Buffer(FF name)

| Load |

-----------------------------------+------------------------+-------+
reset

| IBUF

|4

-----------------------------------+------------------------+-------+

Timing Summary:
--------------Speed Grade: -4

Minimum period: 3.196ns (Maximum Frequency: 312.891MHz)

Minimum input arrival time before clock: No path found
Maximum output required time after clock: 7.285ns
Maximum combinational path delay: No path found

Timing Detail:
-------------All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 3.196ns (frequency: 312.891MHz)
Total number of paths / destination ports: 10 / 4
------------------------------------------------------------------------Delay:
Source:

3.196ns (Levels of Logic = 1)

count_0 (FF)

Destination:

count_0 (FF)

Source Clock:

clk rising

Destination Clock: clk rising

Data Path: count_0 to count_0

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDC:C->Q
INV:I->O
FDC:D

5 0.720 0.921 count_0 (count_0)

1 0.551 0.801 Mcount_count_xor<0>11_INV_0 (Result<0>)
0.203

count_0

---------------------------------------Total

3.196ns (1.474ns logic, 1.722ns route)

(46.1% logic, 53.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 4 / 4

------------------------------------------------------------------------Offset:
Source:

7.285ns (Levels of Logic = 1)

count_0 (FF)

Destination:

count<0> (PAD)

Source Clock:

clk rising

Data Path: count_0 to count<0>

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDC:C->Q
OBUF:I->O

5 0.720 0.921 count_0 (count_0)

5.644

count_0_OBUF (count<0>)

---------------------------------------Total

7.285ns (6.364ns logic, 0.921ns route)

(87.4% logic, 12.6% route)

=========================================================================

Total REAL time to Xst completion: 12.00 secs

Total CPU time to Xst completion: 12.21 secs

-->

Total memory usage is 131564 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

RTL :

TTL :

Power summary:
Same as others

Test fixture:
`timescale 1ns/1ns
module binsync_tb;
reg clk;
reg reset;
wire [3:0]count;
initial
clk=1'b0;
always #5 clk=~clk;
binsync uut(.clk(clk),.reset(reset),.count(count));
initial
begin
reset=1'b0;
#5 reset=1'b1;
#5 reset=1'b0;
#175 $finish;
end
initial
$display($time,"count=%d",count);
endmodule