FAST SIGN DETECTION ALGORITHM FOR THE RNS

MODULI
N+1
SET {2 1, 2N 1, 2N}

ABSTRACT:
This brief presents a fast sign detection algorithm for the residue number
system moduli set {2n+1 1, 2n 1, 2n}. First, a sign detection algorithm for the restricted moduli
set is described. The new algorithm allows for parallel implementation and consists exclusively
of modulo 2n additions. Then, a sign detection unit for the moduli set {2n+1 1, 2n 1, 2n} is
proposed based on the new sign detection algorithm. The unit can be implemented using one
carry save adder, one comparator and one prefix adder. The experimental results demonstrate
that the proposed circuit unit offers 63.8%, 44.9%, and 67.6% savings on average in area, delay
and power, respectively, compared with a unit based on one of the best sign detection algorithms.

EXISTING SYSTEM:
Sign detection plays an essential role in branching operations, magnitude comparisons,
and overflow detection. Because the sign information is concealed in each residue digit in a
residue number system (RNS), sign detection in an RNS is more difficult than that in the
weighted number system, in which the sign is the most significant bit (MSB). Furthermore, sign
detection in an RNS is not as efficient as modular operations such as addition, subtraction, and
multiplication, because of its complexity.

EXISTING ALGORITHM:

Fast Sign Detection Algorithm {2n}

EXISTING SYSTEM DRAWBACK:

Sign detection in an RNS is not as efficient

More Complexity

Area & Delay Increased

PROPOSED SYSTEM:
Proposed system is the only brief to use the combinational logic to implement a sign
detection algorithm based on {2n 1, 2n, 2n +1}. However, the method cannot be extended to
other moduli sets. In this brief, a sign detection algorithm is presented for the moduli set {2n+11,
2n1, 2n }. The proposed sign detection algorithm requires only the addition of the modulo 2 n.
Then, a new sign detection unit is developed for the moduli set {2n+11, 2n1, 2n } based on the
proposed sign detection algorithm.

PROPOSED ALGORITHM:
Sign detection unit for the moduli set {2n+1 1, 2n 1, 2n}

BLOCK DIAGRAM:

PROPOSED SYSTEM ADVANTAGES:

Sign detection in an RNS is as efficient

More Complexity

Less Area & Delay

APPLICATIONS:

Pseudorandom number

Generation and cryptography

Digital Computer & Arithmetic High-Speed Systems

HARDWARE REQUIREMENT:

FPGA Spartan 3

SOFTWARE REQUIREMENTS:

ModelSim 6.4c

Xilinx ISE 9.1/13.2

FUTURE ENHANCEMENT:
We can design an Application part using our Proposed modulo 2n+1 -1,2n -1, 2n adder Design.

ALTERNATE TITLES:
Title 1: Residue Number System moduli set Implementation on FPGA
Title 2: RNS moduli set {2n+1 1, 2n 1, 2n} Implementation based on Fast sign
detection algorithm
Title 3: Implementation of RNS moduli set using Verilog HDL

PROJECT FLOW:
First Phase:
60% of Base Paper (3 Modules only Simulation)

Second Phase:
Remaining 40% of Base Paper with Future Enhancement (Modification).