Vous êtes sur la page 1sur 6

IEEJ Journal of Industry Applications

Vol.2 No.4 pp.183188


DOI: 10.1541/ieejjia.2.183

Paper

Coping with Poor Dynamic Performance of Super-Junction MOSFET


Body Diodes
Martin Pavlovskya) Non-member, Giuseppe Guidi
Atsuo Kawamura Senior Member

Non-member

(Manuscript received Dec. 18, 2012, revised March 23, 2013)

Poor dynamic performance of body diodes in Super Junction MOSFETs may cause diculties when utilised in high
frequency conversion circuits. Excessive reverse recovery as well as forward recovery may in the best case result in
high conversion losses and EMI pollution where as in the worst case they may completely disrupt the converter operation. In this paper, using an auxiliary snubber circuit to control the reverse recovery and connecting a fast diode in
parallel to a super junction switch to reduce the forward recovery is proposed. As documented by numerous experimental results, both proposed concepts work well and both recoveries may be largely avoided. Implementation of the
proposed concepts in a forward boost, reverse buck circuit resulted in eciencies close to 98.5% in 312.5 kW load
range while operating at 62.5 kHz.
Keywords: superjunction MOSFET, body diode, reverse recovery, forward recovery, soft switching

1.

suitable gate control (4) increase of switching losses


due to slowing down the switching speed.
- using a faster discrete diode instead of the body diode (5)
increase of conduction losses due to the necessity of
additional series blocking diode.
This paper discusses an approach which deals with the
poor dynamic performance of SJ-MOSFET body diode without increasing or even reducing the losses in the main power
circuit. The reverse recovery is dealt with by using synchronous rectification as proposed in (6) for hard switched
converters and by using an auxiliary switching circuit that reduces the di/dt during the recovery of the main body diode (7) .
In order to deal with the poor forward recovery, a fast discrete
diodes are connected directly in parallel to SJ-MOSFETs.

Introduction

Design of power converters strives for the best possible efficiency through minimisation of conduction and switching
losses. Since their invention, conventional MOSFETs oer
unbeatable switching speeds as well as low on-state resistance (RDS on ) and therefore they became the primary choice
in low voltage applications. Introduction of so-called SuperJunction (SJ) MOSFET extended the use of MOSFET technology to voltage levels up to hundreds of volts where previously IGBTs were used almost exclusively (1) . In many such
applications, superior dynamic performance of SJ-MOSFETs
and low RDS on are much appreciated and SJ-MOSFETs almost completely pushed out IGBTs.
In spite of numerous advantages of SJ-MOSFETs compared to IGBTs, they have also a drawback in form of an
inherent body diode. This diode is present in the internal
MOSFET structure and therefore it can not be explicitly removed. Due to their primary application, SJ-MOSFETs are
often optimised for the lowest possible RDS on . This leads to
a poor dynamic performance of the body diode (2) . Excessive
reverse and forward recovery limit the use of SJ-MOSFETs
to applications where the diode is not an active part of a circuit. In applications where the diode must perform current
switching functions, special measures must be taken. Examples of such measures and their consequences are:
- optimisation of SJ-MOSFET structure for better body
diode performance (3) increase of RDS on and hence
higher conduction losses.
- slowing down the MOSFET switching process through

2.

The dc-dc converter with controlled reverse recovery is


based on a conventional capacitive turn-o snubber. The operation of the snubber is similar to Auxiliary Resonant Commutated Pole (ARCP) introduced in (8) to soft switched inverters. The advantage of this snubber is that it oers soft
switching without a significant increase of stress on main
power devices unlike some other topologies, for example (9).
In this snubber, a capacitor is connected in parallel to the
active switch in order to slow down the voltage rise across
the main switch during turn-o hence reducing the turn-o
losses. The energy stored in the snubber capacitor during the
turn-o process is recuperated in a resonant fashion before
the turn-on of the main switch in order to prevent excessive
losses.
Circuit diagram of the buck/boost dc-dc converter with
controlled reverse recovery is shown in Fig. 1 as proposed
in (7). The circuit consists of main switches S m1 and

a) Correspondence to: Martin Pavlovsky. E-mail: m.pavlovsky@


ieee.org

Yokohama National University


79-5, Tokiwadai, Hodogaya-ku, Yokohama 240-8501, Japan
c 2013 The Institute of Electrical Engineers of Japan.


Dc-Dc Converter with Controlled Reverse Recovery

183

Coping with Poor Performance of SJ MOSFET Body DiodesMartin Pavlovsky et al.

a) forward boost mode

b) reverse buck mode

Fig. 2. Current flow prior to reverse recovery

Fig. 1. Circuit diagram of forward boost reverse buck


dc-dc circuit used to explore the reverse recovery control
principle

S m2 , snubber capacitors C s1 and C s2 , bi-directional auxiliary


switch comprised of S a1 and S a2 and the auxiliary inductor
La , main inductor Lm and filter capacitors C f 1 and C f 2 . Following discussions concern only intervals relevant to the reverse recovery control. Please, refer to reference (7) for detailed explanation of the circuit operation.
2.1 Reverse Recovery Control Through di/dt Reduction
The reverse recovery control through di/dt is discussed below. Implementations in forward boost respectively
reverse buck mode are very similar and therefore they are discussed together. Relevant current flow through the circuit and
relevant waveforms are shown for both modes in Fig. 2 and
Fig. 3 respectively.
The reverse recovery mode is initiated by turn-on of the
relevant auxiliary switch (S a2 in case of forward boost operation respectively S a1 in case of reverse buck operation). The
action of turning on the auxiliary switch results in the main
inductor current commutation from the rectifying diode (S m2
in case of forward boost mode respectively S m1 in case of reverse buck operation) to the auxiliary circuit (S a1 and S a2 )
during the time interval t0 to t1 . In case if synchronous rectification is used, the synchronous rectifier switch (S m2 in case
of forward boost mode respectively S m1 in case of reverse
buck operation) may be turned-o in the relevant instant after the turn-on of the auxiliary switch as indicated in Fig. 3.
At the end of this commutation interval in the instant t1 , the
reverse recovery occurs. The di/dt of the current commutation which forces the reverse recovery can be calculated as
follows:
- Forward boost operation

a) forward boost mode

b) reverse buck mode

Fig. 3. Waveforms relevant to reverse recovery


explanation

considerably reduced in case of the soft switched approach


(V2 V1 respectively V1 in case of soft switching versus V2
in case of hard switching). The conclusion drawn from this
simple analysis is that the snubber as shown in Fig. 1. is very
eective in controlling the di/dt leading to reverse recovery.
Since the di/dt leading to the reverse recovery is very important to the severity of the reverse recovery itself, reducing the
di/dt may be considered the first step towards reducing the
reverse recovery problem.
2.2 Reverse Recovery Control Through Synchronous
Rectification
Synchronous rectification (SR) is a common practice in converters based on low voltage MOSFETs.
The principle is based on turning on the MOSFET while the
body diode conducts. Very low RDS on in low voltage MOSFETs leads to current shifting from the MOSFET body diode
into the MOSFET channel. The consequence of such operation is reduction of conduction as well as reverse recovery
losses.
The SR operation was until recently restricted to low voltage MOSFETs. In case of high voltage MOSFETs, the RDS on
was not low enough to support SR in a usable current range.
Introduction of SJ-MOSFETs and their subsequent improvement yielded in RDS on which makes the SR viable in applications up to several hundreds of volts.
Using SR in hard switched circuits is explored in (6). The
study shows 60% loss reduction in each SJ-MOSFET where
SR was implemented. The limitation of SR in hard switched
circuits is a requirement of precise timing of gate pulses. The
dead-time between the top and bottom switch of a phase arm
must be as low as 30 ns. In case of longer dead times, the

di/dt = (V2 V1 ) /La (1)


- Reverse buck operation
di/dt = V1 /La (2)
The same di/dt in a hard switched circuit without the recovery control in the forward boost as well as in the reverse buck
mode would be equal to:
di/dt = V2 /L stray (3)
where L stray is the stray inductance of the commutation loop
consisting of S m1 , S m2 and C f 2 . Comparing the hard switched
and soft switched case, it can be seen that the inductance La
which is primarily used to control the charge/discharge of the
snubber capacitors C s1 and C s2 as discussed in (7) can be effectively used to control the di/dt prior to the reverse recovery. In the same time, the voltage which forces the di/dt is
184

IEEJ Journal IA, Vol.2, No.4, 2013

Coping with Poor Performance of SJ MOSFET Body DiodesMartin Pavlovsky et al.

(a) turn-o 200 ns before ZCC

(b) turn-o 100 ns before ZCC

Fig. 4. Illustration of variable SR timing in case of forward boost operation


(c) turn-o at ZCC

current shifts back to the body diode and reverse recovery


occurs. On the other hand, using a dead time which is too
short may result in a shoot through current which may considerably increase the losses in the best case and damage the
phase arm in the worst case.
SR may also be applied to soft switched circuits as shown
in (10). The presented soft switched inverter employs an auxiliary snubber for Zero-Voltage-Switching (ZVS) at the main
switch turn-o. In addition to that, the snubber is very effective in controlling the reverse recovery of the body diode.
Both these eects resulted in 97.5% eciency of the experimental inverter.
Snubber based on the same principle as the one discussed
in (10) was also implemented in a dc-dc chopper discussed
in (11). In this case, the SR was not implemented because the
diode reverse recovery was used to enlarge the soft switching
region. However, the consequence of this approach is loss increase in the auxiliary circuit and the rectifying diode which
results in reduced maximum eciency.
The dc-dc converter circuit shown in Fig. 1. uses the same
snubber as discussed in (11). In this case, SR is implemented
in order to minimise the reverse recovery and hence reach the
maximum possible eciency.
As concluded in (6) and (10), timing of SR switch is very
critical for active suppression of reverse recovery. The timing
of SR may vary as indicated in Fig. 4. As shown, the timing
can be adjusted with respect to the auxiliary switch turn-on
(td1 ) or with respect to the main switch turn-on (td2 ). The
calculation of the SR delay time td1 is rather easy since the
current di/dt remains constant. The relevant equation can be
easily derived from (1) and the result is:

(d) turn-o 100ns after ZCC

Fig. 5. Simulated waveforms for various timings of


synchronous rectifier turn-o; orange current through
synchronous rectifier, purple current through auxiliary
switch, red current of main switch, current scale 10 A/div,
time scale 20 ns/div

Fig. 6. Reverse recovery waveforms for V1 = 200 V,


V2 = 400 V, Po = 3 12.5 kW; CH1 voltage
drain source of S m1 100 V/div, CH3 1/2 current
S m2 10 A/div, CH4 current S a2 20 A/div, time scale
0.2 s/div

crossing (ZCC). Fig. 5 part (a) depicts the case where the reverse recovery suppression is disabled by a premature turno of the SR switch; the current has enough time to commutate from the channel to the diode and recovery occurs as depicted by the waveforms. Turning the SR o closer to ZCC
(Fig. 5 part (b)) reduces the reverse recovery current to a near
zero value. Further shift of the turn-o has only a marginal
impact on the reverse recovery until the point where ZCC occurs (Fig. 5 part (c)). Keeping the SR switch on past the ZCC
introduces a so-called extended reverse conduction shown in
Fig. 5 part (d). Conclusion made from the simulation is that
from the reverse recovery point of view, it is better to turn
the SR o slightly before the ZCC than after. Turning it o
100 ns before the ZCC increases the peak of auxiliary current
by less than 5% (increase from 115 A to 120 A) as shown in
Fig. 5 part (c). However, turning it o 100 ns after the ZCC
increases the peak current by more than 20% (increase from
115 A to 140 A).
2.3 Experimental Results of Reverse Recovery Control
A set of experimental measurements was performed
to verify the reverse recovery approach discussed above. The

td1 = Io La /(V2 V1 ) (4)


where Io f f is the current of SR switch S m2 in the moment of
turn-on of the auxiliary switch S a1 . It should be noted that
the sensitivity of the circuit to stray inductance is very limited since the auxiliary inductance La dominates the auxiliary
path.
pSpice simulation employing real device models was performed to assess the test circuit sensitivity to SR timing. The
simulated waveforms for various timings are shown in Fig. 5.
The timings are indicated with respect to the SR zero current
185

IEEJ Journal IA, Vol.2, No.4, 2013

Coping with Poor Performance of SJ MOSFET Body DiodesMartin Pavlovsky et al.

measured waveforms of the auxiliary and SR switch current


as well as the main switch voltage are shown in Fig. 6. The
waveforms were measured on a test converter identical to
the circuit shown in Fig. 1. Main switches S m1 and S m2 are
made of parallel connected SJ-MOSFETs STY112N65M5 (12)
where as the auxiliary switches S a1 and S a2 are single
IRG4PSC71UD IGBTs (13) . The experiments were performed
at turn-o current increasing from 2 A to 26 A. The peak reverse recovery current as well as the reverse recovery time
remain almost constant. It can be also seen that the di/dt leading to the reverse recovery is 62.5 A/s which is very low
compared to a conventional hard switched circuit. Reverse
recovery charge Qrr estimated from the measured waveforms
equals to approximately 1.3 C which is very low for the SJ
MOSFET with ultra low RDS on . The conclusion based on the
experimental results is that the proposed method of reverse
recovery control works very well and the reverse recovery is
considerably reduced with constant td2 of 200 ns which made
td1 varying with load current exactly as expected.
3.

Fig. 7. Circuit diagram with fast parallel diodes connected

Forward Recovery

(a) SR switch inactive

In recent time, forward recovery in diodes with blocking


voltage of several hundred volts did not pose major problems. However in case of body diodes of SJ-MOSFETs, in
addition to poor reverse recovery, they also exhibit a rather
poor forward recovery. This may cause excessive ringing
at diode turn-on and hence possible EMI issues. Such behaviour was observed while conducting experiments using
the STY112N65M5 SJ-MOSFETs (12) in the circuit shown in
Fig. 1. The forward recovery of S m2 diode without SR being active is shown in Fig. 8 part (a). As shown, the current
commutation from the snubber capacitors to the body diode
results in a considerable ringing of diode current at the frequency of 16.66 MHz with the current peak of 180% of the
steady state value.
3.1 Forward Recovery Control by Synchronous Rectifier
As discussed above, circuit shown in Fig. 1. can
control body diode reverse recovery by Synchronous rectification. The turn-on timing of SR switch has no impact on
the diode reverse recovery as long as the switch is turned on
considerably before the reverse recovery event. However, the
timing of SR switch turn-on may have an impact on the forward recovery if the MOSFET is turned on in the moment
when the current starts its commutation from the snubber capacitors to the diode. This case is presented in Fig. 8 part (b)
where the SR switch turns on when the voltage of S m1 switch
reaches the level of the output voltage Vo . The impact of
such operation is clear when compared to Fig. 8 part (a). As
shown, the current peak is reduced to approximately 120%.
The disadvantage of this operation is that variable and rather
precise timing is required for yet another control signal. This
may in some cases considerably increase the complexity of
the converter controller.
3.2 Forward Recovery Mitigation by Fast Parallel
Diodes
There is zero current flowing in the SJ diode prior
to the forward recovery. This oers yet another solution to
forward recovery by connecting a faster diode directly in parallel to SJ MOSFET as illustrated in Fig. 7. Diodes D1 and
D2 are the fast diodes connected directly in parallel to S m1
and S m2 . These diodes should be fast enough to take over the

(b) SR switch turned on as


soon as VS m1 reaches Vo

Fig. 8. SJ diode forward recovery; Ch1 voltage of


main switch S m1 100 V/div, Ch3 1/2 current of S m2
5 A/div, time scale 0.2 s/div

current as fast as possible and hence prevent the forward recovery of the SJ diode. Conduction properties of these diodes
are not important since they should conduct for only a limited
time.
This approach was tested by using a SiC diode
(IDT16S60C (14) ) at first. The experimental waveforms are
shown in Fig. 9 part (a). As expected, the SiC diode handles
the fast current commutation very well. The current peak is
approximately 125% and the ringing is very small. Subsequently, the current slowly commutates from the SiC diode
to the SJ diode in approximately 0.6 s and after that the SiC
diode current is equal to zero.
The same approach as with SiC diode was also tested with
a conventional Si diode (DSEE29-12CC (15) . The resulting experimental waveforms are shown in Fig. 9 part (b). As can be
seen, the used Si diode handles the current commutation very
well with current peak of only 105%. The ringing is slightly
increased compared to the case with SiC diode but it remains
very small. The subsequent commutation from the parallel
diode to SJ diode is slower due to a lower on-state voltage
compared to SiC diode. The current fully commutates to SJ
MOSFET only once the SR switch is turned on (see Fig. 9
part (b)).
As discussed above, connecting a fast diode in parallel with
SJ MOSFET has direct impact on the forward diode recovery. Fig. 10 shows additional results for Si diode combined
with modified SR turn-on timing. As shown, shortening the
SR delay time has no impact on the fast current commutation
(from snubber capacitor to parallel diode). This action of SR
switch only hastens the slow current commutation (from parallel diode to SJ switch) and hence the average current in the
parallel diode is reduced. However, this has no significant
impact on the overall conversion eciency and therefore it is
186

IEEJ Journal IA, Vol.2, No.4, 2013

Coping with Poor Performance of SJ MOSFET Body DiodesMartin Pavlovsky et al.

References
(1)

(2)

(3)
(a) SiC parallel diode (IDT16S60C)

(b) Si parallel diode (DSEE29-12CC)

Fig. 9. SJ diode forward recovery with a diode in parallel to SJ MOSFET; Ch1 voltage of main switch S m1
100 V/div, time scale 0.2 s/div; a) Ch3 1/2 current of
S m2 5 A/div, Ch2 current of parallel diode 5 A/div, b)
ChA 1/2 current of S m2 5 A/div, Ch3 current of parallel diode 5 A/div

(4)
(5)
(6)

(7)

(8)

(9)

( 10 )

( 11 )

Fig. 10. SJ diode forward recovery with a fast Si diode


(DSEE29-12CC) in parallel to SJ MOSFET and SR active; Ch1 voltage main switch S m1 100 V/div, Ch3, A,
B, C current of parallel diode with modified timing of
SR switch 5 A/div, time scale 0.2 s/div

( 12 )
( 13 )
( 14 )
( 15 )

not required for a proper converter function.


The experimental waveforms discussed above were measured on a 12.5 kW, 62.5 kHz converter prototype with basic
circuit configuration identical to Fig. 7. In 200 V to 400 V
forward boost mode and output power of 5 kW, the measured
eciencies without the parallel diodes, with SiC diodes and
with Si diodes were 98.6%, 98.8% and 98.7%. This testifies
that the use of parallel diodes as proposed in this paper is
very good in suppressing the ringing while it has a negligible
impact on the conversion eciency.
4.

L. Lorenz, G. Deboy, A. Knapp, and M. Marz: COOLMOSTM a new milestone in high voltage power MOS, Proc. of International Symposium on
Power Semiconductor Devices and ICs, ISPSD, pp.310 (1999)
R. Ng, F. Udrea, K. Sheng, and G.A.J.A. Amaratunga: Study of CoolMOS
integral diode: analysis and optimisation, Proc. International Semiconductor
Conference, CAS, Vol.2, pp.461464 (2001)
M.-A. Kutchak, W. Jantscher, D. Zipprick, and A. Ludsteck-Pechlo: A
new 650 V Super Junction Device with rugged body diode for hard and soft
switching applications, Proc. PCIM Europe, p.68 (2010)
Mastering the Art of Slowness, Application Notes of Infineon,
www.infieon.com
http://www.microsemi.com/datasheets/APTC60HM45SCTG-Rev2.pdf
K. Hongrae, T.M. Jahns, and G. Venkataramanan: Minimization of reverse
recovery eects in hard-switched inverters using CoolMOS power switches,
Proc. Industry Applications Conference, IAS2001, Vol.1, pp.641647 (2001)
M. Pavlovsky, G. Guidi, Y. Tsuruta, and A. Kawamura: Buck/Boost Dc-Dc
Converter with Simple Auxiliary Snubber and Complete Soft Switching in
Whole Operating Region, submitted for IEEE Energy Conversion Congress
and Exposition, ECCE America (2012)
R.W. De Doncker and J.P. Lyons: The auxiliary resonant commutated pole
converter, Proc. Industry Applications Society Annual Meeting 1990, IAS
1990, Vol.2, pp.12281235 (1990)
A. Mousavi, M. Pahlevaninezhad, P. Das, and P. Jain: ZCS PWM bidirectional converter with one auxiliary switch, Proc. Energy Conversion
Congress and Exposition, ECCE 2011, pp.11751180 (2011)
J. Zhang and J.-S. Lai: A synchronous rectification featured soft-switching
inverter using CoolMOS, Proc. Applied Power Electronics Conference and
Exposition, APEC (2006)
H. Yu, X. Huang, and J.-S. Lai, A novel load adaptive ZVS utilizing diode
reverse recovery current for soft-switching choppers, Proc. of Industry Applications Conference, IAS2001. Vol.3, pp.18451850 (2001)
http://www.st.com/internet/com/technical resources/technical literature/data
sheet/CD00222838.pdf
http://www.irf.com/product-info/datasheets/data/irg4psc71ud.pdf
http://www.infineon.com
http://ixdev.ixys.com/DataSheet/DSEE29-12CC.pdf

Martin Pavlovsky (Non-member) received his Ing. degree in Electrical Engineering from Technical University of Kosice,
Slovakia in 2000. In 2006, he received his PhD
degree from Delft University of Technology, The
Netherlands with his PhD work entitled Electronic
Dc Transformer with High Power Density. From
2006 till 2008 as well as from 2011 till 2012, he was
a postdoctoral fellow at Yokohama National University, Japan doing research in the field of highly ecient, high power density converters for electric vehicles. In the year 2009 he was a researcher at Kanagawa Academy of Science
and Technology, Kawasaki, Japan working on Advanced Power Electronics
Project concerning advance drive trains for electric vehicles. He received the
IEEE PELS Transactions Prize Paper Award in 2009.

Conclusions

Slow body diodes of Super Junction MOSFETs may


lead to poor reverse recovery as well as forward recovery
performance. As discussed, the reverse recovery can be controlled in a circuit as shown in Fig. 1. through a proper circuit
design and critical timing of synchronous rectifier switch.
Connecting a fast diode in parallel to SJ MOSFET is proposed to deal with the forward recovery issue. As shown this
solves the recovery problem without the need for a critical
turn-on timing of the synchronous rectifier switch.
The proposed concepts were implemented in a converter
prototype based on the circuit shown in Fig. 7. The circuit
handled poor SJ diode performance very well and it reached
eciencies in 98.5% region in the output power range from
3 kW to 12.5 kW while operating at 62.5 kHz.

Giuseppe Guidi (Non-member) graduated from the University of


LAquila, Italy, in 1995, and received his PhD from
the Norwegian University of Science and Technology
(NTNU) in 2009. He has worked for industry in the
field of Power Electronics from 1997 to 2004, joining first Fuji Electric R&D, Japan, as R&D engineer
and then SIEI SpA, Italy as senior engineer. In 2009,
he joined Yokohama National University as Research
Associate. Since 2011, he is also part-time research
associate with NTNU, Norway. His research interests include power electronics, traction control and drive systems for electric
propulsion, as well as application of power electronics to renewable energy.

187

IEEJ Journal IA, Vol.2, No.4, 2013

Coping with Poor Performance of SJ MOSFET Body DiodesMartin Pavlovsky et al.


Atsuo Kawamura (Senior Member) (S77-M81-SM96-F02) was
born in Yamaguchi, Japan, in December 1953. He received the B.S.E.E., M.S.E.E., and Ph.D. degrees in
electrical engineering from the University of Tokyo,
Tokyo, Japan, in 1976, 1978, and 1981, respectively.
In 1981, he was with the Department of Electrical
and Computer Engineering, University of Missouri,
Columbia as a Postdoctoral Fellow and later as an Assistant Professor from 1983 to 1986. Since 1986, he
is with the Division of Electrical and Computer Engineering, Yokohama National University, Yokohama, Japan, where he was
an Associate Professor at first and in 1996 he became a Professor. His research interests include power electronics, digital control, electric vehicles,
robotics, train traction control, etc. Dr. Kawamura is a member of the Institute of Electrical Engineers of Japan (IEEJ), Robotics Society of Japan, and
several other organizations. He was the conference Chairperson of IPECSapporo-ECCE-Asia in 2010. He received the IEEE IAS Transactions Prize
Paper Award in 1988, the Prize Paper Award of IEE of Japan in 1996, IEEE
IES Transactions Best Paper Awards in 2001 and 2002, and EPE-PEMC
Award in 2008.

188

IEEJ Journal IA, Vol.2, No.4, 2013