MIPI Cadence Presentation

Confidential
MIPI MPHY OVERVIEW

Shri Jaganathan
Solutions Architect
Cadence Design Systems
AGENDA
Introduction
Who is MIPI Alliance
What MIPI Do
MPhy Introduction
TX- Key parameters
RX-Key parameters
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Who is MIPI Alliance?

MIPI drive mobile and mobile-influenced
interface technology through the development of
hardware and software specifications
MIPI work globally and collaboratively with other
standards bodies to benefit the mobile
ecosystem
Copyright 2013 MIPI
What MIPI Do
45+ interface specifications released to date
MIPI has full ecosystem of members to support
many types of mobile and mobile-influenced
designs
Specs are widely adopted for designs across the
mobile industry and beyond
255 members worldwide
Copyright 2013 MIPI
MIPI Overview
MIPI Interfaces / Stack
Camera
Display
UniPortD
UniPortM
Audio/
Data/Ctrl
Control
BB-RF 3G
BB-RF 4G
IPC
Mass
Storage
Trace
Gigabit
Trace
Software
NAND
SW
IMF
DDB
App-control
DCS
ICLC
ICLC
OST FrameWork
SPMI :
RF-FE:
DSI-1
Transport
PHY
6
App-data
App-data
App-data
CSI-2
Power
Mgmt.
D-PHY
D-PHY
serial I/F
serial I/F
PIE
Conf
UniPro
1.0
UniPro
1.5 and
2.0
D-PHY
M-PHY
serial I/
F
serial I/
F
SLIMbus
RF
Control
DigRF
3G
DigRF
4G
Conf
HSI
CMOSbased
CMOSbased
M-PHY
serial I/F
CMOS
UniPro
1.5 and
2.0
OST
TWP
STP
UniPro
1.5 and
2.0
M-PHY
PTI
M-PHY
serial I/F
CMOS
serial I/F
MPHY Specification Overview

M-PHY
V1.0 board approved 08 FEB 2011 1.45Gbps

V2.0 Released on June 2012 extends operation to 2.9Gbps
V3.0 Released on Oct 2013 extends operation to 5.8Gbps
V4.0 expected in 2014 extends operation to 11.6Gbps
Connects Modem DigRF v4 and Memory LLI v1.0 to the Application

Processor
Next generation cameras CSI-3 v0.8, displays DSI-2 v0.1
Joint Standard Development: JEDEC UFS v1.1, USB SSIC v1, PCI Mobile Express
Features
Custom Clock
Self Consistent
Aggressive Power Management
Optical/Repeater ready
M-PHY Introduction: Lane, Link and More
Picture taken from the MPHY specification document

9
M-TX =
TX
Module
M-RX =
RX
Module

10
Lane = unidirectional single-signal

physical channel. Consists of one MTX, one M-RX and one line

11
SUB-LINK = a collection of lanes all in

one direction

12
Link = 2 sublinks (one each in opposite direction) + Lane

management function

13
M-TX State Diagram
14
M-RX State Diagram
15
M-PHY Burst Operation
16
M-PHY V1.0
Power On
Race to Halt Power Heuristics

state
HS Burst
LS Burst
Stall
Sleep
Hibern8
recovery
latency
Disable
power
Hibern8
25mW
1mW
ns
10mW
us
100uW
0.1-1ms 10uW
Sleep
LS Burst
Stall
HS Burst
Assumption: one M-TX and one M-RX (including clock multiplication)

Power
17
M-PHY States
M-PHY Configuration
Using protocol configuration mechanism

Local protocol checks capabilities of local PHY and
receives capabilities of remote PHY
Protocol decision on operation profile
Profile request send to local PHY and via the protocol layer to the remote
PHY using the current PHY operation mode
INIT-PCC cycle through the PHYs will activate the change
Optical converters can be configured by flushing configuration data
during the INIT-PCC cycle
PROT
LOCAL
18
PHY
E/O
E/O
O/E
O/E
PHY
PROT
REMOTE
M-PHY Configuration

PROT
LOCAL
19
PHY
E/O
E/O
O/E
O/E
PHY
PROT
REMOTE
M-PHY Configuration

PROT
??
LOCAL
20
PHY
E/O
E/O
O/E
O/E
PHY
PROT
REMOTE
M-PHY Configuration

PROT
??
LOCAL
21
PHY
E/O
E/O
O/E
O/E
PHY
PROT
REMOTE
M-PHY Configuration

PROT
??
LOCAL
22
PHY
E/O
E/O
O/E
O/E
PHY
PROT
REMOTE
M-PHY Configuration

PROT
??
LOCAL
23
PHY
E/O
E/O
O/E
O/E
PHY
PROT
REMOTE
M-PHY Specification Roadmap
1.45Gbps
M-PHY v1
M-PHY supports :
Bandwidth support
- HS GEAR 1
- PWM G0-G3
- SYSBURST
Bandwidth Provisional
- HS-Gear 2
- PWM G4-G5
2011
2012
2013
2014
v1.
0
v2.0
v3.0
v4.0
2.9Gbps
M-PHY v2
Bandwidth support
- HS GEAR 1 & 2
- PWM G0-G5
-SYSBURST
- HS-Gear 3
- PWM G6-G7
DigRF v4
5.8Gbps
M-PHY v3
Bandwidth support
- HS GEAR 1,2 & 3
- PWM G0-G7
-SYSBURST
HS-Gear 4
CSI-3/Mobile Express
UFS
LLI/SSIC
24
11.6Gbps
M-PHY v4
Bandwidth support
- HS GEAR 1, 2, 3 & 4
- PWM G0-G7
- SYSBURST
DPHY and MPHY Comparison

Feature
Min. number of pins per
direction
Minimum configuration (# of
pins)
Data traffic for minimum
configuration
Medium
25
DPHY
MPHY
Unidirectional or halfduplex
<30 cm PCB, flex,microcoax
dual-simplex
< 30 cm PCB, flex,micro coax,<1.2 m
cable, optical
~ 1.25, 2.5, 5 Gb/s (A series); ~ 1.5, 3,
6 Gb/s (B series)
Data rate per

lane
HS Mode
80 Mb/s - 1.5 Gb/s
LP Mode
< 10 Mb/s
10k-600Mb/s
Electrical
signaling
HS Mode
SLVS - 200 mV
SLVS - 200 mV
LP Mode
LVCMOS - 1.2V
SLVS - 200 mV w/o RX-RT
HS Clocking method
DDR Source-Sync Clk
Embedded Clk
HS Line coding
None or 8b-9b
8b-10b
Power Energy/bit
Low
Lower than DPHY
Receiver Complexity
CDR not required
CDR required
LP only PHYs
Disallowed
Allowed
MIPI M-PHY IP
Key Feature List
High-Speed data transfer per lane
Multiple transmission speed ranges and rates per BURST mode to further scale
bandwidth to application needs; Mitigates interference problems.
Supports both SYS and PWM mode LS operation

Flexibility in data rates
Low power dissipation

Multiple power saving modes, where power consumption can be traded-off
against recovery time
Clocking flexibility: designed to be able to operate with independent local

reference clocks at each side, but suitable to exploit the benefits of a
shared reference clock
Optical friendly: enables low-complexity electro-optical signal conversion
and optical data
Distance: optimized for short interconnect (<10 cm) but extendable to a
meter with good quality interconnect or even further with optical converters
and optical waveguides.
Configurability: differences in supported functionality (to reduce cost) and
tune for best performance (implementation) without hampering
interoperability
26
MPHY Key Features v3.0

Supports 2 Low speed modes
Type-1 (PWM Signaling)
Type-2
Supports 2 amplitude modes

LA
SA
Supports 3 Speed modes and 2 rates per mode

Supports 8b-10b encoding
Supports Termination and no Termination modes
Standard RMMI interface definition
27
PWM Bit waveform and Bit Stream Example
28
Line Conditions and States
29
DIF-P and DIF-N : States during normal operation

and used for data-transmission
30
DIF-Z : Possible only during power-up and powersaving states
31
DIF-Q : Possible only when the M-RX has been

powered off.
32
MPHY TX Architecture
CLK from CMN
Block
HSCLK
LSCLK
RMMI Interface
CFGCLK
HS / LS
FSM
DATA
Interface
PPI
Interface
CTRL
Interface
TX_DP
DATA
Serializer
&
Clock Gen
DATA
PATH
BIST
CONTROL
LOOPBACK
33
BIST
HSCLK
LSCLK
Drive
r+
Term
DRIVERS
TX_DN
MPHY RX Architecture
REFCLK
RX_DP
RX_DN
PREAM P
+
TERM
DATA
De Se rialize r
&
CDR
HS / LS
FSM
LOOPBACK
34
SYMCLK
DATA
DATA
PATH
CONTROL
DATA
Inte rface
PPI
Inte rface
CTRL
Inte rface
RMMI Interface
CFGCLK
REFCLK
HS Amp for
PREAM P
G1/G2/G3
+
RX_DN
TERM
modes
RX_DP
DATA
De Se rialize r
&
CDR
LOOPBACK
DATA
Inte rface
SYMCLK
DATA
DATA
PATH
CONTROL
35
HS / LS
FSM
PPI
Inte rface
CTRL
Inte rface
RMMI Interface
CFGCLK
REFCLK
LP Amp for
PREAM P
low-speed
+
RX_DN
TERM
modes
RX_DP
DATA
De Se rialize r
&
CDR
LOOPBACK
DATA
Inte rface
SYMCLK
DATA
DATA
PATH
CONTROL
36
HS / LS
FSM
PPI
Inte rface
CTRL
Inte rface
RMMI Interface
CFGCLK
REFCLK
Ultra low power DATA

PREAM P
squelch
detector De Se& rialize r
+
RX_DN
TERM
CDR
for Hibernate
mode
RX_DP
CONTROL
LOOPBACK
37
HS / LS
FSM
DATA
Inte rface
SYMCLK
DATA
DATA
PATH
PPI
Inte rface
CTRL
Inte rface
RMMI Interface
CFGCLK
Data Transfer Modes
HS-Gear1
(Mandatory)
AND
HS Mode
HS-Gear2
(Optional)
AND
Data Transfer
Modes
AND
HS-Gear3
(Optional)
PWM Mode
(Type-1)
LS Mode
OR
SYS mode
(Type-2)
38
BIST Details
Comprehensive BIST functionality to

o Ease production testing
o Support standalone bring-up of the IP.
The BIST modules can generate and check various patterns ranging from
simple data ramps to complex jitter-inducing patterns.
BIST
Generator
from
PPI/RMMI
TXP
Encoding
+ Serializer
TXN
Input
Latch
BIST
Select
to
PPI/RMMI
BIST_FLAG
39
Output
Latch
RXP
Decoding
+ Deserializer
BIST
Checker
RXN
BIST Features
Option to
generate and check various patterns like PRBS, CRPAT, CJTPAT
etc.
run the BIST infinitely or in a burst mode.
control the burst length.
control the idle time between bursts, within limits of the MPHY
specification.
send patterns that repeat in every burst or differ in every burst.
inject a single-bit error at a programmable point in the data stream.
Supports observable BIST status

BIST error signal is observable at the IP port if required
BIST error counters are readable as status registers
40
BIST Modes
Burn-in Mode: Stress testing
by putting TX and RX in
maximum power consumption
modes with the help of
external loopback.
Loopback Mode: Provides a
transparent bit-by-bit path
from an M-RX serial input to
an M-TX serial output.
41
MPHY Silicon Validation

No certification or Sigfest
Conformance Test suite (CTS)
Developed as part of the PHY Work group
Defines Test procedures
Tek presentation will have details of this
42

Tx Test setup requirements
20GHz BW Oscilloscope
20GHz Active Probe
Clock Source
Digital IO Source/Capture card
Power supplies & Multimeters
Rx Test setup requirements

BERT (with Datarate of atleast 7.5Gbps)
Rj & Sj Jitter injection capabilities
ISI channel
43

Key Tx Parameters
Jitter Test
Eye Mask Test Channel de-embedding
PWM signal Test
44
Jitter Test
Jitter separation is a time consuming process if Spectral
method is followed to get the exact Jitter separation.
Dual Dirac method can be used to get the Jitter split much
faster and if lesser number of samples can be taken and
extrapolate the RJ numbers to reduce the time much lower.
HS default mode is terminated mode and this has to be a
100ohm differential termination across Dp and Dn. This has
to be measure at the pin. This can be achieved only through
probing directly on a 100ohm terminated very near to the Dp/
Dn pin using an active probe.
Active probes normally have a high noise floor which adds
RJ to the measurement and this is reflected on the TX
measurements
45
Eye Mask Test
G1 and G2 eye diagram
46
G3 Eye Diagram
Impact of active probe noise
47
PWM Test Challenges

Unterminated mode probing
PWM data decoding
48

Key Rx Parameters
Jitter Calibration and Test
PWM signal and PPM Offset Test
49
RX calibration Setup
Physical Calibration Setup
Pattern
Generator
+ Deemphasis
+ Jitter
Sources
Replica
Channel
Active Probe
Oscilloscope
SMA Cables
DUT RX
Block diagram taken from CTS discussion PPT
50
Jitter Mask for G3A

2
1.8
1.6
Total Jitter(UI)
1.4
1.2
1
Spec TJ
0.8
0.6
0.4
0.2
0
0.8
10
26
SJ Frequency(MHz)
51
100
166.4
Jitter Components
RX input should have following components
Low frequency Jitter component as shown in the Jitter Mask
Low frequency RJ
High Frequency RJ
High frequency SJ tone
ISI to meet the Spec defines channel loss
No Channel defined- RX spec is defined at the Pin
52
PWM test and PPM offset

For PWM test data need to be sourced from 10kHz to
576MHz
This test cannot be done directly using a BERT
Sourcing can be done by creating the PWM patterns by
adding 1s and 0s.
BER cannot be measured using BERT for PWM and this
need to be done by an On Chip Error counter or need to be
captured using FPGA and compare. Another option is to
loopback to TX and compare using BER counter in
oscilloscope.
PPM offset cannot be measure in loopback mode because
of data rate mismatch.
53
Questions???
54
Thank You
55

MIPI Cadence Presentation

Transféré par

Informations du document

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

MIPI Cadence Presentation

Transféré par

Droits d'auteur :

Formats disponibles

Confidential

MIPI MPHY OVERVIEW

Who is MIPI Alliance?

Copyright 2013 MIPI

Copyright 2013 MIPI

MIPI Interfaces / Stack

MPHY Specification Overview

V1.0 board approved 08 FEB 2011 1.45Gbps

Connects Modem DigRF v4 and Memory LLI v1.0 to the Application

M-PHY Introduction: Lane, Link and More

Picture taken from the MPHY specification document

M-PHY Introduction: Lane, Link and More

Picture taken from the MPHY specification document

M-PHY Introduction: Lane, Link and More

Lane = unidirectional single-signal

Picture taken from the MPHY specification document

M-PHY Introduction: Lane, Link and More

SUB-LINK = a collection of lanes all in

Picture taken from the MPHY specification document

M-PHY Introduction: Lane, Link and More

Link = 2 sublinks (one each in opposite direction) + Lane

Picture taken from the MPHY specification document

M-TX State Diagram

M-RX State Diagram

M-PHY Burst Operation

Race to Halt Power Heuristics

Assumption: one M-TX and one M-RX (including clock multiplication)

Using protocol configuration mechanism

Using protocol configuration mechanism

Using protocol configuration mechanism

Using protocol configuration mechanism

Using protocol configuration mechanism

Using protocol configuration mechanism

M-PHY Specification Roadmap

DPHY and MPHY Comparison

Data rate per

80 Mb/s - 1.5 Gb/s

SLVS - 200 mV w/o RX-RT

DDR Source-Sync Clk

Lower than DPHY

CDR not required

Supports both SYS and PWM mode LS operation

Low power dissipation

Clocking flexibility: designed to be able to operate with independent local

MPHY Key Features v3.0

Supports 2 amplitude modes

Supports 3 Speed modes and 2 rates per mode

PWM Bit waveform and Bit Stream Example

Line Conditions and States

Line Conditions and States

DIF-P and DIF-N : States during normal operation

Line Conditions and States

DIF-Z : Possible only during power-up and powersaving states

Line Conditions and States

DIF-Q : Possible only when the M-RX has been

Ultra low power DATA

Data Transfer Modes

Comprehensive BIST functionality to

Supports observable BIST status

MPHY Silicon Validation

MPHY Silicon Validation

Rx Test setup requirements

MPHY Silicon Validation

Eye Mask Test