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Overview
In this tutorial a new design of back-to-back power inverters is presented. The design involves the prototyping of power electronics circuitry developed in NI Multisim and NI Ultiboard as well as an
FPGA-based digital controller developed in NI LabVIEW FPGA and targeted to the NI Single-Board RIO 9606 and the NI General Purpose Inverter Controller (GPIC).
Table of Contents
1. Concept and Motivation
2. System Co-simulation
3. Circuit Schematic in Multisim
4. Ultiboard Layout
5. Controller Code & System Performance
6. How to Reconfigure and Order Your Own GPIC Research Board
2. System Co-simulation
A major contributor to the effectiveness of this design is the accurate system desktop co-simulation prior to prototyping. LabVIEW FPGA and Multisim offer a variable time step co-simulation
functionality of the complete system made of the analog plant (including the IGBTs, RLC filter output stage, bridge rectifiers, and precharge contactors) and the FPGA control code (including
RMS/phase calculation, PLL blocks, PWM generation). The power inverter co-simulation code is available in the power electronics design guide.
Co-simulation of this system showed excellent agreement with the acquired measurements from the system prototype. However it helped evaluate the following performance parameters before
prototyping which lead to a single prototype spin to get to the final working hardware design:
Validation of control code
Evaluation of the different values of the PID coefficients in the controller
Evaluation of the needed pre-charge contactors needed to eliminate shoot-through currents in the DC link capacitors
Evaluation of the amount of DC link capacitance needed
Evaluation of different output filter topologies
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GPIC Connectivity
This sub-circuit includes the entire break-out connectors to the GPIC signals ( refer to the GPIC page to learn more about the different I/O lines ). Right-angled headers with pluggable terminal
blocks from Phoenix connectors were chosen to make an easy wire-poke connection.
All the connections to the GPIC I/O pass through jumpers that have to be physically placed at the bottom of the board. This feature is helpful in case these I/O lines need to be used in some other
way.
Also 8 of the +3.3V LVTTL DIO lines are connected to on-board potential dividers in case +5V digital input lines need to be connected to directly to the board (for example, signals from a motor
speed encoder)
Power Supplies
Two supplies are needed to power up the board:
1. -
24-pin +12V ATX power supply to power the digital ground section as well as the sbRIO
2. -
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4. Ultiboard Layout
The analog plant circuitry is prototyped on a custom PCB in Ultiboard. The design maintains complete isolation between the high-power analog signals and the low power digital control signals. To
do so, the board is comprised of three main sections:
1. Digital control section with mating connectors to the GPIC and referenced to D-GND. This section contains the routing of the HBDO signals, break-out connectors for DIO lines, relay control
digital lines, ATX-24pin power supply, opto-couplers and isolated buck converters to power up the inverter and the sensors at the analog side.
2. Analog low-power section containing the feedback signals referenced to P-GND. This section contains the routing of the isolated sensed signals to be sent to the GPIC and it break-out
connectors.
3. Analog high-power section containing the grid inputs, the DC Link capacitors, and the 3-phase outputs of each inverter. It also contains circuitry of thermistors and relays to digitally control the
in-rush current into the DC link capacitors.
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