[CSM51A F10] Homework 7 Solutions

Assigned: 11/12/10 Due: 11/19/10

TAs: Pouya Dormiani (pouya@cs.ucla.edu), Jet Jiang (jetjiang@cs.ucla.edu)
Homework is due beginning of discussionno exceptions!

Problem 1
Using 4-bit max/min module to find the fifth largest number of seven 4-bit numbers. A 4-bit max/min module
has inputs x3 x2 x1 x0 and y3 y2 y1 y0 and outputs z3max z2max z1max z0max , z3min z2min z1min z0min , where z min = min(x, y) and
z max = max(x, y). Use hierarchy in your design, there is no limit to the number of modules you can use, but strive
for an efficient design.
Solution:
We can construct bigger and bigger sort networks by using a hierarchical approach, the underlying algorithm
being selection sort. The intuition is that a list of numbers could be sorted by finding its maximum, then finding
the maximum of the remaining numbers and so forth. This approach can be further improved by also finding the
minimum.
2-sort
a b

4-sort
a b
c d

M m

M m

M m

7-sort

a b

6-sort
c d

e f

a b

c d

e f

M m

M m

M m

M m

M m

M m

M m

M m

M m

M m

M m

M m

m M

M m

M m

M m

4-sort
Note, you need the last module:
If b > c, then it would not work, e.g.
11 10

7 5

M m

M m

11

10 5

M m

11

M m

M m

M m

M m

6-sort
th

5 Largest

M m

M m

7 10

The dependency chain can be propagated up from the fifth output to remove any unnecessary max/min
modules.

Problem 2
What patterns does the following circuit NOT recognize? Assume the circuit is initialized in state s1 s0 = 00.
(The single input NAND gate is simply implementing a NOT.)
1

z(t)
x(t)

s1
K

s0

Q
Q

clk

Solution:
s1 (t + 1) = J(t)Q0 (t) + K 0 (t)Q(t)
= xs01 + xs1 = x
s0 (t + 1) = s1 s00 + s1 s0 = s1
z(t) = (xs00 )0 = x0 + s0
We can form a truth table from these expressions,
s1 (t)s0 (t)

00
01
10
11

x
0

00/1
00/1
01/1
01/1

10/0
10/1
11/0
11/1

s1 (t + 1)s0 (t + 1), z(t)

The state machine corresponding to this binary specification is shown below.
1/1

0/1

1/1

1/0

0/1
00

0/1

01

10

11

0/1

1/0

Patterns which it doesnt recognize correspond to input sequences for which an output of zero is generated.
We can see that from the initial state, the patterns which the machine does not recognize are 1, and 11, i.e., either
a single, or two consecutive ones.

Problem 3
Implement a 4-bit coincidence decoder using a 3-bit and 2-bit decoder. How many AND gates do you need?
Solution:

x0

2-bit
Decode
3 2 1 0

x3

x1

3-bit
Decode

0
1
2

11

10

13

12

15

14

...

x2

Problem 4
Analyze the timing characteristic of the following sequential system. The propagation delay for the state register
is tp (cell) = 0.5ns, and the setup time is tsu (cell) = 0.3ns. The network input x stabilizes within tin = 4.0ns after
the triggering edge of the clock; the output z needs to be stable for tout = 3.0ns before the next triggering edge.
For module B1, d1x = 3.5ns, d1y = 5.0ns. For module B2, d2 = 4.2ns.

System A

C LK

B1

register

System B

C LK

B2

System C

C LK

1. Assume no clock skew in the network, what is the maximum clock frequency for the network?
Solution: There are three paths from two adjacent clocks: CLKA x B1 CLKregister , CLKregister
y B1 CLKregister , and CLKregister y B2 z CLKC . The duration along each path is:
tin + d1x + tsu (cell), tp (cell) + d1y + tsu (cell), and tp (cell) + d2 + tout respectively. Therefore we have the

bottleneck as:
Tmin = max(tin + d1x + tsu (cell), tp (cell) + d1y + tsu (cell), tp (cell) + d2 + tout )
= max(4.0 + 3.5 + 0.3, 0.5 + 5.0 + 0.3, 0.5 + 4.2 + 3.0)
= 7.8ns

fmin =

1
128.2MHz
7.8 109

2. Now assume there is clock skew. In particular, the clock signal comes to System C first, and after 0.4ns comes
to System B, and after yet another 0.2ns comes to System A. Then what is the maximum clock frequency
for the network?
Solution: We have to compensate for the clock skew. In particular, for path CLKA x B1 CLKregister
we have to slow down 0.2ns; for path CLKregister y B2 z CLKC we have to slow down 0.4ns.
Then the new bottleneck is:
Tmin = max(tin + d1x + tsu (cell) + 0.2, tp (cell) + d1y + tsu (cell), tp (cell) + d2 + tout + 0.4)
= max(4.0 + 3.5 + 0.3 + 0.2, 0.5 + 5.0 + 0.3, 0.5 + 4.2 + 3.0 + 0.4)
= 8.1ns

fmin =

1
123.5MHz
8.1 109

Problem 5
Using a 4-input decoder and a 16-input encoder to build a device which converts BCD code to 2421 code.
digit

BCD

2421

0
1
2
3
4
5
6
7
8
9

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001

0000
0001
0010
0011
0100
1011
1100
1101
1110
1111

Solution: The design is as follows. Think about why?

0
1
2
3

0
1
2
3
4
5
6
7
D ec 8
9
10
11
12
13
14
15

0
1
2
3
4
0
5
6
1
7
Enc
8
2
9
10
3
11
12
13
14
15

Problem 6
P
Implement the function f (a, b, c, d) = m(1, 3, 5, 7, 10, 14) using a 4-input multiplexer, with a, b as select signals.
You can use NAND gates to generate the input logic for the multiplexer. Assume complemented variables and
constants are available.
Solution:
X
f (a, b, c, d) =
m(1, 3, 5, 7, 10, 14)
= a0 b0 c0 d + a0 b0 cd + a0 bc0 d + a0 bcd + ab0 cd0 + abcd0
= (a0 b0 )(c0 d + cd) + (a0 b)(c0 d + cd) + (ab0 )(cd0 ) + (ab)(cd0 )
= (a0 b0 )d + (a0 b)d + (ab0 )(cd0 ) + (ab)(cd0 )
= m0 (a, b)d + m1 (a, b)d + m2 (a, b)(cd0 ) + m3 (a, b)(cd0 )

The final setup looks like:

d

0
1

c
d'

M UX

3
a

Problem 7
Given the following sequential network, complete the following state transition/output table.

QA

M UX

T A

Q
Q'

QA

Q A'

X
QA

QB

M UX

T B

Q
Q'

M UX

QB

Q B'

QA (t)QB (t)

XY
00

01

10

11

00
01
10
11
QA (t + 1)QB (t + 1), Z
Solution: For clarity, we construct truth tables for TA and TB separately:
QA (t)QB (t)
00
01
10
11

XY

QA (t)QB (t)

00

01

10

11

0
0
0
0

1
1
1
1

0
0
1
1

0
0
1
1

00
01
10
11

XY
00

01

10

11

0
0
1
1

0
0
1
1

0
1
0
1

0
1
0
1

TA (t)

TB (t)

Together with T flip-flops output truth table, we have the following NS outputs:
QA (t)QB (t)
00
01
10
11

XY

QA (t)QB (t)

00

01

10

11

0
0
1
1

1
1
0
0

0
0
0
0

0
0
0
0

00
01
10
11

QA (t + 1)

XY
00

01

10

11

0
1
1
0

0
1
1
0

0
0
0
0

0
0
0
0

QB (t + 1)

Therefore, altogether we have:

QA (t)QB (t)
00
01
10
11

XY
00

01

10

11

00,1
01,0
11,1
10,0

10,1
11,0
01,1
00,0

00,1
00,1
00,1
00,1

00,1
00,1
00,1
00,1

QA (t + 1)QB (t + 1), Z