IAF 0610 Hardware Test Design Coursework

TALLINN
UNIVERSITY OF TECHNOLOGY
Department of Computer Engineering

Erik Kaju
132643IASM

Design for test (IAF 0610)

Variant 12 Coursework

Tallinn 2014
Design of a combinational circuit for the following functionality

if x = 0, z = 0, then Y = k1A + k2B, else
if x = 0, z = 1, then Y = k3A - k1C, else
if x = 1, z = 0, then Y = (k1A k1B k2C) (k3C NOT (k3A) k1B), else
if x = 1, z = 1, then Y = k4A2 + k5A + k6
In order to avoid confusion, then using the boolean operation priority (from high to
low: NOT, (AND), (OR) ) I add parenthesis in the following way:
if x = 0, z = 0, then Y = k1A + k2B, else
if x = 0, z = 1, then Y = k3A - k1C, else
if x = 1, z = 0, then Y = (k1A (k1B k2C)) (k3C (NOT (k3A) k1B)), else
if x = 1, z = 1, then Y = k4A2 + k5A + k6
Then, given variant 12 I use the following coefficients k1=0; k2=k3=1; k4=1,5;
k5=0,8; k6=0,5. Because 1 means inversion and 0 means the lack of inversion on every
bit of the word, the functionality the following form:
1. if x = 0, z = 0, then Y = A + NOT(B), else
2. if x = 0, z = 1, then Y = NOT(A) - C, else
3. if x = 1, z = 0, then Y = (A (B NOT(C) )) (NOT (C) (A B)), else
4. if x = 1, z = 1, then Y = 1,5*A + 0,8 *A + 0,5
Quadratic equation function (fourth)

I started with finding out the last (x=1, z=1) function's Y = 1,5*A2 + 0,8 *A + 0,5
limit:
A
A(3 downto 0) Y
Y round
Y (3 downto 0)
0000
0,5
0001
0001
2,8
0011
0010
8,1
1000
0011
16,4
15
1111
0100
27,7
15
1111
0101
42
15
1111
0110
59,3
15
1111
0111
79,6
15
1111
8 or
higher
1000
15
1111
102,9
Because every bit of Y can have either 0 or 1, we need to build a total of 4 Karnaugh
maps for Y(0) to Y(3).
Y(0):
Karnaugh map:
A(3)A(2)
Y(0)
A(1)A
(0)
00
01
10
11
00
01
10
11

Formula:
Y(0) = ! (!A3 AND !A2 AND A1 AND !A0)

Schematic:
Figure 1 - Observability points O1 and O2 were used later
Y(1):
Karnaugh map:
A(3)A(2)
Y(0)
A(1)A
(0)
00
01
10
11
00
01
10
11

Formula:
Y(1) = ! (!A3 AND !A2 AND !A0)

Schematic:
Y(2):
Karnaugh map:
A(3)A(2)
Y(0)
A(1)A
(0)
00
01
10
11
00
01
10
11

Formula:
Y(2) = A3 OR A2 OR (A1 AND A0)

Schematic:
Y(3):
Karnaugh map:
A(3)A(2)
Y(0)
A(1)A
(0)
00
01
10
11
00
01
10
11

Formula:
Y(3) = A3 OR A2 OR A1

Schematic:
Next a quadratic equation function was compiled:
Logic function (third)

The implementation of third function was analogous to quadratic equation functions
one. At first reusable logic 1bit function was exported as cellview.

Then this 1bit logic was applied for each of four bits of A, B and C.
Adder function (first)

The implementation of complete adder function includes 4 single bit adders: two
of them full 1bit adders, one 1bit adder without carry in signal and one 1bit adder
without carry out signal.

Figure 2 - 1bit adder without carry in
Figure 3 - 1bit full adder with both carry in/out signals
Figure 4 - 1bit adder without carry out
Figure 5 - complete adder function
Subtractor function (second)
For subtractor function 1bit full adder and 1bit adder without carry out signal were reused and
in addition to that a 1 bit subtractor without carry in option was introduced:

Figure 6 1bit subtractor (1bitfulladderWOCINSUB on complete subtractor function), no carry in signal
Figure 7 - complete subtractor function
Main circuit
Figure 8 - Main circuit, 4bit output bus interface
Figure 9 - Main circuit, 2bit output interface
Figure 10 - Main circuit, 1bit output interface
When circuits were created in Cadence I exported them into EDIF 200 format. Then I ran the
ttimport tool to convert them to *.AGM format.
Then I generated fault tables using ttgenerate -fault_table circuitInterfaceX command and got
100% fault coverage.
I started modifying an output *.tst file by removing patterns and table records one by one until I
reached the state with two faults uncovered.
To improve the testability of the circuit, I had to find untestable points in my circuit. I executed
the command ttreport -not_tested circuitInterfaceX. On each of three interfaces, the same pair
of faults was recognized as not tested.
erik.kaju/cadence> ttreport -not_tested
maincircuit4OP1
Generating Report
Reading SSBDD-model file
maincircuit4OP1.agm... OK
Reading test patterns file
maincircuit4OP1.tst... OK
Not tested faults:
Node 182 (_124_I3_124_I0_124_I2>a): sa-0

Node 183 (_124_I3_124_I0_124_I3>a): sa-0
As it turned out, Y(0) formula subfunction of quadratic function contained untestable faults.
necessary observability points were added quadratic sub-circuit (I3), 0-bit subcircuit (I0) to
inverters I2 and I3
Figure 11 - main circuit with observability points two distinct outputs OP2
Figure 12 - main circuit with observability points outputs xored OP1
Fault coverage:
100
80
Original
60
OP1
40
OP2
20
0
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
Figure 13 - fault coverage: original main circuit, main circuit with OP1, main circuit with OP2
Length
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Original
9,308511
18,085106
27,12766
34,308511
37,234043
42,287234
47,074468
52,393617
55,319149
57,446809
58,510638
60,106383
62,234043
62,765957
64,095745
64,893617
65,425532
66,223404
69,946809
72,074468
72,87234
73,93617
74,468085
75,265957
78,723404
79,787234
81,117021
81,382979
83,244681
83,776596
84,574468
85,37234
85,638298
85,904255
86,170213
86,702128
90,159574
90,691489
92,553191
93,351064
95,744681
96,276596
96,808511
97,606383
98,138298
98,93617
99,468085
99,734043
100
OP1
10,051546
18,556701
27,319588
35,051546
38,659794
43,556701
48,195876
53,350515
56,185567
58,247423
59,278351
60,824742
62,886598
63,402062
64,690722
65,979381
66,494845
67,268041
70,876289
72,938144
73,71134
74,742268
75,257732
76,030928
79,381443
80,412371
81,701031
81,958763
83,762887
84,278351
85,051546
85,824742
86,082474
86,340206
86,597938
87,113402
90,463918
90,979381
92,783505
93,556701
95,876289
96,391753
96,907216
97,680412
98,195876
98,969072
100
100
100
OP2
9,308511
18,085106
27,12766
34,308511
37,234043
42,287234
47,074468
52,393617
55,319149
57,446809
58,510638
60,106383
62,234043
62,765957
64,095745
64,893617
65,425532
66,223404
69,946809
72,074468
72,87234
73,93617
74,468085
75,265957
78,723404
79,787234
81,117021
81,382979
83,244681
83,776596
84,574468
85,37234
85,638298
85,904255
86,170213
86,702128
90,159574
90,691489
92,553191
93,351064
95,744681
96,276596
96,808511
97,606383
98,138298
98,93617
99,468085
99,734043
100
It can be seen that adding either separate or single

pins for observability points does not make much
difference. To be precise, it was a bit surprising that
results with separate observability pins were equal
to testing on original circuit. This graph shows that
when adding observability points and linking them
into single pin, it makes fault coverage in small
number of test visibly better, but it is most
probably related to the fact that additional xor gate
is always visible. Improvement over there is rather
deceptive.
But it is clear that it takes less patterns to reach
100% fault coverage. 49 patterns for original
circuit and 47 for the one with observability points
and single pin.
BILBO (Built-in Logic Block Observer)

Because the circuit has 14 input pins, I first found primitive 14-bit polynomial for LFSR-I, which
is 10000000001101. Below is the table for experiments starting with primitive polynomial:
ttbist -ginit 00000000000001 -gpoly 10000000001101 446
-ainit 00000000000001 -apoly 10000000001101 simul bilbo -optimize maincircuit4
100%
ttbist -ginit 00000000000001 -gpoly

11001011110001 -ainit 00000000000001 -apoly
11001011110001 -simul bilbo -optimize
maincircuit4
115
100%

164
10010101001001 -ainit 00000000000001 -apoly
10010101001001 -simul bilbo -optimize maincircuit4
100%

2
10001100010010 -ainit 00000000000001 -apoly
11.7%

191
00110011100101 -ainit 00000000000001 -apoly
100%

535
11001100011101 -ainit 00000000000001 -apoly
100%

2
10011011001010 -ainit 00000000000001 -apoly
11.7%

384
11110110101001 -ainit 00000000000001 -apoly
100%

2
10001100110010 -ainit 00000000000001 -apoly
11.7%

2
01001100110010 -ainit 00000000000001 -apoly
11.7%

Number of BILBO gates:
LFSR of the generator is 14bit, the best possible analyzer is 1bit => overall LFSR amount is
15bit. Each bit needs one 6-gate flip flop, 15*6=90. Also there should be a counter that can
count up to 115, therefore it must be a 7bit counter. 7bit counter contains 7 flip-flops and also 7
gates, (7*6)+7=49. Overall number of BILBO gates is 90+49=139.
CSTP (Circular Self Test Path)

10000000001101 -ainit 00000000000001 -apoly
10000000001101 -simul cstp -optimize maincircuit4
23
56.9%

11001011110001 -ainit 00000000000001 -apoly
45
92.2%

10010101001001 -ainit 00000000000001 -apoly
174
97.6%

10001100010010 -ainit 00000000000001 -apoly
72
93.4%

00110011100101 -ainit 00000000000001 -apoly
60
91.5%

11001100011101 -ainit 00000000000001 -apoly
35
85.1%

10011011001010 -ainit 00000000000001 -apoly
112
98.7%

11110110101001 -ainit 00000000000001 -apoly
163
98.9%

10001100110010 -ainit 00000000000001 -apoly
83
93.9%

01001100110010 -ainit 00000000000001 -apoly
178
99.7%

Number of CSTP gates:
Although 100% wasnt reached, I assume that there might be some tests that could give such
result and number of vectors would fit into 9bit counter. The LFSR of generator/analyzer is
14bits. Every bit needs single 6-gate flip-flop, therefore 14*6=84. Also a 9bit counter is added,
therefore (9*6)+9=63. The overall CSTP gate number is 84+63=147.

Conclusion:
Number of CSTP gates is 5,4% higher compared to BILBO. Also it looks that BILBO needs
smaller counter for reaching 100% FC. BILBO is a preferred option.

Design of the signature analyzer

The best set found in BILBO task would be the following, which only uses 115 vectors to reach
100% coverage.
ttbist -ginit 00000000000001 -gpoly 11001011110001 -ainit 00000001 -apoly 11110001 -
simul bilbo -optimize maincircuit4

115
100%
11001011110001 -ainit 00000000000001 -apoly
11001011110001 -simul bilbo -optimize
maincircuit4
115
11001011110001 -ainit 00000001 -apoly 11110001
-simul bilbo -optimize maincircuit4
100%

11001011110001 -ainit 0001 -apoly 0001 -simul
bilbo -optimize maincircuit4
115
100%

127
11001011110001 -ainit 01 -apoly 01 -simul bilbo optimize maincircuit2
100%

11001011110001 -ainit 1 -apoly 1 -simul bilbo optimize maincircuit1

100%
127
Percentage
120%
100%
80%
60%
Percentage
40%
20%
0%
14

As we can see, we can successfully get 100% coverage even for small signature analyzers.
Hybrid test (4+ bit interface)

Stored Test length
seeds
49
49
34
36
30
45
25
43
22
41
60
20
47
40
15
51
10
74
80
97
99
115
Test length
120
100
80
Test length
20
0
49 34 30 25 22 20 15 10 6

On this graph an optimal point could be chosen, based on known costs. However, when taking a
path of using more than one seed, it must be considered that increase in size would jump due to
introduction of counters, ROM and multiplexers.
I would prefer to have two proposed options:
hardware cost effective: Stored seeds: 1, Test length: 115
speed effective: Stored seeds: 34, Test length: 36

Conclusion

I wouldnt consider adding extra observability points as this does not improve the testability of
given circuit. All gates are observable
In case of BILBO vs CSTP, in current case I would choose BILBO. BILBO-s architecture is more
effective than CSTP and in addition to that for CSTP we need more time to carry out the test.
Although no weights of time vs vector storing were given, I assume that lest length of 115
vectors with single seed is the best optimal choice, given that nowadays most chips work in
MHz range and 115 clock cycles would take very little time to execute and is probably suitable
in most cases.

ROM
Counter

14-bit
Test
Pattern
Generator
Unit
Under
Test
4-bit
Signature
Analyzer
CL

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TALLINN

Design for test (IAF 0610)

Design of a combinational circuit for the following functionality

4. if x = 1, z = 1, then Y = 1,5*A + 0,8 *A + 0,5

Quadratic equation function (fourth)

Figure 1 - Observability points O1 and O2 were used later

Next a quadratic equation function was compiled:

Logic function (third)

Adder function (first)

Figure 2 - 1bit adder without carry in

Figure 3 - 1bit full adder with both carry in/out signals

Figure 4 - 1bit adder without carry out

Figure 5 - complete adder function

Subtractor function (second)

Figure 6 1bit subtractor (1bitfulladderWOCINSUB on complete subtractor function), no carry in signal

Figure 7 - complete subtractor function

Figure 8 - Main circuit, 4bit output bus interface

Figure 9 - Main circuit, 2bit output interface

Figure 10 - Main circuit, 1bit output interface

Node 182 (_124_I3_124_I0_124_I2>a): sa-0

Figure 12 - main circuit with observability points outputs xored OP1

It can be seen that adding either separate or single

BILBO (Built-in Logic Block Observer)

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

CSTP (Circular Self Test Path)

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

Design of the signature analyzer

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

ttbist -ginit 00000000000001 -gpoly

Hybrid test (4+ bit interface)

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4. if x = 1, z = 1, then Y = 1,5A + 0,8 A + 0,5