Inverter (logic gate)

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INPUT OUTPUT

Traditional NOT Gate (Inverter) symbol

NOT A

International Electrotechnical Commission NOT Gate (Inverter) symbol

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shown on the right.
Electronic implementation[edit]

NMOS inverter

PMOS inverter

Static CMOS inverter

NPN transistortransistor logicinverter

Depletion-load NMOS logic NAND

Saturated-load NMOS inverter

NPN resistortransistor logicinverter

An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be constructed using a
single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this 'resistive-drain' approach uses only a single type
of transistor, it can be fabricated at low cost. However, because current flows through the resistor in one of the two states, the resistivedrain configuration is disadvantaged for power consumption and processing speed. Alternatively, inverters can be constructed using
two complementary transistors in a CMOS configuration. This configuration greatly reduces power consumption since one of the
transistors is always off in both logic states. Processing speed can also be improved due to the relatively low resistance compared to
the NMOS-only or PMOS-only type devices. Inverters can also be constructed withbipolar junction transistors (BJT) in either a resistor
transistor logic (RTL) or a transistortransistor logic (TTL) configuration.
Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see binary). An inverter circuit serves as the
basic logic gate to swap between those two voltage levels. Implementation determines the actual voltage, but common levels include
(0, +5V) for TTL circuits.
Digital building block[edit]

This schematic diagram shows the arrangement of NOT gates within a standard 4049 CMOS hex inverting buffer.
The inverter is a basic building block in digital electronics. Multiplexers, decoders, state machines, and other sophisticated digital
devices may use inverters.
The hex inverter is an integrated circuit that contains six (hexa-) inverters. For example, the 7404 TTL chip which has 14 pins and the
4049 CMOSchip which has 16 pins, 2 of which are used for power/referencing, and 12 of which are used by the inputs and outputs of
the six inverters (the 4049 has 2 pins with no connection).
Alternatives[edit]
If no specific NOT gates are available, one can be made from NAND or NOR gates, because NAND and NOR gates are considered the
[1]
"universal gates", meaning that they can be used to make all the others.
NAND construction
NOR construction

Performance measurement[edit]

Voltage transfer curve for a 20 m inverter constructed at North Carolina State University
Digital inverter quality is often measured using the voltage transfer curve (VTC), which is a plot of output vs. input voltage. From such a
graph, device parameters including noise tolerance, gain, and operating logic levels can be obtained.
Ideally, the VTC appears as an inverted step function this would indicate precise switching between on and off but in real devices, a
gradual transition region exists. The VTC indicates that for low input voltage, the circuit outputs high voltage; for high input, the output
tapers off towards the low level. The slope of this transition region is a measure of quality steep (close to infinity) slopes yield precise
switching.
The tolerance to noise can be measured by comparing the minimum input to the maximum output for each region of operation (on / off).
The OR gate is a digital logic gate that implements logical disjunction - it behaves according to the truth table to the right. A HIGH
output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is high, a LOW output (0) results. In another sense,
the function of OR effectively finds the maximumbetween two binary digits, just as the complementary AND function finds
[1]
the minimum.
Symbols[edit]
There are two symbols for OR gates: the American (ANSI or 'military') symbol and the IEC ('European' or 'rectangular') symbol, as well
[2][3]
as the deprecated DIN symbol.
For more information see Logic Gate Symbols.

MIL/ANSI Symbol

IEC Symbol

DIN Symbol

This schematic diagram shows the arrangement of OR gates within a standard 4071 CMOS integrated circuit.
Hardware description and pinout[edit]
OR Gates are basic logic gates, and as such they are available in TTL and CMOS ICs logic families. The standard 4000
series CMOSIC is the 4071, which includes four independent two-input OR gates. The traditional TTL version is the 7432. There are
many offshoots of the original 7432 OR gate. All have the same pinout but different internal architecture, allowing them to operate in
different voltage ranges and/or at higher speeds. In addition to the standard 2-Input OR Gate, 3- and 4-Input OR Gates are also
available. In the CMOS series, these are:
4075: Triple 3-Input OR Gate
4072: Dual 4-Input OR Gate
TTL variations include:
74LS32: Quad 2-input OR gate (Low power Schottky version)
74HC32: Quad 2-input OR gate (High Speed CMOS version) - has lower current consumption/wider Voltage range
74LVC32: Low voltage CMOS version of the same.
Implementations[edit]

NMOS OR gate
CMOS OR gate

OR gate using diodes

OR gate usingtransistors

Alternatives[edit]
If no specific OR gates are available, one can be made from NAND or NOR gates in the configuration shown in the image below. Any
logic gate can be made from a combination of NAND or NOR gates.
NAND Construction
NOR construction

Wired-OR[edit]

Wired OR gate using open-collector NOR gates

With active low open collector logic outputs, as used for control signals in many circuits, an OR function can be produced by wiring
together several outputs. This arrangement is called a wired OR. This implementation of an OR function typically is also found in
integrated circuits of N or P-type only transistor processes.
The AND gate is a basic digital logic gate that implements logical conjunction - it behaves according to the truth table to the right. A
HIGH output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one input to the AND gate is HIGH, a
LOW output results. In another sense, the function of AND effectively finds the minimum between two binary digits, just as
the OR function finds the maximum. Therefore, the output is always 0 except when all the inputs are 1s.
Symbols[edit]
There are three symbols for AND gates: the American (ANSI or 'military') symbol and the IEC ('European' or 'rectangular') symbol, as
well as the deprecated DIN symbol. For more information see Logic Gate Symbols.

MIL/ANSI Symbol IEC Symbol

DIN Symbol

The AND gate with inputs A and B and output C implements the logical expression
Implementations[edit]

NMOS AND gate

AND gate using diodes AND gate using transistors

An AND gate is usually designed using N-channel (pictured) or P-channel MOSFETs. The digital inputs a and b cause the output F to
have the same result as the AND function.
Alternatives[edit]
If no specific AND gates are available, one can be made from NAND or NOR gates, because NAND and NOR gates are considered the
[1]
"universal gates," meaning that they can be used to make all the others. XOR Gates can also be used to simulate AND functions, but
are rarely used to do so.
Desired gate
NAND construction
NOR construction

The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the right. A HIGH output (1)
results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOW output (0) results. NOR is the result of

the negation of the OR operator. It can also be seen as an AND gate with all the inputs inverted. NOR is a functionally
complete operationNOR gates can be combined to generate any other logical function. By contrast, the OR operator is monotonic as
it can only change LOW to HIGH but not vice versa.
In most, but not all, circuit implementations, the negation comes for freeincluding CMOS and TTL. In such logic families, OR is the
more complicated operation; it may use a NOR followed by a NOT. A significant exception is some forms of the domino logic family.
The original Apollo Guidance Computer used 4,100 ICs, each one containing only a single 3-input NOR gate.
Symbols[edit]
There are three symbols for NOR gates: the American (ANSI or 'military') symbol and the IEC ('European' or 'rectangular') symbol, as
well as the deprecated DIN symbol. For more information see Logic Gate Symbols.

MIL/ANSI Symbol

IEC Symbol

DIN Symbol

In digital electronics, a NAND gate (Negated AND or NOT AND) is a logic gate which produces an output that is false only if all its
inputs are true; thus its output is complement to that of the AND gate. A LOW (0) output results only if both the inputs to the gate are
HIGH (1); if one or both inputs are LOW (0), a HIGH (1) output results. It is made using transistors.
The NAND gate is significant because any boolean function can be implemented by using a combination of NAND gates. This property
is called functional completeness.
Digital systems employing certain logic circuits take advantage of NAND's functional completeness.
The function NAND(a1, a2, ..., an) is logically equivalent to NOT(a1 AND a2 AND ... AND an).
Symbols[edit]
There are three symbols for NAND gates: the MIL/ANSI symbol, the IEC symbol and the deprecated DIN symbol sometimes found on
old schematics. For more information see logic gate symbols.

MIL/ANSI Symbol
IEC Symbol
DIN Symbol
Hardware description and pinout[edit]
NAND gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs.

This schematic diagram shows the arrangement of NAND gates within a standard 4011 CMOS integrated circuit.
CMOS version[edit]
The standard, 4000 series, CMOS IC is the 4011, which includes four independent, two-input, NAND gates.
Availability[edit]
These devices are available from most semiconductor manufacturers such as Fairchild Semiconductor, Philips or Texas Instruments.
These are usually available in both through-hole DIL and SOIC format. Datasheets are readily available in most datasheet databases.
The standard 2-, 3-, 4- and 8-input NAND gates are available:
CMOS
4011: Quad 2-input NAND gate
4023: Triple 3-input NAND gate
4012: Dual 4-input NAND gate
4068: Mono 8-input NAND gate
TTL
7400: Quad 2-input NAND gate
7410: Triple 3-input NAND gate
7420: Dual 4-input NAND gate

7430: Mono 8-input NAND gate

Implementations[edit]
The NAND gate has the property of functional completeness. That is, any other logic function (AND, OR, etc.) can
[1]
be implemented using only NAND gates. An entire processor can be created using NAND gates alone. In TTL ICs using multipleemitter transistors, it also requires fewer transistors than a NOR gate.

NMOS NAND
gate

CMOS NAND
gate

TTL NAND gate

Die of a 74AHC00D quad 2-input NAND

The physical
layout of a CMOS gate manufactured by NXP
Semiconductors.
NAND

Alternatives[edit]
If no specific NAND gates are available, one can be made from NOR gates, because NAND and NOR gates are considered the
[1]
"universal gates", meaning that they can be used to make all the others.
NOR construction

The XOR gate (sometimes EOR gate, or EXOR gate and pronounced as Exclusive OR gate) is a digital logic gate that implements
an exclusive or; that is, a true output (1/HIGH) results if one, and only one, of the inputs to the gate is true. If both inputs are false
(0/LOW) or both are true, a false output results. XOR represents the inequality function, i.e., the output is true if the inputs are not alike
otherwise the output is false. A way to remember XOR is "one or the other but not both".
XOR can also be viewed as addition modulo 2. As a result, XOR gates are used to implement binary addition in computers. A Half
[1]
adder consists of an XOR gate and an AND gate. Other uses include substractors, comparators, and controlled inverters.
The algebraic expressions
and
(
The behavior of XOR is summarized in the truth table shown on the right.

) both represent the XOR gate with inputs A and B.

CMOS XOR gate

Symbols[edit]
There are two symbols for XOR gates: the traditional symbol and the IEEE symbol. For more information see Logic Gate Symbols.

Traditional XOR Symbol

IEEE XOR Symbol

The logic symbols and can be used to denote XOR in algebraic expressions.

C-like languages use the caret symbol ^ to denote bitwise XOR. (Note that the caret does not denote logical conjunction (AND) in these
languages, despite the similarity of symbol.)
Alternatives[edit]
If a specific type of gate is not available, a circuit that implements the same function can be constructed from other available gates. A
circuit implementing an XOR function can be trivially constructed from an XNOR gate followed by a NOT gate. If we consider the
expression
, we can construct an XOR gate circuit directly using AND, OR and NOT gates. However, this
approach requires five gates of three different kinds.
An XOR gate circuit can be made from four NAND or five NOR gates in the configurations shown below . In fact, both NAND and NOR
gates are so-called "universal gates," and any logical function can be constructed from either NAND logic or NOR logic alone.
As an alternative, if different gates are available we can apply Boolean algebra to transform
(
) as stated above, and apply de Morgan's Law to the last term to get
implemented using only three gates as shown below.

which can be

XOR gate circuit constructed using only NAND gates.

XOR gate circuit constructed using only NOR gates.

XOR gate circuit using three mixed gates

More than two inputs[edit]
Strict reading of the definition of exclusive or, or observation of the IEC rectangular symbol, raises the question of correct behaviour
with additional inputs. If a logic gate were to accept three or more inputs and produce a true output if exactly one of those inputs were
true, then it would in effect be a one-hot detector (and indeed this is the case for only two inputs). However, it is rarely implemented this
way in practice.
It is most common to regard subsequent inputs as being applied through a cascade of binary exclusive-or operations: the first two
signals are fed into an XOR gate, then the output of that gate is fed into a second XOR gate together with the third signal, and so on for
any remaining signals. The result is a circuit that outputs a 1 when the number of 1s at its inputs is odd, and a 0 when the number of
incoming 1s is even. This makes it practically useful as a parity generator or a modulo-2 adder.
[2]
For example, the 74LVC1G386 microchip is advertised as a three-input logic gate, and implements a parity generator.
Applications[edit]
Uses in addition[edit]
The XOR logic gate can be used as a one-bit adder that adds any two bits together to output one bit. For example, if we
add 1 plus 1 in binary, we expect a two-bit answer, 10(i.e. 2 in decimal). Since the trailing sum bit in this output is achieved with XOR,
the preceding carry bit is calculated with an AND gate. This is the main principle in Half Addersand the combined AND-XOR circuit may
be chained together in order to add ever longer binary numbers.

Example half adder circuit diagram

Pseudo-random number generation[edit]
Pseudo-random number (PRN) generators, specifically Linear feedback shift registers, are defined in terms of the exclusive-or
operation. Hence, a suitable setup of XOR gates can model a linear feedback shift register, in order to generate random numbers.
Correlation and sequence detection[edit]
XOR gates produce a 0 when both inputs match. When searching for a specific bit pattern or PRN sequence in a very long data
sequence, a series of XOR gates can be used to compare a string of bits from the data sequence against the target sequence in
parallel. The number of 0 outputs can then be counted to determine how well the data sequence matches the target sequence.

Correlators are used in many communications devices such as CDMA receivers and decoders for error correction and channel codes.
In a CDMA receiver, correlators are used to extract the polarity of a specific PRN sequence out of a combined collection of PRN
sequences.
A correlator looking for 11010 in the data sequence 1110100101 would compare the incoming data bits against the target sequence at
every possible offset while counting the number of matches (zeros):
1110100101 (data)
11010
(target)
00111
(XOR) 2 zero bits
1110100101
11010
00000
5 zero bits
1110100101
11010
01110
2 zero bits
1110100101
11010
10011
2 zero bits
1110100101
11010
01000 4 zero bits
1110100101
11010
11111 0 zero bits
Matches by offset:
.
:
:
: : : : :
----------0 1 2 3 4 5
In this example, the best match occurs when the target sequence is offset by 1 bit and all five bits match. When offset by 5 bits, the
sequence exactly matches its inverse. By looking at the difference between the number of ones and zeros that come out of the bank of
XOR gates, it is easy to see where the sequence occurs and whether or not it is inverted. Longer sequences are easier to detect than
short sequences.
Transistortransistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT) and resistors. It is
called transistortransistor logic because both the logic gating function (e.g., AND) and the amplifying function are performed by
transistors (contrast with RTL and DTL).
TTL is notable for being a widespread integrated circuit (IC) family used in many applications such as computers, industrial controls,
test equipment and instrumentation, consumer electronics, synthesizers, etc. The designation TTL is sometimes used to mean TTLcompatible logic levels, even when not associated directly with TTL integrated circuits, for example as a label on the inputs and outputs
[1]
of electronic instruments.
After their introduction in integrated circuit form in 1963 by Sylvania, TTL integrated circuits were manufactured by several
semiconductor companies, with the 7400 series by Texas Instruments becoming particularly popular. TTL manufacturers offered a wide
range of logic gate, flip-flops, counters, and other circuits. Several variations from the original bipolar TTL concept were developed,
giving circuits with higher speed or lower power dissipation to allow optimization of a design. TTL circuits simplified design of systems
compared to earlier logic families, offering superior speed to resistortransistor logic(RTL) and easier design layout than emittercoupled logic (ECL). The design of the input and outputs of TTL gates allowed many elements to be interconnected.
TTL became the foundation of computers and other digital electronics. Even after much larger scale integrated circuits made multiplecircuit-board processors obsolete, TTL devices still found extensive use as the "glue" logic interfacing more densely integrated
components. TTL devices were originally made in ceramic and plastic dual-in-line (DIP) packages, and flat-pack form. TTL chips are
now also made in surface-mount packages. Successors to the original bipolar TTL logic often are interchangeable in function with the
original circuits, but with improved speed or lower power dissipation.
History[edit]

A real-time clock built of TTL chips around 1979.

TTL was invented in 1961 by James L. Buie of TRW, "particularly suited to the newly developing integrated circuit design technology",
[2]
and it was originally named transistor-coupled transistor logic (TCTL). The first commercial integrated-circuit TTL devices were
[3]
manufactured by Sylvania in 1963, called the Sylvania Universal High-Level Logic family (SUHL). The Sylvania parts were used in the
[3]
controls of the Phoenix missile. TTL became popular with electronic systems designers after Texas Instruments introduced the 5400
series of ICs, with military temperature range, in 1964 and the later 7400 series, specified over a narrower range, and with inexpensive
[4]
plastic packages in 1966.
The Texas Instruments 7400 family became an industry standard. Compatible parts were made
[5][6]
by Motorola, AMD, Fairchild,Intel, Intersil, Signetics, Mullard, Siemens, SGS-Thomson and National Semiconductor,
and many other
[citation needed]
companies, even in the Eastern Bloc (Soviet Union, GDR, Poland, Bulgaria).
Not only did others make compatible TTL parts,
but compatible parts were made using many other circuit technologies as well. At least one manufacturer, IBM, produced non[7]
compatible TTL circuits for its own use; IBM used the technology in the IBM System/38, IBM 4300, and IBM 3081.
The term "TTL" is applied to many successive generations of bipolar logic, with gradual improvements in speed and power consumption
[citation needed]
[8]
over about two decades. The most recently introduced family
, 74AS/ALS Advanced Schottky, was introduced in 1985. As
of 2008, Texas Instruments continues to supply the more general-purpose chips in numerous obsolete technology families, albeit at
increased prices. Typically, TTL chips integrate no more than a few hundred transistors each. Functions within a single package
generally range from a few logic gates to a microprocessor bit-slice. TTL also became important because its low cost made digital
[9]
techniques economically practical for tasks previously done by analog methods.
The Kenbak-1, ancestor to the first personal computers, used TTL for its CPU instead of a microprocessor chip, which was not
[10]
available in 1971. The 1973 Xerox Alto and 1981 Star workstations, which introduced the graphical user interface, used TTL circuits
integrated at the level of ALUs and bitslices, respectively. Most computers used TTL-compatible "glue logic" between larger chips well
into the 1990s. Until the advent of programmable logic, discrete bipolar logic was used to prototype
and emulate microarchitectures under development.
Implementation[edit]
Fundamental TTL gate[edit]

Two-input TTL NAND gate with a simple output stage (simplified).

TTL inputs are the emitters of a multiple-emitter transistor. This IC structure is functionally equivalent to multiple transistors where the
[11]
bases and collectors are tied together. The output is buffered by a common emitter amplifier.
Inputs both logical ones. When all the inputs are held at high voltage, the baseemitter junctions of the multiple-emitter transistor are
reverse-biased. Unlike DTL, a small collector current (approximately 10A) is drawn by each of the inputs. This is because the
transistor is in reverse-active mode. An approximately constant current flows from the positive rail, through the resistor and into the
[12]
base of the multiple emitter transistor. This current passes through the base-emitter junction of the output transistor, allowing it to
conduct and pulling the output voltage low (logical zero).
An input logical zero. Note that the base-collector junction of the multiple-emitter transistor and the base-emitter junction of the output
transistor are in series between the bottom of the resistor and ground. If one input voltage becomes zero, the corresponding baseemitter junction of the multiple-emitter transistor is in parallel with these two junctions. A phenomenon called current steering means
that when two voltage-stable elements with different threshold voltages are connected in parallel, the current flows through the path
with the smaller threshold voltage. As a result, no current flows through the base of the output transistor, causing it to stop conducting
and the output voltage becomes high (logical one). During the transition the input transistor is briefly in its active region; so it draws a
large current away from the base of the output transistor and thus quickly discharges its base. This is a critical advantage of TTL over
[13]
DTL that speeds up the transition over a diode input structure.
The main disadvantage of TTL with a simple output stage is the relatively high output resistance at output logical "1" that is completely
determined by the output collector resistor. It limits the number of inputs that can be connected (the fanout). Some advantage of the
simple output stage is the high voltage level (up to VCC) of the output logical "1" when the output is not loaded.
A common variation omits the collector resistor of the output transistor, making an open collector output. This allows the designer to
fabricate logic by connecting the open collector outputs of several logic gates together and providing a single external pull-up resistor. If
any of the logic gates becomes logic low (transistor conducting), the combined output will be low. Examples of this type of gate are the
[14]
7401 and 7403 series.
TTL with a "totem-pole" output stage[edit]

Standard TTL NAND with a "totem-pole" output stage, one of four in 7400
To solve the problem with the high output resistance of the simple output stage the second schematic adds to this a "totem-pole"
("pushpull") output. It consists of the two n-p-n transistors V3 and V4, the "lifting" diode V5 and the current-limiting resistor R3 (see the
figure on the right). It is driven by applying the same current steering idea as above.
When V2 is "off", V4 is "off" as well and V3 operates in active region as a voltage follower producing high output voltage (logical "1").
When V2 is "on", it activates V4, driving low voltage (logical "0") to the output. V2 and V4 collectoremitter junctions connect V4 base
emitter junction in parallel to the series-connected V3 baseemitter and V5 anodecathode junctions. V3 base current is deprived; the
transistor turns "off" and it does not impact on the output. In the middle of the transition, the resistor R 3 limits the current flowing directly
through the series connected transistor V3, diode V5 and transistor V4 that are all conducting. It also limits the output current in the case
of output logical "1" and short connection to the ground. The strength of the gate may be increased without proportionally affecting the
[15][16]
power consumption by removing the pull-up and pull-down resistors from the output stage.
The main advantage of TTL with a "totem-pole" output stage is the low output resistance at output logical "1". It is determined by the
upper output transistor V3 operating in active region as a voltage follower. The resistor R 3 does not increase the output resistance since
it is connected in the V3 collector and its influence is compensated by the negative feedback. A disadvantage of the "totem-pole" output
stage is the decreased voltage level (no more than 3.5 V) of the output logical "1" (even, if the output is unloaded). The reason of this
reduction are the voltage drops across the V3 baseemitter and V5 anodecathode junctions.
Interfacing considerations[edit]
Like DTL, TTL is a current-sinking logic since a current must be drawn from inputs to bring them to a logic 0 level. At low input voltage,
the TTL input sources current which must be absorbed by the previous stage. The maximum value of this current is about 1.6 mA for a
[17]
standard TTL gate. The input source has to be low-resistive enough (<500 ) so that the flowing current creates only a negligible
voltage drop (<0.8 V) across it, for the input to be considered as a logical "0". TTL inputs are sometimes simply left floating to provide a
logical "1", though this usage is not recommended.
Standard TTL circuits operate with a 5-volt power supply. A TTL input signal is defined as "low" when between 0 V and 0.8 V with
[18]
respect to the ground terminal, and "high" when between 2.2 V and VCC (5 V) and if a voltage signal ranges between 0.8 V and 2.0 V
were to be sent into the input of a TTL gate, there would be no certain response from the gate and therefore it is considered "uncertain"
(precise logic levels vary slightly between sub-types and by temperature). TTL outputs are typically restricted to narrower limits of
between 0.0 V and 0.4 V for a "low" and between 2.6 V and VCC for a "high", providing at least 0.4 V of noise immunity. Standardization

of the TTL levels was so ubiquitous that complex circuit boards often contained TTL chips made by many different manufacturers
selected for availability and cost, compatibility being assured; two circuit board units off the same assembly line on different successive
days or weeks might have a different mix of brands of chips in the same positions on the board; repair was possible with chips
manufactured years (sometimes over a decade) later than original components. Within usefully broad limits, logic gates could be
treated as ideal Boolean devices without concern for electrical limitations.
In some cases (e.g., when the output of a TTL logic gate needs to be used for driving the input of a CMOS gate), the voltage level of
the "totem-pole" output stage at output logical "1" can be increased up to V CC by connecting an external resistor between the
[19]
V3 collector and the positive rail. It pulls up the V5 cathode and cuts-off the diode. However, this technique actually converts the
sophisticated "totem-pole" output into a simple output stage having significant output resistance when driving a high level (determined
by the external resistor).
Packaging[edit]
Like most integrated circuits of the period 19651990, TTL devices are usually packaged in through-hole, dual in-line packages with
between 14 and 24 lead wires, usually made of epoxy plastic (PDIP) or sometimes of ceramic (CDIP). Beam-lead chip dies without
packages were made for assembly into larger arrays as hybrid integrated circuits. Parts for military and aerospace applications were
packaged in flat packs, a form of surface-mount package, with leads suitable for welding or soldering to printed circuit boards. Today,
many TTL-compatible devices are available in surface-mount packages, which are available in a wider array of types than through-hole
packages.
TTL is particularly well suited to bipolar integrated circuits because additional inputs to a gate merely required additional emitters on a
shared base region of the input transistor. If individually packaged transistors were used, the cost of all the transistors would discourage
one from using such an input structure. But in an integrated circuit, the additional emitters for extra gate inputs add only a small area.
Comparison with other logic families[edit]
Main article: Logic family
TTL devices consume substantially more power than equivalent CMOS devices at rest, but power consumption does not increase with
[20]
clock speed as rapidly as for CMOS devices. Compared to contemporary ECL circuits, TTL uses less power and has easier design
rules but is substantially slower. Designers can combine ECL and TTL devices in the same system to achieve best overall performance
and economy, but level-shifting devices are required between the two logic families. TTL is less sensitive to damage fromelectrostatic
discharge than early CMOS devices.
Due to the output structure of TTL devices, the output impedance is asymmetrical between the high and low state, making them
unsuitable for driving transmission lines. This drawback is usually overcome by buffering the outputs with special line-driver devices
where signals need to be sent through cables. ECL, by virtue of its symmetric low-impedance output structure, does not have this
drawback.
The TTL "totem-pole" output structure often has a momentary overlap when both the upper and lower transistors are conducting,
resulting in a substantial pulse of current drawn from the power supply. These pulses can couple in unexpected ways between multiple
integrated circuit packages, resulting in reduced noise margin and lower performance. TTL systems usually have a decoupling
capacitor for every one or two IC packages, so that a current pulse from one TTL chip does not momentarily reduce the supply voltage
to another.
Several manufacturers now supply CMOS logic equivalents with TTL-compatible input and output levels, usually bearing part numbers
similar to the equivalent TTL component and with the same pinouts. For example, the 74HCT00 series provides many drop-in
replacements for bipolar 7400 series parts, but uses CMOS technology.
Sub-types[edit]
Successive generations of technology produced compatible parts with improved power consumption or switching speed, or both.
Although vendors uniformly marketed these various product lines as TTL with Schottky diodes, some of the underlying circuits, such as
[21]
used in the LS family, could rather be considered DTL.
Variations of and successors to the basic TTL family, which has a typical gate propagation delay of 10ns and a power dissipation of
10 mW per gate, for a powerdelay product(PDP) or switching energy of about 100 pJ, include:
Low-power TTL (L), which traded switching speed (33ns) for a reduction in power consumption (1 mW) (now essentially replaced
by CMOS logic)
High-speed TTL (H), with faster switching than standard TTL (6ns) but significantly higher power dissipation (22 mW)
Schottky TTL (S), introduced in 1969, which used Schottky diode clamps at gate inputs to prevent charge storage and improve
switching time. These gates operated more quickly (3ns) but had higher power dissipation (19 mW)
Low-power Schottky TTL (LS) used the higher resistance values of low-power TTL and the Schottky diodes to provide a good
combination of speed (9.5ns) and reduced power consumption (2 mW), and PDP of about 20 pJ. Probably the most common type of
TTL, these were used as glue logic in microcomputers, essentially replacing the former H, L, and S sub-families.
Fast (F) and Advanced-Schottky (AS) variants of LS from Fairchild and TI, respectively, circa 1985, with "Miller-killer" circuits to speed
up the low-to-high transition. These families achieved PDPs of 10 pJ and 4 pJ, respectively, the lowest of all the TTL families.
Low-voltage TTL (LVTTL) for 3.3-volt power supplies and memory interfacing.
Most manufacturers offer commercial and extended temperature ranges: for example Texas Instruments 7400 series parts are rated
from 0 to 70 C, and 5400 series devices over the military-specification temperature range of 55 to +125 C.
Special quality levels and high-reliability parts are available for military and aerospace applications.
Radiation-hardened devices are offered for space applications.
Applications[edit]
Before the advent of VLSI devices, TTL integrated circuits were a standard method of construction for the processors of mini-computer
and mainframe processors; such as theDEC VAX and Data General Eclipse, and for equipment such as machine tool numerical
controls, printers and video display terminals. As microprocessors became more functional, TTL devices became important for "glue
logic" applications, such as fast bus drivers on a motherboard, which tie together the function blocks realized in VLSI elements.
Analog applications[edit]
While originally designed to handle logic-level digital signals, a TTL inverter can be biased as an analog amplifier. Connecting a resistor
between the output and the input biases the TTL element as a negative feedback amplifier. Such amplifiers may be useful to convert

[22]

analog signals to the digital domain but would not ordinarily be used where analog amplification is the primary purpose. TTL inverters
can also be used in crystal oscillators where their analog amplification ability is significant.
A parity bit, or check bit is a bit added to the end of a string of binary code that indicates whether the number of bits in the string with
the value one is even or odd. Parity bits are used as the simplest form of error detecting code.
There are two variants of parity bits: even parity bit and odd parity bit.
In the case of even parity, the number of bits whose value is 1 in a given set are counted. If that total is odd, the parity bit value is set to
1, making the total count of 1's in the set an even number. If the count of ones in a given set of bits is already even, the parity bit's value
remains 0.
In the case of odd parity, the situation is reversed. Instead, if the sum of bits with a value of 1 is odd, the parity bit's value is set to zero.
And if the sum of bits with a value of 1 is even, the parity bit value is set to 1, making the total count of 1's in the set an odd number.
Even parity is a special case of a cyclic redundancy check (CRC), where the 1-bit CRC is generated by the polynomial x+1.
If the parity bit is present but not used, it may be referred to as mark parity (when the parity bit is always 1) or space parity (the bit is
always 0).
Parity[edit]
In mathematics, parity refers to the evenness or oddness of an integer, which for a binary number is determined only by the least
significant bit. In telecommunications and computing, parity refers to the evenness or oddness of the number of bits with value one
within a given set of bits, and is thus determined by the value of all the bits. It can be calculated via an XOR sum of the bits, yielding 0
for even parity and 1 for odd parity. This property of being dependent upon all the bits and changing value if any one bit changes allows
for its use in error detection schemes.
Error detection[edit]
If an odd number of bits (including the parity bit) are transmitted incorrectly, the parity bit will be incorrect, thus indicating that a parity
error occurred in the transmission. The parity bit is only suitable for detecting errors; it cannot correct any errors, as there is no way to
determine which particular bit is corrupted. The data must be discarded entirely, and re-transmitted from scratch. On a noisy
transmission medium, successful transmission can therefore take a long time, or even never occur. However, parity has the advantage
that it uses only a single bit and requires only a number of XOR gates to generate. See Hamming code for an example of an errorcorrecting code.
Parity bit checking is used occasionally for transmitting ASCII characters, which have 7 bits, leaving the 8th bit as a parity bit.
For example, the parity bit can be computed as follows, assuming we are sending simple 4-bit values 1001.
Type of bit parity Successful transmission scenario

Even parity

A wants to transmit: 1001

A computes parity bit value: 1+0+0+1 (mod 2) = 0
A adds parity bit and sends: 10010
B receives: 10010
B computes parity: 1+0+0+1+0 (mod 2) = 0
B reports correct transmission after observing expected even result.

Odd parity

A wants to transmit: 1001

A computes parity bit value: 1+0+0+1 + 1 (mod 2) = 1
A adds parity bit and sends: 10011
B receives: 10011
B computes overall parity: 1+0+0+1+1 (mod 2) = 1
B reports correct transmission after observing expected result.

This mechanism enables the detection of single bit errors, because if one bit gets flipped due to line noise, there will be an incorrect
number of ones in the received data. In the two examples above, B's calculated parity value matches the parity bit in its received value,
indicating there are no single bit errors. Consider the following example with a transmission error in the second bit using XOR:
Type of bit parity error Failed transmission scenario

Even parity
Error in the second bit

A wants to transmit: 1001

A computes parity bit value: 1^0^0^1 = 0
A adds parity bit and sends: 10010
...TRANSMISSION ERROR...
B receives: 11010
B computes overall parity: 1^1^0^1^0 = 1
B reports incorrect transmission after observing unexpected odd result.

Even parity
Error in the parity bit

A wants to transmit: 1001

A computes even parity value: 1^0^0^1 = 0
A sends: 10010
...TRANSMISSION ERROR...
B receives: 10011
B computes overall parity: 1^0^0^1^1 = 1
B reports incorrect transmission after observing unexpected odd result.

There is a limitation to parity schemes. A parity bit is only guaranteed to detect an odd number of bit errors. If an even number of bits
have errors, the parity bit records the correct number of ones, even though the data is corrupt. (See also error detection and correction.)
Consider the same example as before with an even number of corrupted bits:
Type of bit parity error Failed transmission scenario

A wants to transmit: 1001

A computes even parity value: 1^0^0^1 = 0
A sends: 10010
Even parity
...TRANSMISSION ERROR...
Two corrupted bits
B receives: 11011
B computes overall parity: 1^1^0^1^1 = 0
B reports correct transmission though actually incorrect.
B observes even parity, as expected, thereby failing to catch the two bit errors.
Usage[edit]
Because of its simplicity, parity is used in many hardware applications where an operation can be repeated in case of difficulty, or
where simply detecting the error is helpful. For example, the SCSI and PCI buses use parity to detect transmission errors, and
many microprocessor instruction caches include parity protection. Because the I-cache data is just a copy of main memory, it can be
disregarded and re-fetched if it is found to be corrupted.
In serial data transmission, a common format is 7 data bit, an even parity bit, and one or two stop bits. This format neatly
accommodates all the 7-bit ASCII characters in a convenient 8-bit byte. Other formats are possible; 8 bits of data plus a parity bit can
convey all 8-bit byte values.
In serial communication contexts, parity is usually generated and checked by interface hardware (e.g., a UART) and, on reception, the
result made available to the CPU (and so to, for instance, the operating system) via a status bit in a hardware register in the interface
hardware. Recovery from the error is usually done by retransmitting the data, the details of which are usually handled by software (e.g.,
the operating system I/O routines).
RAID[edit]
Parity data is used by some RAID levels to achieve redundancy. If a drive in the array fails, remaining data on the other drives can be
combined with the parity data (using the Boolean XOR function) to reconstruct the missing data.
For example, suppose two drives in a three-drive RAID 5 array contained the following data:
Drive 1: 01101101
Drive 2: 11010100
To calculate parity data for the two drives, an XOR is performed on their data:
01101101
XOR 11010100
_____________
10111001
The resulting parity data, 10111001, is then stored on Drive 3.
Should any of the three drives fail, the contents of the failed drive can be reconstructed on a replacement drive by subjecting the data
from the remaining drives to the same XOR operation. If Drive 2 were to fail, its data could be rebuilt using the XOR results of the
contents of the two remaining drives, Drive 1 and Drive 3:
Drive 1: 01101101
Drive 3: 10111001
as follows:
10111001
XOR 01101101
_____________
11010100
The result of that XOR calculation yields Drive 2's contents. 11010100 is then stored on Drive 2, fully repairing the array. This same
XOR concept applies similarly to larger arrays, using any number of disks. In the case of a RAID 3 array of 12 drives, 11 drives
participate in the XOR calculation shown above and yield a value that is then stored on the dedicated parity drive.
History[edit]
A "parity track" was present on the first magnetic tape data storage in 1951. Parity in this form, applied across multiple parallel signals,
is known as a transverse redundancy check. This can be combined with parity computed over multiple bits sent on a single signal,
a longitudinal redundancy check. In a parallel bus, there is one longitudinal redundancy check bit per parallel signal.
Parity was also used on at least some paper-tape (punched tape) data entry systems (which preceded magnetic tape systems). On the
systems sold by British company ICL (formerly ICT) the 1-inch-wide (25 mm) paper tape had 8 hole positions running across it, with the
8th being for parity. 7 positions were used for the data, e.g., 7-bit ASCII. The 8th position had a hole punched in it depending on the
number of data holes punched.
For a contrary view, Seymour Cray, premier designer of supercomputers, held parity designs in contempt. He felt it showed poor
designif you designed your transmission paths to be reliable, you would not have to waste resources on parity. His famous quote on
this (circa 1963) was "Parity is for farmers" (after the use of the term "parity" in the New Deal). After he later included parity bits on the
[1]
CDC 7600, Cray reputedly said that "I learned that a lot of farmers buy computers."

7 bits of data (count of 1 bits)

8 bits including parity

even

odd

0000000

00000000 00000001

1010001

10100011 10100010

1101001

11010010 11010011

1111111

11111111 11111110

A totem pole is a certain type of driver, used to amplify square waves (and sine waves, with additional components to prevent
distortion!) into a stronger square wave for driving other types of semiconductors faster.
A totem pole consists of a PNP and NPN transistor arranged emitter to emitter, with their bases coupled together. The output signal is
taken from where the emitter of the NPN transistor and the collector of the PNP transistor meet. The plus of this is the ease of use, but
the downside is that transistors do make heat, and this may (depends on your application) create enough heat to warrant a heat sink.
A totem pole driver can be used to more effectively drive MOSFETS, (which will be explained in the next step, actually), and IGBT's.
The increase in current allows the semiconductors to turn on and off faster, reducing heating.
You can use just about any NPN and PNP transistor combination, as long as they can handle the amount of current you need to drive
the mosfet or IGBT with.
AND-OR-Invert (AOI) logic and AOI gates are two-level compound (or complex) logic functions constructed from the combination of
one or more AND gates followed by a NOR gate. Construction of AOI cells is particularly efficient using CMOS technology where the
total number of transistor gates can be compared to the same construction using NAND logic or NOR logic. The complement of AOI
Logic is OR-AND-Invert (OAI) logic where the OR gates precede an AND gate.
Logic operations[edit]
AOI gates perform one or more AND operations followed by an OR operation and then an inversion. For example, a 2-2 AOI gate can
be represented by the boolean equation and truth table:

2-2 AOI
INPUT
OUTPUT
A B C D F
0 X X 0 1
X 0 X 0 1
0 X 0 X 1
X 0 0 X 1
1 1 X X 0
X X 1 1 0
A 2-1 AOI gate can be represented by following the boolean equation and truth table:
2-1 AOI
INPUT OUTPUT
A B C F
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
Larger AOI gates, such as 4-3 AOI or 3-3-3 AOI can also be used.
Electronic implementation[edit]

CMOS implementation of a 2-1 AOI gate

AOI and OAI gates can be readily implemented in CMOS circuitry. AOI gates are particularly advantaged in that the total number of
transistors (or gates) is less than if the AND, NOT, and OR functions were implemented separately. This results in increased speed,
reduced power, smaller area, and potentially lower fabrication cost. For example, a 2-1 AOI gate can be constructed with 6 transistors
in CMOS compared to 10 transistors using a 2-input NAND gate (4 transistors), an inverter (2 transistors), and a 2-input NOR gate (4
transistors).
In NMOS logic, only the lower half of the CMOS circuit is used, in combination with a load device, or pull-up transistor (typically
a depletion load or adynamic load).
AOI gates are similarly efficient in transistortransistor logic (TTL). The TTL 7400 line included a number of AOI gate parts, such as the
7451 dual 2-wide 2-input AND-OR-invert gate and the 7464 4-2-3-2-input AND-OR-invert gate.