Mathematical Analysis

A thorough understanding of the MODFET terminal characteristics is essential for the

reader who intends to design MOS circuits.
There are three distinct regions of operation: the cutoff region, the triode region, and
the saturation region. The suturation region is used if the FET is to operate as an
amplifier. For operation as a switch, the cutoff and triode regions are utilized. The
deveice is cutoff when vGS < Vt. To operate the MOSFET in the triode region we must
first induce a channel,
vGS >= Vt (Induced Channel) ------------ (1)
And then keep vDS small enough so that the channel remains contiuous. This is
achieved by ensuring that the gate-to-drain voltage is
vGD > Vt (Continuous Channel) --------- (2)
This condition can be stated explicitly in terms of vDS by
writing vGD = vGS + vSD = vGS - vDS; thus
vGS -vDS > Vt ---------- (3)
which can be rearranged to yield
vDS < vGS -Vt (Continuous channel) ------------ (4)
Eq. (2) or (4) can be used to ascertain triode-region operation. In words, the n-channel
enhancement-type MOSFET operates in the triode region when vGS is greater then
Vt and drain voltage is lower than the gate by at least Vt volts.
In the triode region, the iD-vDS characteristics can be described by teh relationship of
iD = kn'W/L[(vGS - Vt)vDS - 1/2*vDS2] ------------ (5)
where kn' = nCox is the process transconductance parameter; its value is determined
by the fabrication technology. If vDS is sufficiently small so that we can neglect the
vDS2 term if the Eq. (5), we obtain for the iD-vDScharacterristics near the origin the
relationship
iD ~= kn'W/L(vGS - Vt)vDS ----------- (6)

This linear relationship represents the operation of the MOS transistor as a linear
resistance rDS,
rDS = vDS/iD = [kn'W/L(vGS - Vt)]-1 ---------- (7)
whose value is controlled by vGS.
To operate the MOSFET in the saturation region, a channel must be induced,
vGS >= Vt (Induced channel) ---------- (8)
and pinch off at the drain end by raising vDS to a value that results in the gate-to-drain
volatage falling below Vt,
vGD <= Vt (Pinched-off channel) --------- (9)
This condition can be expressed explicitly in terms of vDS as
vDS >= vGS - Vt (Pinched-off channel) ---------- (10)
In words, the n-channel enhancement-type MOSFET operates in the saturation region
when vGS is greater than Vt and the drain voltage does not fall below the gate voltage
by more than Vt volts.
The boundary between the trode region and the saturation region is characterized by
vDS = vGS - Vt (Boundary) ----------- (11)
Substituting this value of vDS into Eq.(5) gives the saturation value of the current iD as
iD = 1/2 kn'W/L(vGS - Vt)2 ---------- (12)
Thus in saturation the MOSFET provides a drain current whose value is independent
of the drain voltage vDS and is determined by teh gate voltage vGS according to the
squre-law relationship in (12). Thus the saturated MOSFET behaves as an ideal
current source whose value is controlled by vGS according to the nonlinear relationship
in Eq.(12).
The boundary between the triode and saturation regions is characterized by vDS = vGS Vt, its sequation can be found by substituting for vGS -Vt by vDS in either the triode
region equation (5) or the saturation region equation (12). The result is
iD = 1/2 kn'W/LvDS2

Mathematical Analysis
Note: In this applet, all the circuits have the Source Resistor RS. So the calculation of
DC and AC analysis should be more complex. But in the teaching mode, you can also
do the calculation with RS = 0. This will be familiar with you.
Common Source
1)NMOS
When the NMOS device in the Saturation mode, VDS >= VGS - Vtn
for VGS = Vin - ID * RS (if RS = 0, then VGS = Vin),
ID = 1 / 2 * un * Cox * W / L * (Vin - ID * RS - Vtn)^2
If the MOSFET device is in the Triode mode, VDS < VGS - Vtn
ID = 1 / 2 * un * Cox * W / L * (2 * ( Vin - ID * RS - Vthn) * Vout - Vout *
Vout)
other important values:
kn = un * Cox
gm = 2 * kn * (Vin - ID * RS - Vthn)
Rout =RD || ( ( RS || ro || (1/gm) ) / RS / ro)
Av = -gm * RD * ro /(RD + ro)
2)PMOS
When the PMOS device in the Saturation mode, so VSD >= VSG - Vtp

For VSG = VDD - ID * RS - Vin( if RS = 0, then VSG = VDD - Vin)

ID = 1 / 2 * un * Cox * W / L * ( VDD - ID * RS - Vin - Vtp)^2
or in Triode mode, VDS < VGS - Vtp
ID = 1 / 2 * un * Cox * W / L * (2 * ( VDD - ID * RS - Vin - Vtp) * Vout - Vout
* Vout)
other important values:
gm = un * Cox * W / L * (VDD - Vin - Vthp)
Rout =RD || ((RS || ro || (1/gm)) / RS / ro)
Av = -gm / ( gm * RS / RD + RS / RD /ro + 1 / ro + 1 / RD)
Common Gate
1)NMOS
When the NMOS device in the Saturation mode, so VDS >= VGS - Vtn
For VDS = Vbias - Vin - ID * RS (if RS = 0, then VGS = Vbias - Vin)
ID = 1 / 2 * un * Cox * W / L * (Vbias - Vin - ID * RS - Vthn)^2
or in Triode mode, VDS < VGS - Vtn
ID = 1 / 2 * un * Cox * W / L * (2 * ( Vbias - Vin - ID * RS - Vthn) * Vout Vout * Vout)
other important values:
gm = 2 * kn * (Vbias - Vin - ID * RS - Vtn)
Rout =RD || ((RS || ro || (1/gm)) / RS / ro)
Av = gm * RD
2)PMOS
When the PMOS device in the Saturation mode, so VSD >= VSG - Vthp

For VSG = VDD + Vbias - ID * RS - Vin (when RS = 0, VSG = VDD + Vbias Vin)
ID = 1 / 2 * un * Cox * W / L * (VDD + Vbias - ID * RS - Vin - Vthp)^2
or in Triode mode, VDS < VGS - Vthp
ID = 1 / 2 * un * Cox * W / L * (2 * ( Vin - ID * RS - Vthp) * Vout - Vout *
Vout)
other important values:
gm = un * Cox * W / L * (Vin - Vin - Vthp)
Rout =RD || ((RS || ro || 1/gm) / RS / ro)
Av = -gm / ( gm * RS / RD + RS / RD /ro + 1 / ro + 1 / RD)
Common Drain ( Source Follower )
1)NMOS
When the NMOS device in the Saturation mode, so VDS >= VGS - Vtn
For VGS = Vin - ID * RS, ( if RS = 0, then VGS = Vin);
ID = 1 / 2 * un * Cox * W / L * (Vin - ID * RS - Vtn)^2
==> You may solve for ID. Then get VGS from it.
==> Or, you may solve for VGS instead like this link. Note that the applet's DC
analysis is INCORRECT (applet has error in the formula -- it errorneously used VS
= 0 for the ID calculation!).
or in Triode mode, VDS < VGS - Vthn
ID = 1 / 2 * un * Cox * W / L * (2 * ( Vin - ID * RS - Vthn) * Vout - Vout *
Vout)
other important values:
gm = 2 * kn * (Vin - ID * RS - Vtn)
Rout = RS || (1 / RD * (((1 / gm) || ro) / ( RD || ro )))

Av = -gm * RS / (1 + gm * RS)
2)PMOS
When the PMOS device in the Saturation mode, so VSD >= VSG - Vtp
For VSG = Vout - Vin = VDD - ID * RS - Vin ( if RS = 0, then VSG = VDD - Vin)
ID = 1 / 2 * un * Cox * W / L * ( VDD - ID * RS - Vin - Vtp)^2
or in Triode mode, VDS < VGS - Vtp
ID = 1 / 2 * un * Cox * W / L * (2 * ( VDD - ID * RS - Vin - Vtp) * Vout - Vout
* Vout)
other important values:
gm = un * Cox * W / L * (VDD - ID * RS - Vin - Vtp)
Rout = RS || (1 / RD * (((1 / gm) || ro) / ( RD || ro )))
Av = gm / ( 1 / ro + RD / RS /ro + gm + 1 / RS)

Mathematical Analysis
The static operation of the CMOS inverter is as the followings:
When the input voltage vin = 0, vo = VOH = VDD, and the output node is connected to
VDD through the resistance rDSP of the pull up transistor Qp. Similarly, with vin =
VDD, vo = VOL = 0, and the output node is connected to ground through the
resistoance rDSN of the pull-down transistor QN. Thus, in steady state, no direct-current
path exists between VDD and ground, and the static current and the static power
dissipation are both zero (leakage effects are usually negligibly small).
The CMOS inverter can be made to switch at the midpoint of the logic swing, 0 to
VDD, that is at VDD/2, by appropriately sizing the transistors. Specifically, it can be
shown that the swithcing threshold is given by
Vth = [VDD - |Vtp| + (kn/kp)1/2Vtn]/[1+(kn/kp)1/2]
where kn = kn'(W/L)n and kp = kp'(W/L)p, from which we see that for the typical case
where Vtn = |Vtp|, Vth = VDD/2 for kn = kp, that is

kn'(W/L)n = kp'(W/L)p
Thus a symmetrical transfer characteristic is obtained when the devices are designed
to have equal transconductance parameters, a condition we refer to as matching.
Since n is two to three times larger than p, matching is achived by making
(W/L)p two to three times (i.e., times)(W/L)n,
(W/L)p = (np)(W/L)n
Normally, the two devices have the same channel length, L, which is set at the
minimum alowable for the given process technology. The minimum width of the
NMOS transistor is usually one and a half to two times L, and the width of the PMOS
transistor two to three times that. If the inverter is required to drive a relatively large
capacitive load, the transistors are made wider. However, to conserve chip area, most
inverters would have the "minimum size".
Placing the gate threshold at the center of the logic swing, match the transconductance
parameters of QN and QP provides the inverter with equal current driving capacity in
both directions (pull-up and pull-down). Futhermore, and obviously related, it
makes rDSN = rDSP. Thus an inverter with matched transistors will ahve equal
propagation delays, tPLH and tPHL.
When the inverter threshold is at VDD/2, the noise margins NMH and NML are
equalized and their values are maximized, such that:
NMH = NML = 3/8*(VDD + 2/3*Vt)
Since typically Vt = 0.1 to 0.2 VDD, the noise margins are approximately 0.4VDD. This
value, being close to half the power supply voltage, makes the CMOS inverter nearly
ideal from a noise-immunity standpoint. Futher, since inverter dc input current is
practically zero, the noise margins are not dependent on the gate fan-out.
As a final comment on the inverter VTC, we note that the slope in the transition
region, though large, is finite and is given by -(gmN + gmP)(roN||roP).