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Spare Cells
Posted on November 23, 2012 by Sini Mukundan in Physical Design // 5
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I have been writing an article on ECO flows.Of course I cannot talk about
freeze_silicon ECOs without talking about spare cells.When I was a wee intern
sitting through PnR training, spare cells confused me. I thought I had to insert
the spares and use them in the same session! So heres a small note about spare
cells.
Spare cells are just that.They are extra cells placed in your layout in
anticipation of a future ECO.When I say future, I mean after you taped out and
got your silicon back.After silicon tests complete, it might become necessary to
have some changes to the design.There might be a bug, or a very easy feature
that will make the chip more valuable.This is where you try to use the existing
spare cells in your design to incorporate the design change.For example, if
you need a logic change that requires addition of an AND cell, you can use an
existing spare AND to make this change. This way, you are ensuring that the
base layer masks need no regeneration. The metal connections have changed,
and hence only metal masks are regenerated for the next fabrication.
Inserting Spare Cells

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Spare cells need to added while the initial implementation. There are two ways
to do this.
1. The designer adds separate modules with the required cells. You start your
PnR with spare cells included, and must make sure that the tool hasnt
optimized them away. There can be more than one such spare modules,
and they will be typically named spare* or some such combination. The
inputs are tied to power or ground nets, as floating gates shouldnt be
allowed in the layout. The outputs are left unconnected.
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//Definition
module spare_cells ( );
INVX5 spare_inv1 ( .A(1'b0) );
INVX5 spare_inv2 ( .A(1'b0) );
DFFCPX2 spare_dff2 ( .D(1'b0), .CP(1'b0), .CLR(1'b0), .PREZ(1'b1) );
DFFCPX2 spare_dff2 ( .D(1'b0), .CP(1'b0), .CLR(1'b0), .PREZ(1'b1) );
endmodule
//Instantiation
spare_cells spare_i_1 ( );
spare_cells spare_i_2 ( );

2. Use a command provided by the PnR tool to add the spare cells to the
netlist in placement stage. An example using ICCompiler command is given
below.
1 insert_spare_cells -lib_cell
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} \
4

{INVX5 \
DFFCPX2 \
-cell_name spare -num_instances 4 -tie -skip_legal

Spare Cell Placement

You need to give some thought as to where to place your spare cells in
layout.They are not timing critical, and if you do not give any constraints,
PnR tool will place them all together.However, you do not know which area
of the layout will eventually require a connection to the spares.You can
have two placement approaches.

Sprinkled Spares
Sprinkle the individual spare cells in your layout, so from any point
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you may have a reasonably close library cell.

Group the spare cells in multiple groups and sprinkle/place each
group in the layout.

Grouped Spares
If the spare cells are included in the netlist, you need to set an attribute
spare_cell so that the PnR tool does no optimize these. If you do not set
them as spare_cell or set a dont_touch, you will find that after placement all
spare cells are gone.
Given below is an example of spare cell placement as grouped instances.
Here it is assumed that the spare cells are instantiated in the netlist as
spare_i_1 & spare_i_2.
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set physopt_tie_spare_cells true

set_attribute [get_cells spare_i*/*] is_spare_cell true
spread_spare_cells [get_cells spare_i_1/*] -bbox {{30 30} {80 80}}
spread_spare_cells [get_cells spare_i_2/*] -bbox {{300 100} {350 150}}
place_opt

And heres an example of inserting & placing spare cells using ICC. You
can group the cells by giving cell names, which I havent done below. It is
sprinkled individually instead.
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place_opt
set physopt_tie_spare_cells true
insert_spare_cells -lib_cell
{INVX5 \
DFFCPX2 \
} \
-cell_name spare -num_instances 2 -tie -skip_legal
legalize_placement -incremental
spread_spare_cells [get_cells spare*] -bbox {{30 30} {350 150}}
psynopt

Note that I have used a command set physopt_tie_spare_cells true in the

examples above. This ensures that the inputs are tied to TIE cells in the
subsequent placement stage, instead of connecting directly to the power or
ground lines. If you want to control the number of pins connected to a TIE
cell, use the command set_max_fanout 1 libname/TIE* before running the above
commands.
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http://vlsi.pro/spare-cells/

Latest Posts

Sini Mukundan
Staff Engineer at Texas Instruments

Sini is an expert on physical design flow and related methodologies.

Outside work, she is an avid reader and generally loves being lazy.

eco
pnr

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3 Comments on Spare Cells

1.

raghu // November 2, 2013 at 10:32 am // Reply

could you please tell me the intrnl structure of the spare cell?
Sini // November 6, 2013 at 5:25 pm // Reply
Spare cells are not special cells. The existing cells from the used
standard cell library are included as spare cells. The only difference
is that the input pins are tied to VDD/VSS instead of signals. So the
internal structure is the same as any other NAND/NOR/AND/FF in the
library.

2.

renjith // December 12, 2013 at 12:26 am // Reply

Could you please give a detailed description including pictures on Tie high

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and tie low cell. How it is helpful since we are using it to avoid the direct
connection of gate of unused pins with VDD and GND
2 Trackbacks & Pingbacks
1. ECO | VLSI Pro
2. Physical Design Flow II:Placement | VLSI Pro

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