1412

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 4, APRIL 2013

200 V Superjunction N-Type Lateral Insulated-Gate

Bipolar Transistor With Improved
Latch-Up Characteristics
Elizabeth Kho Ching Tee, Marina Antoniou, Florin Udrea, Member, IEEE, Alexander Hlke,
Steven John Pilkington, Deb Kumar Pal, Ng Liang Yew, and Wan Azlan Bin Wan Zainal Abidin

Abstract This paper evaluates the technique used to improve

the latching characteristics of the 200 V n-type superjunction
(SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial
silicon-on-insulator. SJ IGBT devices are more prone to latchup than standard IGBTs due to the presence of a strong pnp
transistor with the p layer serving as an effective collector of
holes. The initial SJ LIGBT design latches at about 23 V with a
gate voltage of 5 V with a forward voltage drop (VON ) of 2 V at
300 A/cm2 . The latch-up current density is 1100 A/cm2 . The latest
SJ LIGBT design shows an increase in latch-up voltage close to
100 V without a significant penalty in VON . The latest design
shows a latch-up current density of 1195 A/cm2 . The enhanced
robustness against static latch-up leads to a better forward bias
safe operating area.
Index Terms Latch-up, lateral insulated-gate
transistor (LIGBT), partial silicon-on-insulator
superjunction.

bipolar
(SOI),

I. I NTRODUCTION

ATERAL insulated-gate bipolar transistors (LIGBTs)

have long been proposed for use in integrated power
integrated circuits [1], and LIGBTs fabricated on silicon-oninsulator (SOI) substrate are favored over bulk silicon substrate
due to their superior isolation, lower switching losses, and the
possibility of co-integrating fast recovery diodes and control
circuits. However, there are some weaknesses in SOI LIGBT
[2] and the partial SOI (PSOI) concept was subsequently
proposed [3][5] to suppress the crowding of the electrostatic
potential lines in the confined silicon and to reduce self-heating
in SOI technology. For better tradeoff between breakdown
voltage (BV) and specific on resistance (Ron ), most high voltage structures use a form of RESURF [6]. Subsequently, the
superjunction (SJ) [7] concept was introduced and later proven
to be effective in MOSFET and even in breaking the silicon

Manuscript received December 17, 2012; revised February 4, 2013; accepted

February 5, 2013. Date of publication March 7, 2013; date of current version
March 20, 2013. The review of this paper was arranged by Editor G. Dolny.
E. K. C. Tee, A. Hlke, S. J. Pilkington, and D. K. Pal are
with the X-FAB Sarawak Sdn. Bhd, Kuching 93350, Malaysia
(e-mail:
elizabeth.kho@xfab.com;
Alexander.Hoelke@xfab.com;
steven.pilkington@xfab.com; deb.kumar@xfab.com).
M. Antoniou and F. Udrea are with the Engineering Department, University
of Cambridge, Cambridge CB2 1PZ, U.K., (e-mail: ma308@cam.ac.uk;
fu@eng.cam.ac.uk).
N. L. Yew and W. A. B. W. Z. Abidin are with the Department of
Electronics Engineering, University of Sarawak, Kuching 93400, Malaysia
(e-mail: ngliangy@feng.unimas.my; wzaazlan@feng.unimas.my).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2013.2246165

limit in terms of Ron scaling with the BV [8]. The concept is

also applicable to both discrete IGBTs [9][11] and LIGBTs
[12][14], as it helps to increase the BV and switching speed.
A major limitation of the lateral IGBT is the embedded
parasitic thyristor-like four-layer pnpn structure that can be
easily latched into a state whereby the gate control is lost and
the device is destroyed. This effect has a strong impact on the
forward bias safe operating area (FBSOA), and is a weakness
of the IGBTs compared to power MOSFETs. The latch-up is
even more pronounced in a SJ IGBT-type structure, as the
highly doped p layer within the drift region helps to collect
more effectively the holes from the drift region and direct
them to the source short, under the n+ source. As a result,
the hole/electron ratio at the cathode side is increased for a
SJ device compared to an equivalent standard IGBT. While
this is beneficial in terms of collecting holes from the drift
region during turn-off, it can induce a premature latch-up, as
the holes under the n+ source can trigger the parasitic pnpn
thyristor structure. The first silicon result of 200 V SJ n-type
LIGBT latches at 23 V (corresponding to a current density
of 1100 A/cm2 ) with VON of 2 V at 300 A/cm2 . To increase
the FBSOA, an alternate n+/p+ diffusion design at the source
region is being introduced and its impact toward the latch-up
voltage and VON is further investigated.
II. D EVICE S TRUCTURE AND O N -S TATE M ECHANISM
Fig. 1(a) shows a typical SOI LIGBT cell structure with
the equivalent circuit given in Fig. 1(b). The parasitic thyristor
that causes latch-up is comprised of the n+ source/p well/n
layer and n buffer/p+ anode. This thyristor is triggered when
the hole current, which flows through the p well underneath
the n+ source (Rshunt ) is sufficiently large to forward bias the
n+ source/p well junction and thus, the lateral npn bipolar
component is turned on, causing latch-up. The pnp transistor
gain is important as it sets the amount of holes that are
eventually reaching the p well to flow under the n+ source.
Fig. 2(a) shows the initial design of a 200 V n-type SJ
LIGBT on SOI substrate. The designed buried oxide (BOX)
has a thickness of 1 m and the silicon on top has a thickness
of 3.5 m. A buried junction is placed beside the deep trench
isolation (DTI) and partially below the BOX to realize the
PSOI structure for increased BV. The drift region is made up
of two opposite polarity layers, extending from the n buffer
to the source of the LIGBT with concentration in the range

0018-9383/$31.00 2013 IEEE

TEE et al.: 200 V SJ N-TYPE LIGBT WITH IMPROVED LATCH-UP CHARACTERISTICS

Source (cathode)

so u rce /ga te
body

a n od e

p o ly

p+ n+

1413

p+

n d rift

Rshunt

n b uf

p well

npn

buried oxide (BOX)

p - h a nd le w afe r
superjunction
(a)

pnp
Source cathode)

Rshunt

anode

npn

(a)

Source (cathode)
pnp

Rshunt
anode

T1

T3

(b)
Fig. 1.

(a) Cross section and (b) equivalent circuit of typical SOI LIGBT.

T2

T4

n layer

source/ gate
body

p layer

anode nbur

poly
p+n+

p+

n layer
p well

n+

nbuf

p layer

n well

buried oxide (BOX)

deep trench
isolation (DTI)

nbur

anode
(b)
Fig. 3.

(a) Simplified and (b) detailed equivalent circuits of SJ LIGBT.

p- handle wafer

(a)

IA(A)

Initial design
1.6E-02
1.4E-02
1.2E-02
1.0E-02
8.0E-03
6.0E-03
4.0E-03
2.0E-03
0.0E+00

VGS=5V
0

10

15

20

25

VA(V)

(b)
Fig. 2. (a) Cross section and (b) output characteristic at VGS = 5 V of
initial design at T = 300 K.

of 1016 cm3 . The n buffer has about 1 order higher doped

as compared to SJ drift region. This junction has no influence
on the plasma in the n/p layer during on-state operation, but
only provides an extra depletion region during the off-state
(blocking mode) for enhanced breakdown. Fig. 2(b) shows
the measured latch-up characteristics in the on-state for this
initial design.

Fig. 3(a) shows the equivalent circuit of the SJ LIGBT,

where the SJ block describes the drift region. The pnp transistor has enhanced gain compared to that of a simple drift
region LIGBT due to the presence of the p layer, which acts
as an enhanced hole collector. A more meaningful equivalent
circuit is shown in Fig. 3(b) using two pnp transistors and two
npn transistors to account separately for the n and p layers as
shown below.
T1: NPN n+ source (emitter)/p well (base)/n layer
(collector).
T2: PNP p+ anode (emitter)/n layer (base)/p well (collector).
T3: NPN n+ source (emitter)/p well, p layer (base)/n buffer
(collector).
T4: PNP p+ anode (emitter)/n buffer (base)/p layer
(collector).
The pnp transistors associated with the p layer of the drift
region (T4) has a higher gain than that associated with the n
layer (T2) as it has a narrower base (and wider collector). This
leads to an increased hole current flowing under the p well to
the source short contact. This is to say that the current flowing
through Rshunt is higher thus more easily forward biasing the
two npn transistors. Note that although it looks like T1 and T2
are in a thyristor pair and T3 and T4 are in another thyristor

1414

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 4, APRIL 2013

anode nbur

n layer
p layer

p well

p+

n+

LVpwell p+n+

Forward voltage drop vs latch-up voltage

poly

nbuf DTI n well

BOX

nbur

p- handle wafer

Fig. 4.

Cross sections of new design with split of a:a.

2.40
2.30
2.20
2.10
2.00
1.90
1.80
1.70
1.60
1.50

100
80
60
40
20
bufferwidth=2.0m
length=4a
nn buffer

0
a:a

a:2a

a:4a

L AYOUT S PLITS TO I NVESTIGATE THE N EW D ESIGN I MPACTS

T OWARD V ON AND L ATCH -U P V OLTAGE
Design

Higher p+ to n+ ratio
4a

Same p+ to n+ ratio

a:a

4a:4a

Initial
design

Splits
New design with p+ diffusion to n+ diffusion = 2a:2a

a:2a

1.6E-02

a:4a

1.4E-02

2a:a

1.2E-02

4a:a

1.0E-02

a:a
4a:4a

IA(A)

3a

4a:a

Fig. 5. Tradeoff parameters of latch-up voltage versus VON at 300 A/cm2

when VGS = 5 V at T = 300 K.

a:a
Lower p+ to n+ ratio

2a:a

p+ diffusion : n+ diffusion

TABLE I

Buffer Length

120

n buffer
buffer width=1.5m
n
length=3a

Latch-up voltage (V)

VON (V) at 300A/cm

source/ gate
body

VGS=2V
VGS=3V
VGS=4V
VGS=5V

8.0E-03
6.0E-03
4.0E-03
2.0E-03

pair, one can also form a stronger thyristor made out of the
two higher gain bipolar transistors T1 and T4.
III. E XPERIMENTS AND R ESULTS
Several experiments have been carried out to increase the
latch-up voltage of this device. Fig. 4 illustrates the new design
of the SJ LIGBT.
An extra p well, LVpwell, which shares the same implant
as the baseline device is implemented underneath the n+
source to reduce the Rshunt , with a certain distance away from
the poly gate to avoid any disturbance to channel doping
as shown in Fig. 4. In addition, instead of a long n+ strip,
alternate n+/p+ layers are introduced along the source region
(in z-direction). These alternate p+ diffusion regions are
connected to the p+ body pick-up and butted with the source
and body to allow majority holes to be collected by the p
body directly without flowing through Rshunt . However, it is
still possible for part of the hole current to flow underneath the
n+ source and be collected by the neighboring p+ diffusion in
z-axis and p+ diffusion behind the n+ source in x-axis.
Besides, since part of the n+ source area is reduced, an
increase in the channel resistance and hence a higher VON
is expected. Layout splits in Table I are carried out to investigate the tradeoff parameters with different p+ diffusion and
n+ diffusion layer widths. The device geometry is given in
multiple of a scale factor a. For the result shown here, the
device width is 48a. Fig. 5 presents the variation of latch-up
voltage with VON at gate to source voltage (VGS ) = 5 V from
different splits shown in Table I. The anode is only swept
to 100 V due to measurement limitations. Fig. 6 shows the
measured DC output characteristics of new design with split
of 4a:4a at T = 300 K.

0.0E+00
0

10

20

30

40

50
60
VA(V)

70

80

90

100

Fig. 6. Measured DC output characteristics of new design with split of 4a:4a

at T = 300 K.

IV. D ISCUSSION
In comparison to the initial design, the new design in Fig. 4
successfully increases the latch-up voltage significantly from
23.0 V to about 100 V at VGS of 5 V. This corresponds to
an increase in the current density from 1100 to 1195 A/cm2 .
The VON is slightly increased from 2 to 2.3 V. However, the
increase of VON is considered small (the additional parameter
that can affect VON is carrier lifetime variation, which varies
significantly from wafer to wafer and can result in relatively
larger differences in VON ). With the increase of n+ diffusion
width, the latch-up voltage is reduced from 81 to 68 V. As
the n+ diffusion width is enlarged, the Rshunt is increased
thus more easily forward biasing the base-emitter junction of
the npn transistor (T1). Similarly, a reduction in the total p+
diffusion width results in a reduction in the latch-up voltage.
As it can be seen from Table I and Fig. 5, with an increase in
the p+ diffusion width, the latch-up voltage increases from
81 to (more than) 100 V with about 0.15 V increase in
VON (due to the increase in the MOS channel resistance).
It is worth noting that changing the p+ diffusion width has a
greater impact on the tradeoff parameters than changing the
n+ diffusion width.
Theoretically, an equal and minimum width of p+ diffusion
and n+ diffusion will yield a better latching characteristic as
the hole current is expected to be collected more uniformly
and effectively. However, the results show that a split of 4a:4a

TEE et al.: 200 V SJ N-TYPE LIGBT WITH IMPROVED LATCH-UP CHARACTERISTICS

has an obviously higher latch-up voltage as compared to the

split of a:a although they are having same p+ diffusion width
to n+ diffusion width ratio. This is due to the higher surface
concentration of n+ (Arsenic) diffusion when compared to that
of the p+ (Boron) diffusion. Thus, the a:a split ends up with
a narrower, effective p+ width, as the concentration of the
n+ lateral diffusion is higher than that of the p+ diffusion.
However, in 4a:4a split, the larger widths of each p+ and
n+ diffusion regions make this effect to be negligible, thus
yielding a better latching characteristic. Further investigation
of this parameter is needed to get an optimized width of both
p+ and n+ diffusion regions. Besides, although the split of
4a:4a gives higher latch-up voltage when compared to split
a:a, it has lower saturation current (about 30% less) which
can be both an advantage or a disadvantage depending on the
particular application.

1415

[10] M. Antoniou, F. Udrea, and F. Bauer, Optimisation of SuperJunction

bipolar transistor for ultra-fast switching applications, in Proc. 19th
Int. Symp. Power Semicond. Devices ICs, Jeju, Korea, May. 2005,
pp. 101104.
[11] M. Antoniou, F. Udrea, and F. Bauer, The superjunction insulated gate
bipolar transistor optimization and modeling, IEEE Trans. Electron
Devices, vol. 57, no. 3, pp. 594600, Mar. 2010.
[12] F. Udrea, T. Trajkovic, C. Lee, D. Garner, X. Yuan, J. Joyce, N. Udugampola, G. Bonnet, D. Coulson, and R. Jacques, Ultra-fast LIGBTs and
superjunction devices in membrane technology, in Proc. 17th Int. Symp.
Power Semicond. Devices ICs, Santa Barbara, CA, USA, May. 2005,
pp. 267270.
[13] E. C. T. Kho, A. D. Hoelke, S. J. Pilkington, D. K. Pal, W. A. Wan
Zainal Abidin, Y. N. Liang, M. Antoniou, and F. Udrea, 200-V lateral
superjunction LIGBT on partial SOI , IEEE Electron Device Lett.,
vol. 33, no. 9, pp. 12911293, Sep. 2012.
[14] E. C. T. Kho, A. D. Hoelke, S. J. Pilkington, D. K. Pal, W. A. Wan
Zainal Abidin, Y. N. Liang, M. Antoniou, and F. Udrea, 200-V lateral
superjunction lateral IGBT fabricated on partial SOI in Proc. Accepted
ISPSD Proceess., 2013.

V. C ONCLUSION
The SJ SOI LIGBT is more prone to latch-up when compared to the standard SOI LIGBT. By engineering the source
side of the 200 V device (with alternate p+/n+ diffusion
regions shorted together and placed in the z-axis), we showed
an improvement in the latch-up voltage from 23 (corresponding to a current density of 1100 A/cm2 ) to close to 100 V
(corresponding to a current density of 1195 A/cm2 ) without a
significant penalty in VON . The p+ diffusion regions placed
in the z-axis are able to collect the holes more effectively
by diverting the majority of hole current flow away from
underneath the n+ source and thus preventing the triggering
of the parasitic thyristor responsible for the latch-up.

Elizabeth Kho Ching Tee, photograph and biography are not available at the
time of publication.

Marina Antoniou, photograph and biography are not available at the time of
publication.

Florin Udrea (M90), photograph and biography are not available at the time
of publication.

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Alexander Hlke, photograph and biography are not available at the time of
publication.

Steven John Pilkington, photograph and biography are not available at the
time of publication.

Deb Kumar Pal, photograph and biography are not available at the time of
publication.

Ng Liang Yew, photograph and biography are not available at the time of
publication.

Wan Azlan Bin Wan Zainal Abidin, photograph and biography are not
available at the time of publication.