Op-Amp Design Overview

Operational Amplifier
Stability
Compensation
Miller Effect
Phase Margin
Unity Gain Frequency
Slew Rate Limiting
Reading:
Solomon, The Monolithic IC Op Amp: A
Tutorial Study

Two-stage op-amp

Analysis Strategy
Recognize sub-blocks
Represent as cascade of simple stages

Total op-amp model

Input differential pair Common source stage

DC operating point
MOSFET
M1
M2
M3
M4
M5
M6
M7
M8

ID[A]
25
25
25
25
50
50
50
50

Veff
0.235
0.235
0.247
0.247
0.350
0.332
0.332
0.332

Small signal parameters

MOSFET ID[A]
Veff
gm[A/V] rds
M1
25 0.235
208
M2
25 0.235
800k
M3
25 0.247
M4
25 0.247
1.43M
M5
50 0.350
285
715k
M6
50 0.332
M7
50 0.332
M8
50 0.332
400k
Note: Channel length modulation parameters
n= 0.050 V-1 ; p= 0.028 V-1

Total op-amp model: Low frequency gain

Input differential pair Common source stage

av1 = gm1( rds2 rds 4 )

av2 = gm2 (rds5 rds8 )

av1 = (208A V )(800k! 1.43M!)

av2 = ( 285A V )(400k! 715k!)

av1 = 106

av2 = 73

Total op-amp model with capacitances

Gate of M5
"
F
Cg = (900m)(10m) 4.17E ! 4 2 $
#
m %
Cg = 3.74 pF

Load: scope probe 10pF

Total op-amp model with capacitances

First stage pole

1
f p1 =
2! (rds2 rds4 )Cg5
f p1 =

1
2! (800k" 1.43M")(3.74pF )

f p1 = 82kHz

Second stage pole

1
f p1 =
2! (rds5 rds 8 )CL
f p1 =

1
2! (400k" 715k" )(10 pF )

f p1 = 61kHz

Open loop transfer function

Product of individual stage transfer functions
gm1( rds2 rds 4 )gm5( rds5 rds8 )
A( j!) =
1 + j!2" (rds 2 rds 4 )Cg5 1 + j!2" (rds 5 rds8 )CL

][

Two-stage op-amp: Simulation Schematic

DC Operating Point Simulation

Bode plot (single-pole term)

Magnitude, phase on log scales

Pole: Root of denominator polynomial

Open loop Bode plot

Product of terms : Sum on log-log plot

Open Loop Bode Plot Simulation

Stability example: Closed loop follower

Negative feedback:
Output connected to inverting input

Unity gain: Why bother?

! RL $
& vin
vout = #
" RL + RS %

vout = vin

No buffer:
With buffer:
Voltage divider
No current required
from source
Signal reduced due to
voltage drop across RS

Problem: Instability
Oscillation superimposed on desired output
Output for zero input
Why? Need...

Controls: ES3011 in 20 minutes

General framework
A: Forward Gain
: Feedback Factor
fraction of output
fed back to input

Example: Op-amp, Noninverting Gain

A: Forward Gain
Op-amp open loop gain
Vout=A(V+-V-)
Transfer function A(j)
: Feedback Factor

R1
!=
R1 + R2

Closed Loop Gain

Output

vout = A(vin ! "vout )

14243
v+ ! v!

Solve for vout/vin

vout = Avin ! A"v out

(1 + A")vout = Avin
vout
A
=
vin 1 + A"

Op-amp with negative feedback

If A >> 1
vout
A
A
=
"
vin 1 + A! A!

vout 1
"
vin
!

Closed loop gain determined only by

Advantage of negative feedback:
Open loop gain A can be ugly (nonlinear,
poorly controlled) as long as it's large!

Example: Op-amp, Noninverting Gain

: Feedback Factor
R1
!=
R1 + R2

Closed loop gain

vout R1 + R2 1
=
=
vin
R1
!

Reexamine closed loop transfer function

Output with no input:
vout
A
=
infinite gain
vin 1 + A!
Infinite when 1+A = 0
Condition for oscillation:
1+A = 0
In general A, functions of
If there's a frequency at which 1+A = 0:
Oscillation at that frequency!

Example: follower
!=1 "

vout
A
=
vin 1 + A

Use A(j),
solve for 1+A = 0
No thanks!
gm1( rds2 rds 4 )gm5( rds5 rds8 )
A( j!) =
1 + j!2" (rds 2 rds 4 )Cg5 1 + j!2" (rds 5 rds8 )CL

][

Reexamine condition for oscillation

1+A = 0 A = -1
Magnitude and phase condition:
|A| = 1 AND A = -180
Easier to get from Bode plot

Look at original A for 2 stage op-amp

Find at which |A| = 1; Check A -180 ?

Trouble!

Simulation A for 2 stage op-amp

Compensation: Dominant Pole

Move one pole to
lower frequency
How?

Compensation: Dominant Pole

Need to increase
capacitance
by 1000X:
BAD! Die area cost

Miller Effect
Impedance across inverting gain stage G
Reduced by factor equal to (1+G)

Math for Miller effect

v x " ("Gv x )
ix =
Z
v x (1 + G )
ix =
Z
vx
Z
= Zin =
ix
(1 + G)
Impedance across inverting gain stage G
Reduced by factor equal to (1+G)

Example: Impedance is capacitive

Capacitance multiplied by (1+G)

Z
Zin =
(1+ G)
1
Z=
sC

1
! Zin =
)3
s(1
14
+2
G4
C
C eq

Equivalent capacitance higher by factor 1+G

Problem for high bandwidth amplifiers
Opportunity for compensation ...

Miller Compensation
Need effect of large capacitance
Use Miller effect to multiply small on-chip
capacitance to higher effective value
Effect of large capacitance
without die area cost of large capacitance

New schematic
Add CC across 2nd stage

New transfer function

New step response

No oscillation!

"Phase margin"
How stable is new
transfer function?
Phase margin =
Phase lag at |A| = 1
minus (-180)

Dominant pole op-amp model

Simpler model with dominant pole from CC

Approximate dominant pole transfer function

gm1 (rds 2 rds 4 ) A2

A(j! ) "
1+ j! (rds 2 rds4 )A2CC

A2 = gm5 (rds5 rds8 )

Unity gain frequency

Depends only on
Input stage
transconductance gm
Compensation
capacitor CC

gm1(rds2 rds 4 ) A2
A(j! ) "
!(rds2 rds4 )A2CC

A(j! ) = 1 at ! T
gm1
!T "
CC

Slew rate
I= C dV/dt
Only limited current IBIAS available to charge,
discharge CC

Slew rate
I= C dV/dt

dV
dt

IBIAS
CC

Summary Op-amp:

Stability
Compensation
Miller effect
Phase Margin
Unity gain frequency
Slew Rate Limiting