Proceedings of ESSCIRC, Grenoble, France, 2005

A Novel Current-Mode Very Low Power

Analog CMOS Four Quadrant Multiplier
Mirko Gravati(1), Maurizio Valle(1), Giuseppe Ferri(2), Nicola Guerrini(2) and Linder Reyes(3)
(1) DIBE, University of Genova, Via AllOpera Pia 11/A, I16145 GENOVA, Italy.
(2) DIE, Universit dellAquila, Monteluco di Roio, I67040 L'Aquila, Italy
(3) Instituto de Ingenieria Electrica, Facultad de Ingenieria, Universidad de la Republica, Montevideo, Uruguay
mirkus@micro.dibe.unige.it, valle@dibe.unige.it , ferri@ing.univaq.it ,
guerrini@ing.univaq.it , lreyes@fing.edu.uy

Abstract:
In this paper, a novel current mode CMOS four-quadrant
analog multiplier circuit is presented. The multiplication
is implemented by four translinear loops with MOS
transistors operating in weak inversion. Information
carrying signals are differential balanced currents. The
multiplier circuit has been implemented in a test chip in a
standard 0.35 m CMOS technology. The experimental
measurements (dc bias current of 250 nA and a power
supply of 2.0 V) show a bandwidth of 200 kHz and a
THD figure value lower than 0.9 %. The multiplier
features a wide signal dynamic range and linearity, low
power consumption (the maximum power consumption
is of 5.510-6 W) and very low area (18.7 10-3 mm2). The
multiplier is suitable for a wide range of analog signal
processing applications. Due to the low power and
silicon area consumption, scalability and modularity can
be also easily integrated in massive parallel systems.

1. Introduction
The evolution of integrated circuit technology and future
scenarios of ubiquitous and pervasive computing have
stressed the need of very low power and low voltage
circuits with high signal dynamic range and linearity. We
will focus on analog multipliers as basic blocks of many
analog and mixed-mode systems: e.g. RMS-DC
converters, modulators, frequency synthesizers, massive
parallel systems, etc.
Current inputs current outputs multipliers can achieve
low power, low voltage and high dynamic range. To this
aim, two different implementation approaches can be
found: i) translinear loops with MOS transistors
operating in the strong inversion region [1]; ii) loops
with MOS transistors operating in the weak inversion
region [2]. Both approaches are suitable for standard
CMOS fabrication.
In this paper we present a compact current mode CMOS
four-quadrant analog multiplier circuit based on a novel
topology which adopts the latter approach. The circuit
exhibits wide signal dynamic range, high modularity and
scalability. We designed a test chip using the AMI
Semiconductor CMOS 0.35 Pm minimum channel length
technology and we report main experimental results and
0-7803-9205-1/05/$20.00 2005 IEEE

495

compare them with those reported in [1]. The

experimental results indicate that the circuit achieves
very low power, low voltage, high linearity and silicon
area efficiency.
The paper is organized as follows. Section 2 will present
the multiplier circuit, while Section 3 will introduce and
discuss the experimental results. Conclusions are drawn
in Section 4.

2. Translinear current mode MOS

multiplier circuits
2.1

Modelling MOS translinear loops

In a previous paper [3] we presented a model of MOS

translinear loops operating in weak inversion. We will
use that model to introduce the novel circuit topology
that will be presented in Section 2.2. Hence, we briefly
introduce the model reported in [3]. We refer to the
following expression of the channel current in a MOS
transistor biased in weak inversion [4]:

I DC e

I DS

VGS VTH
nIt

V
 DS

1  e It

Eq. 1
where IDC is a current term, VTH is the threshold voltage,
n is the weak inversion slope factor. The mismatch
between devices causes random variations of the values
of IDCi and VTHi [5]. From Eq. (1) and taking into account
a generic transistor i of a translinear loop, we can define

Gi

G (VDS ) 1  e

VDSi

It

as a generic error term whose

value depends on the drain to source voltage value. If,

due to mismatch between devices, the terms IDCi and VTHi
experience variations (i.e. errors) of 'IDCi and 'VTHi
respectively from their nominal/typical values, then we
can write for a generic transistor i:

I DSi

1  'I DCi I DC e

VGSi VTH
nIt

'VTHi
nIt

Gi

Eq. 2
Please note that in Eq. (2), the term 'IDCi represents the
percentage variation with respect of the nominal value;
on the other hand 'VTHi represents an absolute variation.

Paper 9.E.1

Proceedings of ESSCIRC, Grenoble, France, 2005

is a bias (reference) current. The output current is:

In other words:

1  'I DC  I DC , VTH _ real

I DC _ real

VTH  'VTH

I OUT

Let us take into account the (basic) translinear loop

shown in Fig. 1.
IDS1

IDS2

M1

IDS3

M2

2.2

M4

Novel multiplier circuit topology

I O1

( I X I W ) I B . The transistors M7, M8, M11 and

M12

(translinear

operation: I O 2

Figure 1: Generic (alternate) translinear loop.

loop)

implement

the

following

 
X W

( I I ) I B . The currents IO1 and IO2

are summed at node n2; the result is the positive single

ended
term
of
the
output
current
IOUT+:

After some mathematical computations one can obtain:

I DS 1 I DS 3

xwI B .

In this paper we present a novel circuit topology that is

shown in Figure 2. The transistors M1, M2, M3 and M4
(translinear loop) implement the following operation:

IDS4

M3



I OUT
 I OUT

J I DS 2 I DS 4


I OUT

Eq. 3
where we have approximated n to the value of one. In the

I X I W  ( I X I W ) I B .

I O1  I O 2

Iout-

Iout+

(n1)

(n2)

Iw+

IB

M1

Io1

M2

M3

I x+

I x-

M4

M5

Io3

M6

Iw-

IB

M7

Io4

M8

I x+

I x-

M10

M9

M11

Io2

M12

(np)

+
VPOL

Mp2

Mp1

previous equation, we introduced a non linearity factor

J which takes into account the effects of mismatch
between the devices belonging to the translinear loop.
The term J is defined as follows:
1  'I DC1  1  'I DC3  G1G 3 e 'VTH 1 'VTH 3n'It VTH 2 'VTH 4
J
1  'I DC2 1  'I DC4  G 2G 4
Eq. 4
The non linearity factor J is given, besides by the spread
of the technological parameters 'IDCi and 'VTHi, by the
bias point value through the terms

Gi 1 e

Figure 2: Novel multiplier circuit topology

In a similar way, the current term IO3 (the result of the
operation of the translinear loop made by transistors M1,
M2, M5 and M6) is summed at node n1 to the current
term IO4 (the result of the operation of the translinear
loop made by transistors M7, M8, M9 and M10). The
result is the negative single ended term of the output
current
IOUT-:

I OUT

VDSi

It

(1  x)( I B 2), I X
(1  w)( I B 2), I W

I X I W  ( I X I W ) I B .

It has been verified through experimental measurements

that the translinear loops are rather insensitive to the
value of VPOL to a large extent (i.e. [0.5 y1.2] V). Then,
to simplify the circuit, one can substitute the bias voltage
generator VPOL with a transistor working in the linear
region (transistor Mb1, see Figure 3)

. In the

following we will consider all terms Gi equal to 1. The

error given by this approximation is fairly low: in fact if,
let say, VDS is equal to only 100 mV, the error is in the
order of magnitude of about 0.05%. Please note that the
non linearity term J depends also on the topology of the
circuit and on the layout design (i.e. matching
structures). In particular, J = 1 in the case of ideal
matching between the devices of the translinear loop. In
the following subsections we will apply the previous
model to the novel four quadrant current mode
translinear multiplier circuit. In the following we will
consider input (IX and IW) and output (IOUT) signals as
differential and balanced current mode signals:

I X
I W

I O3  I O 4

Iw+

IB

(np)

Mb1

(1  x)( I B 2)
(1  w)( I B 2)

Mp1

Figure 3: Circuit implementation of VPOL.

Due to the spread of technological parameters, each
translinear loop introduces a non linearity term Ji (i=1:4,
See Eq. (4)).

where x and w are the input information carrying

variables (please note that -1 d x d+1, -1 dw d+1) and IB
496

Proceedings of ESSCIRC, Grenoble, France, 2005

The output current can be expressed as:

I OUT

I offset  > Ax x  Aw w  AI xw@

where:

AI

Ax

1,0

Eq. 5

0,5

J1  J 2  J 3  J 4 ,
IB
,
4

Iout/ IB

J 1  J 2  J 3  J 4 

I offset

IB
4

x = -1
x = -0.6
x = -0.3
x=0
x = +0.3
x = +0.6
x = +1

0,0

-0,5

J 1  J 2  J 3  J 4 , Aw J 1  J 2  J 3  J 4 .
-1,0

The proposed multiplier circuit topology is more

symmetric and exhibits the following advantages over
the standard current mode MOS Gilbert multiplier ([6]):
a) The expression of the output current (see Eq. (5)) does
not present any higher order term of the inputs (i.e.

x 2 , x 3 .. w 2 , w3 .. ) even in the case that mismatch is

taken into account. b) If the non linearity terms Ji assume
similar values (i.e. in the case of matching inside and
between the transistors of translinear loops) then the
terms AI, Ax, Aw, Ioffset tend to decrease and the overall
linearity increases. C) In the expressions of AI, Ax, Aw,
Ioffset, terms in the form of JiJj (izj) are not present.

-0,5

0,0

0,5

1,0

w [-1:1]

Figure 5: Measured DC transfer characteristics

Fig. 6 shows the DC measured transfer
characteristics of the multiplier in the case: x input is on
the x axis, and the w input is used as parameter.
1,0

0,5

Iout/ IB

3. Experimental results

-1,0

w = -1
w = -0.6
w = -0.3
w=0
w = +0.3
w = +0.6
w = +1

0,0

-0,5

We designed a test chip by using the AMI

Semiconductor CMOS 0.35 Pm minimum channel length
double metal, double poly technology. The
microphotograph of the multiplier is shown in Fig. 4.
The multiplier area is of about 170 Pm u 110 Pm.

-1,0

-1,0

-0,5

0,0

0,5

1,0

x [-1:1]

170Pm

Figure 6: Measured DC transfer characteristics

Absolute error [nA]

110Pm

Translinear loops

One can note that the multiplier exhibits linear

behaviour with respect to both inputs.
The static linearity error is shown in Fig. 7.

Figure 4: Microphotograph of the multiplier

The transistors sizes are reported in the Table 1.
Transistor
W [Pm] /L
[Pm]

Mp1-Mp2 Mb1-Mb2

1/6

3/10

M1-M2-M3-M4M5-M6-M7-M8M9-M10-M11M12

x = -1
x = -0.6
x = -0.3
x = +0.3
x = +0.6
x = +1

-1

-2

-1,0

-0,5

0,0

0,5

1,0

w [-1:1]

60/1

Figure 7: Linearity error

Table 1: sizes of transistors (see Fig. 2 and Fig. 3)

In all the following measurement results, IB was set at
250 nA; IOUT+ and IOUT- vary in the range [0nA y 250nA],
while IOUT varies in the range [-250nA y +250nA].
Fig. 5 shows the DC measured transfer characteristics of
the multiplier. The w input is on the x axis, and the x
input is used as parameter.

497

The measured -3 dB Band Width is of 200 kHz. The

maximum power consumption is of 5.5 10-6 W.
The total harmonic distortion (THD) of the output
current versus the input signal level is shown in Fig. 8.

Proceedings of ESSCIRC, Grenoble, France, 2005

multiplier. With respect to other well known topologies,

the proposed circuit is linear with respect to both inputs
We compared the proposed circuit topology with the
standard MOS current mode Gilbert multiplier ([6]) and
we found that our multiplier achieves higher linearity.
When compared to state-of-the-art voltage- translinear
CMOS multiplier circuits, such as that proposed in [1],
the performances of the multiplier proposed here are
similar in terms of linearity (see Table 2). Nevertheless,
the power consumption and silicon area are
impressively lower also taking into account the smaller
minimum channel length given by the technology.

1,0

0,8

THD [%]

0,6

x input
w input

0,4

0,2

0,0
20

40

60

80

100

120

140

160

180

200

Modulated input current [nA]

Figure 8: THD of the output waveform for different input

amplitudes.
The magnitude spectrum of the output current waveform
is shown in Fig. 9: the w input is a 1kHz sinusoidal
waveform with a peak value of 112 nA, (W = 0.45) and
the x input is a DC input with a value of 210 nA (X =
0.84).

Multiplier

[1]

Technology (CMOS)

2.4 m

This
paper
0.35 m

Supply voltage [V]

3.3

2.0

THD as gain cell [%]

(measured)

1.5

0.9

Max. rel. error as multiplier

[%] (measured)

1.9

BW as gain cell

3 MHz

200 kHz

(simulated)

(measured)

Area [mm2]

0.24

18.7 10-3

Power consumption [W]

600

5.5

Table 2
Our long term goal is to design multiplier circuit
topologies able to effectively operate at very low current
values [7].

Figure 9: Magnitude spectrum of the output current

waveform.
Figure 10 shows the experimental results obtained by
modulating a 4 kHz high frequency sinusoidal signal
with a peak value of 160nA, (w = 0.64) with a 100 Hz
low frequency sinusoidal signal with a peak value of 40
nA (x = 0.16).

Figure 10. Output current waveform in the case of

waveforms modulation.

4. Conclusions
In this paper we present the circuit topology of a
novel analog CMOS four quadrant current mode
498

References:
[1] A. J. Lopez-Martin, A. Carlosena, Current-Mode
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subtrsheold CMOS, Analog Integrated Circuits and Signal
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submitted to ECCTD05, Cork, Ireland, 29 august 1
september 2005.
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