08/01/2015

1.1TypesofASICs

[Chapterstart][Previouspage][Nextpage]
PortionsfromApplicationSpecificIntegratedCircuitsCopyright1997byAddison
WesleyLongman,Inc.

1.1TypesofASICs
ICsaremadeonathin(afewhundredmicronsthick),circularsiliconwafer,with
eachwaferholdinghundredsofdie(sometimespeopleusediesordicefortheplural
ofdie).Thetransistorsandwiringaremadefrommanylayers(usuallybetween10
and15distinctlayers)builtontopofoneanother.Eachsuccessivemasklayerhasa
patternthatisdefinedusingamasksimilartoaglassphotographicslide.Thefirst
halfdozenorsolayersdefinethetransistors.Thelasthalfdozenorsolayersdefine
themetalwiresbetweenthetransistors(theinterconnect).
AfullcustomICincludessome(possiblyall)logiccellsthatarecustomizedand
allmasklayersthatarecustomized.Amicroprocessorisanexampleofafullcustom
ICdesignersspendmanyhourssqueezingthemostoutofeverylastsquaremicron
ofmicroprocessorchipspacebyhand.CustomizingalloftheICfeaturesinthisway
allowsdesignerstoincludeanalogcircuits,optimizedmemorycells,ormechanical
structuresonanIC,forexample.FullcustomICsarethemostexpensiveto
manufactureandtodesign.Themanufacturingleadtime(thetimeittakesjustto
makeanICnotincludingdesigntime)istypicallyeightweeksforafullcustomIC.
ThesespecializedfullcustomICsareoftenintendedforaspecificapplication,sowe
mightcallsomeofthemfullcustomASICs.
WeshalldiscussfullcustomASICsbrieflynext,butthemembersoftheICfamily
thatwearemoreinterestedinaresemicustomASICs,forwhichallofthelogiccells
arepredesignedandsome(possiblyall)ofthemasklayersarecustomized.Using
predesignedcellsfromacelllibrarymakesourlivesasdesignersmuch,mucheasier.
TherearetwotypesofsemicustomASICsthatweshallcover:standardcellbased
ASICsandgatearraybasedASICs.Followingthisweshalldescribethe
programmableASICs,forwhichallofthelogiccellsarepredesignedandnoneof
themasklayersarecustomized.TherearetwotypesofprogrammableASICs:the
programmablelogicdeviceand,thenewestmemberoftheASICfamily,thefield
programmablegatearray.
http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

1/14

08/01/2015

1.1TypesofASICs

1.1.1FullCustomASICs
InafullcustomASICanengineerdesignssomeorallofthelogiccells,circuits,or
layoutspecificallyforoneASIC.Thismeansthedesignerabandonstheapproachof
usingpretestedandprecharacterizedcellsforallorpartofthatdesign.Itmakessense
totakethisapproachonlyiftherearenosuitableexistingcelllibrariesavailablethat
canbeusedfortheentiredesign.Thismightbebecauseexistingcelllibrariesarenot
fastenough,orthelogiccellsarenotsmallenoughorconsumetoomuchpower.You
mayneedtousefullcustomdesigniftheASICtechnologyisneworsospecialized
thattherearenoexistingcelllibrariesorbecausetheASICissospecializedthatsome
circuitsmustbecustomdesigned.FewerandfewerfullcustomICsarebeingdesigned
becauseoftheproblemswiththesespecialpartsoftheASIC.Thereisonegrowing
memberofthisfamily,though,themixedanalog/digitalASIC,whichweshalldiscuss
next.
Bipolartechnologyhashistoricallybeenusedforprecisionanalogfunctions.There
aresomefundamentalreasonsforthis.Inallintegratedcircuitsthematchingof
componentcharacteristicsbetweenchipsisverypoor,whilethematchingof
characteristicsbetweencomponentsonthesamechipisexcellent.Supposewehave
transistorsT1,T2,andT3onananalog/digitalASIC.Thethreetransistorsareallthe
samesizeandareconstructedinanidenticalfashion.TransistorsT1andT2are
locatedadjacenttoeachotherandhavethesameorientation.TransistorT3isthesame
sizeasT1andT2butislocatedontheothersideofthechipfromT1andT2andhasa
differentorientation.ICsaremadeinbatchescalledwaferlots.Awaferlotisagroup
ofsiliconwafersthatareallprocessedtogether.Usuallytherearebetween5and30
wafersinalot.Eachwafercancontaintensorhundredsofchipsdependingonthe
sizeoftheICandthewafer.
IfweweretomakemeasurementsofthecharacteristicsoftransistorsT1,T2,and
T3wewouldfindthefollowing:
TransistorsT1willhavevirtuallyidenticalcharacteristicstoT2onthesameIC.
Wesaythatthetransistorsmatchwellorthetrackingbetweendevicesis
excellent.
TransistorT3willmatchtransistorsT1andT2onthesameICverywell,butnot
ascloselyasT1matchesT2onthesameIC.
TransistorT1,T2,andT3willmatchfairlywellwithtransistorsT1,T2,andT3
onadifferentIConthesamewafer.Thematchingwilldependonhowfarapart
thetwoICsareonthewafer.
TransistorsonICsfromdifferentwafersinthesamewaferlotwillnotmatchvery
http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

2/14

08/01/2015

1.1TypesofASICs

well.
TransistorsonICsfromdifferentwaferlotswillmatchverypoorly.
Formanyanalogdesignstheclosematchingoftransistorsiscrucialtocircuit
operation.Forthesecircuitdesignspairsoftransistorsareused,locatedadjacentto
eachother.Devicephysicsdictatesthatapairofbipolartransistorswillalwaysmatch
morepreciselythanCMOStransistorsofacomparablesize.Bipolartechnologyhas
historicallybeenmorewidelyusedforfullcustomanalogdesignbecauseofits
improvedprecision.Despiteitspooreranalogproperties,theuseofCMOStechnology
foranalogfunctionsisincreasing.Therearetworeasonsforthis.Thefirstreasonis
thatCMOSisnowbyfarthemostwidelyavailableICtechnology.ManymoreCMOS
ASICsandCMOSstandardproductsarenowbeingmanufacturedthanbipolarICs.
Thesecondreasonisthatincreasedlevelsofintegrationrequiremixinganalogand
digitalfunctionsonthesameIC:thishasforceddesignerstofindwaystouseCMOS
technologytoimplementanalogfunctions.Circuitdesigners,usingclevernew
techniques,havebeenverysuccessfulinfindingnewwaystodesignanalogCMOS
circuitsthatcanapproachtheaccuracyofbipolaranalogdesigns.

1.1.2StandardCellBasedASICs
AcellbasedASIC(cellbasedIC,orCBICacommonterminJapan,pronounced
seabick)usespredesignedlogiccells(ANDgates,ORgates,multiplexers,andflip
flops,forexample)knownasstandardcells.WecouldapplythetermCBICtoany
ICthatusescells,butitisgenerallyacceptedthatacellbasedASICorCBICmeansa
standardcellbasedASIC.
Thestandardcellareas(alsocalledflexibleblocks)inaCBICarebuiltofrowsof
standardcellslikeawallbuiltofbricks.Thestandardcellareasmaybeusedin
combinationwithlargerpredesignedcells,perhapsmicrocontrollersoreven
microprocessors,knownasmegacells.Megacellsarealsocalledmegafunctions,full
customblocks,systemlevelmacros(SLMs),fixedblocks,cores,orFunctional
StandardBlocks(FSBs).
TheASICdesignerdefinesonlytheplacementofthestandardcellsandthe
interconnectinaCBIC.However,thestandardcellscanbeplacedanywhereonthe
siliconthismeansthatallthemasklayersofaCBICarecustomizedandareuniqueto
aparticularcustomer.TheadvantageofCBICsisthatdesignerssavetime,money,
andreduceriskbyusingapredesigned,pretested,andprecharacterizedstandardcell
library.Inadditioneachstandardcellcanbeoptimizedindividually.Duringthe
designofthecelllibraryeachandeverytransistorineverystandardcellcanbechosen
http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

3/14

08/01/2015

1.1TypesofASICs

tomaximizespeedorminimizearea,forexample.Thedisadvantagesarethetimeor
expenseofdesigningorbuyingthestandardcelllibraryandthetimeneededto
fabricatealllayersoftheASICforeachnewdesign.
Figure1.2showsaCBIC(lookingdownonthedieshowninFigure1.1b,for
example).TheimportantfeaturesofthistypeofASICareasfollows:
Allmasklayersarecustomizedtransistorsandinterconnect.
Customblockscanbeembedded.
Manufacturingleadtimeisabouteightweeks.
FIGURE1.2AcellbasedASIC(CBIC)diewith
asinglestandardcellarea(aflexibleblock)
togetherwithfourfixedblocks.Theflexible
blockcontainsrowsofstandardcells.Thisis
whatyoumightseethroughalowpowered
microscopelookingdownonthedieof
Figure1.1(b).Thesmallsquaresaroundthe
edgeofthediearebondingpadsthatare
connectedtothepinsoftheASICpackage.

Eachstandardcellinthelibraryisconstructedusingfullcustomdesignmethods,
butyoucanusethesepredesignedandprecharacterizedcircuitswithouthavingtodo
anyfullcustomdesignyourself.Thisdesignstylegivesyouthesameperformance
andflexibilityadvantagesofafullcustomASICbutreducesdesigntimeandreduces
risk.
Standardcellsaredesignedtofittogetherlikebricksinawall.Figure1.3showsan
exampleofasimplestandardcell(itissimpleinthesenseitisnotmaximizedfor
densitybutidealforshowingyouitsinternalconstruction).Powerandgroundbuses
(VDDandGNDorVSS)runhorizontallyonmetallinesinsidethecells.

http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

4/14

08/01/2015

1.1TypesofASICs

FIGURE1.3Lookingdownonthelayoutofastandardcell.This
cellwouldbeapproximately25micronswideonanASICwith
(lambda)=0.25microns(amicronis106m).Standardcellsare
stackedlikebricksinawalltheabutmentbox(AB)definesthe
edgesofthebrick.Thedifferencebetweentheboundingbox
(BB)andtheABistheareaofoverlapbetweenthebricks.Power
supplies(labeledVDDandGND)runhorizontallyinsidea
standardcellonametallayerthatliesabovethetransistorlayers.
Eachdifferentshadedandlabeledpatternrepresentsadifferent
layer.Thisstandardcellhascenterconnectors(thethree
squares,labeledA1,B1,andZ)thatallowthecelltoconnectto
others.ThelayoutwasdrawnusingROSE,asymboliclayout
editordevelopedbyRockwellandCompass,andthenimported
intoTannerResearchsLEdit.
StandardcelldesignallowstheautomationoftheprocessofassemblinganASIC.
Groupsofstandardcellsfithorizontallytogethertoformrows.Therowsstack
verticallytoformflexiblerectangularblocks(whichyoucanreshapeduringdesign).
Youmaythenconnectaflexibleblockbuiltfromseveralrowsofstandardcellsto
otherstandardcellblocksorotherfullcustomlogicblocks.Forexample,youmight
wanttoincludeacustominterfacetoastandard,predesignedmicrocontrollertogether
withsomememory.Themicrocontrollerblockmaybeafixedsizemegacell,you
mightgeneratethememoryusingamemorycompiler,andthecustomlogicand
memorycontrollerwillbebuiltfromflexiblestandardcellblocks,shapedtofitinthe
emptyspacesonthechip.
BothcellbasedandgatearrayASICsusepredefinedcells,butthereisadifference
http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

5/14

08/01/2015

1.1TypesofASICs

wecanchangethetransistorsizesinastandardcelltooptimizespeedand
performance,butthedevicesizesinagatearrayarefixed.Thisresultsinatradeoffin
performanceandareainagatearrayatthesiliconlevel.Thetradeoffbetweenarea
andperformanceismadeatthelibrarylevelforastandardcellASIC.
ModernCMOSASICsusetwo,three,ormorelevels(orlayers)ofmetalfor
interconnect.Thisallowswirestocrossoverdifferentlayersinthesamewaythatwe
usecoppertracesondifferentlayersonaprintedcircuitboard.Inatwolevelmetal
CMOStechnology,connectionstothestandardcellinputsandoutputsareusually
madeusingthesecondlevelofmetal(metal2,theupperlevelofmetal)atthetops
andbottomsofthecells.Inathreelevelmetaltechnology,connectionsmaybe
internaltothelogiccell(astheyareinFigure1.3).Thisallowsformoresophisticated
routingprogramstotakeadvantageoftheextrametallayertorouteinterconnectover
thetopofthelogiccells.WeshallcoverthedetailsofroutingASICsinChapter17.
Aconnectionthatneedstocrossoverarowofstandardcellsusesafeedthrough.
Thetermfeedthroughcanrefereithertothepieceofmetalthatisusedtopassa
signalthroughacellortoaspaceinacellwaitingtobeusedasafeedthroughvery
confusing.Figure1.4showstwofeedthroughs:oneincellA.14andoneincellA.23.
Inbothtwolevelandthreelevelmetaltechnology,thepowerbuses(VDDand
GND)insidethestandardcellsnormallyusethelowest(closesttothetransistors)
layerofmetal(metal1).Thewidthofeachrowofstandardcellsisadjustedsothat
theymaybealignedusingspacercells.Thepowerbuses,orrails,arethenconnected
toadditionalverticalpowerrailsusingrowendcellsatthealignedendsofeach
standardcellblock.Iftherowsofstandardcellsarelong,thenverticalpowerrailscan
alsoberuninmetal2throughthecellrowsusingspecialpowercellsthatjustconnect
toVDDandGND.Usuallythedesignermanuallycontrolsthenumberandwidthof
theverticalpowerrailsconnectedtothestandardcellblocksduringphysicaldesign.
AdiagramofthepowerdistributionschemeforaCBICisshowninFigure1.4.

http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

6/14

08/01/2015

1.1TypesofASICs

FIGURE1.4RoutingtheCBIC(cellbasedIC)shownin
Figure1.2.Theuseofregularlyshapedstandardcells,suchas
theoneinFigure1.3,fromalibraryallowsASICslikethistobe
designedautomatically.ThisASICusestwoseparatelayersof
metalinterconnect(metal1andmetal2)runningatrightanglesto
eachother(liketracesonaprintedcircuitboard).
Interconnectionsbetweenlogiccellsusesspaces(called
channels)betweentherowsofcells.ASICsmayhavethree(or
more)layersofmetalallowingthecellrowstotouchwiththe
interconnectrunningoverthetopofthecells.
AllthemasklayersofaCBICarecustomized.Thisallowsmegacells(SRAM,a
SCSIcontroller,oranMPEGdecoder,forexample)tobeplacedonthesameICwith
standardcells.MegacellsareusuallysuppliedbyanASICorlibrarycompany
completewithbehavioralmodelsandsomewaytotestthem(ateststrategy).ASIC
librarycompaniesalsosupplycompilerstogenerateflexibleDRAM,SRAM,and
ROMblocks.Sinceallmasklayersonastandardcelldesignarecustomized,memory
designismoreefficientanddenserthanforgatearrays.
Forlogicthatoperatesonmultiplesignalsacrossadatabusadatapath(DP)
theuseofstandardcellsmaynotbethemostefficientASICdesignstyle.SomeASIC
librarycompaniesprovideadatapathcompilerthatautomaticallygenerates
datapathlogic.Adatapathlibrarytypicallycontainscellssuchasadders,
subtracters,multipliers,andsimplearithmeticandlogicalunits(ALUs).The
connectorsofdatapathlibrarycellsarepitchmatchedtoeachothersothattheyfit
together.Connectingdatapathcellstoformadatapathusually,butnotalways,results
infasteranddenserlayoutthanusingstandardcellsoragatearray.
Standardcellandgatearraylibrariesmaycontainhundredsofdifferentlogiccells,
http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

7/14

08/01/2015

1.1TypesofASICs

includingcombinationalfunctions(NAND,NOR,AND,ORgates)withmultiple
inputs,aswellaslatchesandflipflopswithdifferentcombinationsofreset,presetand
clockingoptions.TheASIClibrarycompanyprovidesdesignerswithadatabookin
paperorelectronicformwithallofthefunctionaldescriptionsandtiminginformation
foreachlibraryelement.

1.1.3GateArrayBasedASICs
Inagatearray(sometimesabbreviatedtoGA)orgatearraybasedASICthe
transistorsarepredefinedonthesiliconwafer.Thepredefinedpatternoftransistorson
agatearrayisthebasearray,andthesmallestelementthatisreplicatedtomakethe
basearray(likeanM.C.Escherdrawing,ortilesonafloor)isthebasecell
(sometimescalledaprimitivecell).Onlythetopfewlayersofmetal,whichdefine
theinterconnectbetweentransistors,aredefinedbythedesignerusingcustommasks.
Todistinguishthistypeofgatearrayfromothertypesofgatearray,itisoftencalleda
maskedgatearray(MGA).Thedesignerchoosesfromagatearraylibraryof
predesignedandprecharacterizedlogiccells.Thelogiccellsinagatearraylibraryare
oftencalledmacros.Thereasonforthisisthatthebasecelllayoutisthesamefor
eachlogiccell,andonlytheinterconnect(insidecellsandbetweencells)is
customized,sothatthereisasimilaritybetweengatearraymacrosandasoftware
macro.InsideIBM,gatearraymacrosareknownasbooks(sothatbooksarepartofa
library),butunfortunatelythisdescriptivetermisnotverywidelyusedoutsideIBM.
Wecancompletethediffusionstepsthatformthetransistorsandthenstockpile
wafers(sometimeswecallagatearrayaprediffusedarrayforthisreason).Since
onlythemetalinterconnectionsareuniquetoanMGA,wecanusethestockpiled
wafersfordifferentcustomersasneeded.Usingwafersprefabricateduptothe
metallizationstepsreducesthetimeneededtomakeanMGA,theturnaroundtime,
toafewdaysoratmostacoupleofweeks.Thecostsforalltheinitialfabrication
stepsforanMGAaresharedforeachcustomerandthisreducesthecostofanMGA
comparedtoafullcustomorstandardcellASICdesign.
TherearethefollowingdifferenttypesofMGAorgatearraybasedASICs:
Channeledgatearrays.
Channellessgatearrays.
Structuredgatearrays.
Thehyphenationofthesetermswhentheyareusedasadjectivesexplainstheir
construction.Forexample,inthetermchanneledgatearrayarchitecture,thegate
http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

8/14

08/01/2015

1.1TypesofASICs

arrayischanneled,aswillbeexplained.Therearetwocommonwaysofarranging
(orarraying)thetransistorsonaMGA:inachanneledgatearrayweleavespace
betweentherowsoftransistorsforwiringtheroutingonachannellessgatearrayuses
rowsofunusedtransistors.Thechanneledgatearraywasthefirsttobedeveloped,but
thechannellessgatearrayarchitectureisnowmorewidelyused.Astructured(or
embedded)gatearraycanbeeitherchanneledorchannellessbutitincludes(or
embeds)acustomblock.

1.1.4ChanneledGateArray
Figure1.5showsachanneledgatearray.Theimportantfeaturesofthistypeof
MGAare:
Onlytheinterconnectiscustomized.
Theinterconnectusespredefinedspacesbetweenrowsofbasecells.
Manufacturingleadtimeisbetweentwodaysandtwoweeks.

FIGURE1.5Achanneledgatearraydie.Thespaces
betweenrowsofthebasecellsaresetasidefor
interconnect.

AchanneledgatearrayissimilartoaCBICbothuserowsofcellsseparatedby
channelsusedforinterconnect.Onedifferenceisthatthespaceforinterconnect
betweenrowsofcellsarefixedinheightinachanneledgatearray,whereasthespace
betweenrowsofcellsmaybeadjustedinaCBIC.

1.1.5ChannellessGateArray
Figure1.6showsachannellessgatearray(alsoknownasachannelfreegatearray
,seaofgatesarray,orSOGarray).TheimportantfeaturesofthistypeofMGAare
asfollows:
Onlysome(thetopfew)masklayersarecustomizedtheinterconnect.
Manufacturingleadtimeisbetweentwodaysandtwoweeks.
http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

9/14

08/01/2015

1.1TypesofASICs

FIGURE1.6Achannellessgatearrayorseaofgates
(SOG)arraydie.Thecoreareaofthedieis
completelyfilledwithanarrayofbasecells(thebase
array).

Thekeydifferencebetweenachannellessgatearrayandchanneledgatearrayis
thattherearenopredefinedareassetasideforroutingbetweencellsonachannelless
gatearray.Insteadwerouteoverthetopofthegatearraydevices.Wecandothis
becausewecustomizethecontactlayerthatdefinestheconnectionsbetweenmetal1,
thefirstlayerofmetal,andthetransistors.Whenweuseanareaoftransistorsfor
routinginachannellessarray,wedonotmakeanycontactstothedeviceslying
underneathwesimplyleavethetransistorsunused.
Thelogicdensitytheamountoflogicthatcanbeimplementedinagivensilicon
areaishigherforchannellessgatearraysthanforchanneledgatearrays.Thisis
usuallyattributedtothedifferenceinstructurebetweenthetwotypesofarray.Infact,
thedifferenceoccursbecausethecontactmaskiscustomizedinachannellessgate
array,butisnotusuallycustomizedinachanneledgatearray.Thisleadstodenser
cellsinthechannellessarchitectures.Customizingthecontactlayerinachannelless
gatearrayallowsustoincreasethedensityofgatearraycellsbecausewecanroute
overthetopofunusedcontactsites.

1.1.6StructuredGateArray
Anembeddedgatearrayorstructuredgatearray(alsoknownasmastersliceor
masterimage)combinessomeofthefeaturesofCBICsandMGAs.Oneofthe
disadvantagesoftheMGAisthefixedgatearraybasecell.Thismakesthe
implementationofmemory,forexample,difficultandinefficient.Inanembedded
gatearraywesetasidesomeoftheICareaanddedicateittoaspecificfunction.This
embeddedareaeithercancontainadifferentbasecellthatismoresuitablefor
buildingmemorycells,oritcancontainacompletecircuitblock,suchasa
microcontroller.
Figure1.7showsanembeddedgatearray.Theimportantfeaturesofthistypeof
MGAarethefollowing:
http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

10/14

08/01/2015

1.1TypesofASICs

Onlytheinterconnectiscustomized.
Customblocks(thesameforeachdesign)canbeembedded.
Manufacturingleadtimeisbetweentwodaysandtwoweeks.

FIGURE1.7Astructuredorembeddedgate
arraydieshowinganembeddedblockinthe
upperleftcorner(astaticrandomaccess
memory,forexample).Therestofthedieis
filledwithanarrayofbasecells.

Anembeddedgatearraygivestheimprovedareaefficiencyandincreased
performanceofaCBICbutwiththelowercostandfasterturnaroundofanMGA.One
disadvantageofanembeddedgatearrayisthattheembeddedfunctionisfixed.For
example,ifanembeddedgatearraycontainsanareasetasidefora32kbitmemory,
butweonlyneeda16kbitmemory,thenwemayhavetowastehalfoftheembedded
memoryfunction.However,thismaystillbemoreefficientandcheaperthan
implementinga32kbitmemoryusingmacrosonaSOGarray.
ASICvendorsmayofferseveralembeddedgatearraystructurescontaining
differentmemorytypesandsizesaswellasavarietyofembeddedfunctions.ASIC
companieswishingtoofferawiderangeofembeddedfunctionsmustensurethat
enoughcustomersuseeachdifferentembeddedgatearraytogivethecostadvantages
overacustomgatearrayorCBIC(theSunMicrosystemsSPARCstation1described
inSection1.3madeuseofLSILogicembeddedgatearraysandthe10Kand100K
seriesofembeddedgatearraysweretwoofLSILogicsmostsuccessfulproducts).

1.1.7ProgrammableLogicDevices
Programmablelogicdevices(PLDs)arestandardICsthatareavailableinstandard
configurationsfromacatalogofpartsandaresoldinveryhighvolumetomany
differentcustomers.However,PLDsmaybeconfiguredorprogrammedtocreatea
partcustomizedtoaspecificapplication,andsotheyalsobelongtothefamilyof
ASICs.PLDsusedifferenttechnologiestoallowprogrammingofthedevice.
Figure1.8showsaPLDandthefollowingimportantfeaturesthatallPLDshavein
common:
http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

11/14

08/01/2015

1.1TypesofASICs

Nocustomizedmasklayersorlogiccells
Fastdesignturnaround
Asinglelargeblockofprogrammableinterconnect
Amatrixoflogicmacrocellsthatusuallyconsistofprogrammablearraylogic
followedbyaflipfloporlatch

FIGURE1.8Aprogrammablelogicdevice
(PLD)die.Themacrocellstypicallyconsistof
programmablearraylogicfollowedbyaflipflop
orlatch.Themacrocellsareconnectedusinga
largeprogrammableinterconnectblock.

ThesimplesttypeofprogrammableICisareadonlymemory(ROM).Themost
commontypesofROMuseametalfusethatcanbeblownpermanently(a
programmableROMorPROM).AnelectricallyprogrammableROM,or
EPROM,usesprogrammableMOStransistorswhosecharacteristicsarealteredby
applyingahighvoltage.YoucaneraseanEPROMeitherbyusinganotherhigh
voltage(anelectricallyerasablePROM,orEEPROM)orbyexposingthedevice
toultravioletlight(UVerasablePROM,orUVPROM).
ThereisanothertypeofROMthatcanbeplacedonanyASICamask
programmableROM(maskprogrammedROMormaskedROM).AmaskedROM
isaregulararrayoftransistorspermanentlyprogrammedusingcustommaskpatterns.
AnembeddedmaskedROMisthusalarge,specialized,logiccell.
ThesameprogrammabletechnologiesusedtomakeROMscanbeappliedtomore
flexiblelogicstructures.ByusingtheprogrammabledevicesinalargearrayofAND
gatesandanarrayofORgates,wecreateafamilyofflexibleandprogrammablelogic
devicescalledlogicarrays.ThecompanyMonolithicMemories(boughtbyAMD)
wasthefirsttoproduceProgrammableArrayLogic(PAL,aregisteredtrademark
ofAMD)devicesthatyoucanuse,forexample,astransitiondecodersforstate
machines.APALcanalsoincluderegisters(flipflops)tostorethecurrentstate
informationsothatyoucanuseaPALtomakeacompletestatemachine.
JustaswehaveamaskprogrammableROM,wecouldplacealogicarrayasacell
onacustomASIC.Thistypeoflogicarrayiscalledaprogrammablelogicarray
(PLA).ThereisadifferencebetweenaPALandaPLA:aPLAhasaprogrammable
http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

12/14

08/01/2015

1.1TypesofASICs

ANDlogicarray,orANDplane,followedbyaprogrammableORlogicarray,orOR
planeaPALhasaprogrammableANDplaneand,incontrasttoaPLA,afixedOR
plane.
DependingonhowthePLDisprogrammed,wecanhaveanerasablePLD
(EPLD),ormaskprogrammedPLD(sometimescalledamaskedPLDbutusually
justPLD).ThefirstPALs,PLAs,andPLDswerebasedonbipolartechnologyand
usedprogrammablefusesorlinks.CMOSPLDsusuallyemployfloatinggate
transistors(seeSection4.3,EPROMandEEPROMTechnology).

1.1.8FieldProgrammableGateArrays
AstepabovethePLDincomplexityisthefieldprogrammablegatearray(FPGA
).ThereisverylittledifferencebetweenanFPGAandaPLDanFPGAisusually
justlargerandmorecomplexthanaPLD.Infact,somecompaniesthatmanufacture
programmableASICscalltheirproductsFPGAsandsomecallthemcomplexPLDs.
FPGAsarethenewestmemberoftheASICfamilyandarerapidlygrowingin
importance,replacingTTLinmicroelectronicsystems.EventhoughanFPGAisa
typeofgatearray,wedonotconsiderthetermgatearraybasedASICstoinclude
FPGAs.ThismaychangeasFPGAsandMGAsstarttolookmorealike.
Figure1.9illustratestheessentialcharacteristicsofanFPGA:
Noneofthemasklayersarecustomized.
Amethodforprogrammingthebasiclogiccellsandtheinterconnect.
Thecoreisaregulararrayofprogrammablebasiclogiccellsthatcanimplement
combinationalaswellassequentiallogic(flipflops).
Amatrixofprogrammableinterconnectsurroundsthebasiclogiccells.
ProgrammableI/Ocellssurroundthecore.
Designturnaroundisafewhours.
WeshallexaminethesefeaturesindetailinChapters48.

FIGURE1.9Afieldprogrammablegatearray
(FPGA)die.AllFPGAscontainaregular
structureofprogrammablebasiclogiccells
surroundedbyprogrammableinterconnect.The
http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

13/14

08/01/2015

1.1TypesofASICs

exacttype,size,andnumberofthe
programmablebasiclogiccellsvaries
tremendously.

[Chapterstart][Previouspage][Nextpage]

http://iroi.seu.edu.cn/books/asics/Book2/CH01/CH01.1.htm#pgfId=1331

14/14