Efficient Implementation of 1024-bit Symmetric

Encryption and Decryption Algorithm for Real

Time Communication Systems
Abubakar Ishfaq

Talha Naqash

M. Amish Hasan

Department of GS&AS
Department of GS&AS
Bahria University
Bahria University
Islamabad, Pakistan
Islamabad, Pakistan
abubakar_2626@yahoo.com talha.naqash@yahoo.com

M.Ali Ashraf Ch
Department of GS&AS
Bahria University
Islamabad, Pakistan
gli_ltd@hotmail.com

Umar Mujahid
Department of Elect. Engg.
Bahria University
Islamabad, Pakistan
umarkhokhar1@hotmail.com

Abstract-Over a decade of era our communication

security demands are increasing exponentially.
Government, semi-government agencies, national and
international companies have their first priority on
sheltering their wireless communication. Thus engineers
have designed more than hundreds of algorithms for
making the secure communication, just like Rijndael
algorithm (AES) which was approved by US National
Institute Standards and Technology (NIST) in 2001. So
security is a never ending battle between the security
algorithm designers and attackers. However AES
cannot meet the requirements for real time
communication. In this paper we have proposed a
symmetric encryption algorithm operating at 1024-bits
of data, through this scheme we can have lower
resource consumption, high speed, low power and cost
effective hardware.
Index- Advanced Encryption Standard (AES), National
Institute Standards and Technology (NIST), Data
Encryption Standard (DES)

I.

INTRODUCTION

The rapid growth of communication technology

has intensely affected human life during the past two
decades. Thousands of applications have been
invented which are directly related to the wired or
wireless communications, such as credit card and
transaction system, so if there is an unsheltered
network, then there may be a massive loss. So
security issue is more important for todays wireless
or wired communication. Sheltering the electronic
communication is an active debate for wireless and
wired networks. Applications such as corporate class

Amir Mukhtar

Member, Research group GS&AS

Member, Research group
Bahria University
GS&AS Bahria University
Islamabad, Pakistan
Islamabad, Pakistan
aamishsn@gmail.com
amir22j@gmail.com

M. Najam-ul-Islam
Department of Elect. Engg.
Bahria University
Islamabad, Pakistan
najam.ul.islam@gmail.com

discussion, online banking (Secret documentations),

aircraft
communication,
Vehicle
tracking,
government agencies information security, military
communication, mobile telephony and audio/video
communication have need for not only the bandwidth
but also security measures [1], [2].
National Institute of Standards and Technology
standardized Rijndael algorithm, which was named as
Advance Encryption Standard (AES) [3]. It was a
replacement of the Data Encryption Standard (DES)
[4], which was widely being used for wireless
communication and the entire internet [5]. In 1975
DES was published and standardized in 1976. This
was having key size of 56-bit, block size of 64-bit,
structure was Balanced Feistel Network and encrypt
data in 16 rounds. This algorithm ruled the
communication world for 22 years, but in 1999 Deep
Crack and distrubted.net break DES key in 22 hours
and 15 minutes. Now there was a need of new
algorithm which should be stronger than DES, so in
2001 new encryption algorithm was standardized by
NIST. This was first time published by Vincet
Rijmen and Joan Daemen in 1998. The National
Institute of Standards and Technology (NIST) have
published full detail of the algorithm under the name
of FIPS-197 [6].
AES consists of 128, 192, 256 bit key. If one
second is required to decrypt the DES key, then it
would take 149 trillion years to decrypt AES key.
Now, AES has become one of the most well-known
standard among symmetric key encryption algorithm

and been used worldwide. Compaaring pervious

encrypting and decrypting algoriithm through
software, the realization of the A
AES algorithm
guarantees a higher physical security leevel. When we
are discussing about the secure commuunication, then
parallel to it, throughput is also discuussed [7]. AES
algorithm is a cipher block algorithm
m, it deals with
data block of 128/192/256 bits. First the incoming
data will be bitwise XORed with the initial key and
then four transformations are exeecuted in the
following order: Sub Bytes, Shifting Rows, Mixing
Columns and Adding Round Key. Thhese four steps
are iterated for 10/12/14 times and att the receiving
end same procedure is reversed, as show
wn in figure 1.

Figure 1. AES-128 bit algorithm

m

Through this scheme, we secure our data but

despite of this our memory conssumption and
throughput efficiencies have been deccreased, which
have made this algorithm restricted for some
applications. Such as, we cannot appply the AES
algorithm for military real time coommunication,
mobile telephony, vehicle trackinng and live
conversations. There are many lighttweight, lower
memory consumption and highh throughput
algorithms parallel to AES. But these all are
separately operated. So here we have a need of such
an algorithm which would be havving all four
parameters in it, so that all the ccommunication
applications can be executed efficientlyy.
II.

RELETATED WO
ORK

There are frequent algorithm designns in the course

of which, we can have high speed, low
w memory, low
power, cost effective parameters. These all
innovative designs can be found in thee literature. All
these algorithms were made for thee unique AES
scheme. Such as the authors propoosed different
techniques in [8]-[12]. In these pappers they used
different techniques to amplify the throoughput but on
the other side they have to enhance the hardware,

which is a costly solution, on the

t other side if we
reduce the hardware, there is deccline of throughput,
which is a immense hurdle among real time
communication applications, such
s
as the work
proposed in [13]-[14]. Before choosing
c
the Vincet
Rijmen and Joan Daemen encryption algorithm, there
were various correlated hardwaare implementations,
that were proposed in [15]-[19], they make available
a variety of structural design options
o
for Advance
Encryption Standard (AES) fin
nalist. Earlier than
agreeing upon any algorithm; security, area and
ority.
speed optimization were first prio
Implementation through Fiield Programmable
Devices (FPD) was presented for Rijndael in [20], a
comparison with Xilinx FPGA implementation. In
this paper the author claims of high
h
throughput over
other FPGA implementations. S-Box scheme was
proposed in [21] for an efficientt compact hardware.
In [16] another compact AES sch
heme was proposed,
through this design we have smalll embedded systems
with low memory constraints.
Efficient throughput/memory tradeoff design was
wise in [11]-[12] 128,
proposed in [10] for AES. Likew
192, and 256-bit key size ASIC
C implementation of
AES were proposed to achieve high
h
throughput. As
all these schemes are not more thaan 256-bits.
III.

STATEMENT OF THE PROBLEM

With the advancement of communication

techniques, more applications arre beginning to use
Advanced Encryption Standard (A
AES) to protect their
information but due to numerous iterations, it doesnt
support real time communicatio
on such as wireless
military communication and mobile
m
telephony as
they need high throughput and lesss hardware.
1. In the cryptographic systems (like
(
Chip Operation
System (COS) or next card
ds) potential of the
algorithm dont realize on the
t exposure of the
credential of the algorithm
m. Security of the
algorithm does not rely on thee size of the data but
it relies on the size of the key..
2. In the real time communicatiion system (wireless
military communication and
d mobile telephony)
need secure and fast commun
nication. A classical
encryption algorithm like AE
ES doesnt meet the
requirements of the real tim
me communications,
due to its numerous iterations..

3. If we increase the throughput, then there should

be a highly resourceful hardware, which is a
costly solution. In small communication systems
like Proximity Cards computational power is low
so we need an algorithm which meets the security
of encryption standards, utilizes low power and
provides us a trust based communication. Here
we need such a data encryption algorithm which
should be efficient in speed, area, power and cost.
IV.

PROPOSED SOLUTION

To conquer the matter of low efficiency over the

customary CPU-based implementation of AES, we
have proposed a new algorithm which would be
supported by small devices such as military Walkytalky, mobile telephony, smart cards, pager, online
documentation
and
aircraft
communication.
According to our proposal, we have designed an
encryption and decryption algorithm. With respect to
our proposed algorithm; it will make available better
efficiency towards throughput, hardware, power and
cost. Here in this paper we have proposed 1024-bit
symmetric encryption and decryption algorithm for
the real time communication applications. According
to this algorithm our data is constructed into block
cipher of 1024-bit each. Odd and even bits are
selected and arranged in a matrix of 32x32. After the
formation of matrix, key will be generated and bit
wise XORed with the previous data matrix.

bit is separated from the string pattern, this will make

two different strings naming as even string pattern
and odd string pattern. These two patterns are
classified in a matrix of 32x32 as shown in figure 2.
We will start placing even pattern in matrix; starting
from , up to
and remaining 512-odd bits
,
pattern will be placed after even bits, starting form
, up to
, . This scrambling of bits raises the
reliance of bit for each other. We have done this to
avoid numerous repetitive iterations which have been
done in AES, such as sub bytes formation, shift rows,
mix column and then XOR the shuffle data with
round key, these steps are repeated 10 times. When
we know the algorithm then why making our
processor so busy? As the security of data depend
upon the length of key.
In EA-1024 we have shuffled the bits on simple
basis so that our processor should be relaxed. If we
give an overlook to AES, we will see that 128-bit
data is processed up to almost 10240 bits (1280bytes) and in the end 128-bit data is constructed as
shown in figure 1.
B. KEY GENERATION
1024-bit key will be generated from the plain text.
Key generation mechanism also scrambler the bits
and arrange in matrix shape of 32x32 as shown figure
3. Padding of bits is used to shorten the key size. For
making our data more secure we will use no padding.

A. EA-1024 ARCHITECTURE
1024-bit architecture for encryption and
decryption is shown in figure 4. The plain text and
the key are 1024-bit. The resulting cipher text will be
also 1024-bits. More details about each
transformation used in the Encryption Algorithm
(EA-1024) are described in the coming sections;
where as the key generation will be explained later.

Figure 2. EA-1024

Block size of 1024-bit will be constructed from

the given plain text; these bits will be arranged in a
string pattern for making further transformations.
1024-bit is selected so to make encryption highly
complicated without knowing key. An even and odd

Figure 3. Key for EA-1024

The final operation wills bitwise XOR of data

with the key to have encrypted message as shown in
figure 4 (a). The receiver reverses the process of
encryption to extract original data, shown in figure 4
(b). The key is known through safer channel.

2.4 GHz and 2 GB RAM. Through this algorithm the

efficiency of 87.5% was increased towards
throughput and 50% memory consumption as
compared to AES-128, as shown in figure 5. On the
other hand the hardware cost and power consumption
is reduced up to 90% as compared to the AES-128.
Data can be made more secure against brute-force
attack by using full key size. The EA-1024 algorithm
is ultimate for real time communication and mobile
telephony with higher throughput, low power, low
memory resource and cheap hardware. This
algorithm provides the significant results for
throughput, area, power and cost.

(a)

(a)

(b)

(b)
Figure 4. Block Diagram of EA-1024

V.

Results and Evaluation

The proposed EA-1024 bit and the original AES128 algorithm were coded in MATLAB. As a source
we used Hewelt Packard core i3 machine, processor

Figure 5. (a) EA-1024 simulation encryption & decryption (b)

AES-128 simulation encryption & decryption

VI.

CONCLUSION

Nowadays AES has being widely used in many

applications. In this paper we have proposed EA-

1024 algorithm with 1024-bit input block and 1024bit key size. We used different scheme for shuffling
bits, which advance the efficiency in the direction of
security, throughput, area, power and cost up to 90%.
This algorithm support applications in which high
level security, high throughput, low power and low
memory are required such as in military
communication, mobile telephony and multimedia
communications.
VII.

FUTURE WORK

We can increase efficiency of EA-1024 by using

Vertix 7 FPGA. This algorithm prevents snooper,
hackers from viewing your communication
information such as instant messages, downloads,
credit card information or anything else you send
over the network.
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