2009 International Conference on Measuring Technology and Mechatronics Automation

FPGA Implementation of a Best-precision Fixed-point Digital PID Controller

Yankai XU

Kai SHUANG Shan JIANG Xiaoliang WU

Faculty of Mechanical and Electronic Engineering

China University of Petroleum(Beijing)
Beijing China,
E-mail: xuyk163@163.com

Faculty of Mechanical and Electronic Engineering

China University of Petroleum(Beijing)
Beijing China,
E-mail: shuangkai815@163.com

Abstract Proportional-Integral-Derivative (PID) controllers

have been broadly used in many areas. Compared with analog
controllers, digital ones by Digital Signal Processor (DSP) or
Field Programmable Gate Arrays (FPGA) are more stable
and easier to adjust parameter. Digital controllers are usually
implemented with FPGA for its fast and stable performance.
When it is implemented with FPGA, floating-point arithmetic
is usually converted to fixed-point arithmetic. However the
process of a floating-fixed conversion is complex, the period is
long and the precision is proved to be low. Since the above
problems, this paper proposes both best-precision fixed point
arithmetic and the FPGA implementation details of a digital
PID controller. And it illustrates the process of converting
analog controllers to digital one. The simulation results show
that the best-precision fixed point digital PID Controller is
simple, and it outperforms by high-speed response, better
precision, minor error and high dynamic range.

II. MODELING OF DIGITAL PID CONTROLLERS

The proportional-integral-Derivative (PID) law has been
widely used in industrial field. The control actions are
shown in Fig.1.

Keywords- Best-precision Fixed-point; digital PID controller

; FPGA

Figure1.

Proportional Control means that u(t) is changed in direct

proportion to the error e(t). Where, K p is proportional gain.

I. INTRODUCTION
Due to its simple arithmetic and robust properties, analog
PID controllers are applied in many areas. But nowadays it
can not keep pace with faster, cheaper, more stable and
more flexible requirements dictated by modern
applications. In recent years, digital controllers
implemented with DSP or FPGA have been conceived and
designed to improve performance. Implemented with these
fixed point devices, floating point arithmetic is usually
converted to fixed point format. However fixed point
format can not offer high precision and wide dynamic
range. At the same time, the process of a float-fixed
conversion is complex and the period is long.
In order to improve accuracy and minimize error, and to
reduce speed and complexity of conversion of floating
point format to fixed point, best-precision fixed point
arithmetic is conceived and applied to implementation of
PID controllers by FPGA circuitry because it excels one
with DSP in speed and stability.
This paper describes the process of converting analog
controllers to digital ones, presents both best-precision
fixed point arithmetic and the FPGA implementation details
of a digital PID controller.

978-0-7695-3583-8/09 $25.00 2009 IEEE

DOI 10.1109/ICMTMA.2009.517

Topology of a PID Controller

Integral part controls the output by integrating the error

signal. K i = 1 Ti is called the integral gain which is the
reciprocal of the integral time. Derivative output is the
derivative of the error signal. K d is derivative gain. So the
control law of a PID controller can be written as Eq. (1),

u = K p e + K i e dt +K d

de
dt

To get the discrete model of a PID controller, we built an

analog PID controller. The schematic was shown in Fig.2.

Figure2.

384

Schematic of the analog controller

wave signal with 50% duty time. The sampling

time Ts takes 1s . The response of the discrete model with
Simulink is shown in Fig.4.

The response of the controller will be the sum of the

response of input vi and the response of input vd [1], that is,
V o (s )

Z2
Z
V i (s ) + 1 + 2 V d (s )
Z1
Z1

Input signal
6

C
1
1
= 2 + 1 +
+ R 2 C 1 s V i (s )
R1 C 2 C 2 R1 s

2.5

3.5

4.5

5
0

-10

0.5

1.5

2.5

3.5

4.5

5
-3

x 10

Figure4.

Simulation of the discrete PI controller

Using the model in Eq. (5) and the given controller

parameters as above, we get the formula as follows.

y ( n) = 0.01333[ vi (n ) - 2.5] + y ( n - 1)

vo (n ) = 8.0625 - 0.075vi (n ) y (n)

R
C
1
vo (n ) = 2 + 1 vi (n )
[vo 2 (n 1) + Ts vi (n )]
R
C
C2 R1
1
2

III.

v (k ) .

FPGA IMPLEMENTION

(a)input signal

k =0

5
0

Moreover, in our design the derivative item in Eq.(4) is

smaller , which can be neglected. Omit the action of the
derivative item, we get a PI controller as follows [3]

R C
1
[vo2(n 1) +Ts vi (n)]
vo(n) = 2 + 1 vi (n)
C2R1
R1 C2
R C
nTv
+1+ 2 + 1 vd C + s d
C2R1
R1 C2

(6)

Due to only Integer and logic data can be operated in

FPGA, the controller formulated in Eq.(6) is implemented
after its fractional coefficients being converted to fixedpoint ones[4,5]. So we take the 22-bit word length with 15
fractional bits fixed-point system simulation with Matlab
and the simulation is shown in Fig.5.

R
C
nT v
R2C1 [vi (n ) vi (n 1)] + 1 + 2 + 1 vd C + s d
R1 C 2
C2 R1

0.5

1.5

2.5

3.5

4.5

5
-3

x 10
(b)output of the floating-point controller
10
0
-10

0.5

1.5

2.5

3.5

4.5

5
-3

x 10
(c)output of the 22-bit word length with 15 fractional bits fixed-point controller
10
0
-10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5

-3

x 10
(d)absolute error of the 22-bit word length with 15 fractional bits fixed-point controller
0
-0.05
-0.1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5

The discrete model is shown in Fig.3.

Take a group of parameters of the analog controller
shown in Fig.1, let

-3

x 10

Figure5.

C1 = 100 pF R1 = 7.5K C2 = 0.01F R2 = 480

-KR2/R1+C1/C2
-KSaturation

Simulation of the fixed-point controller

Compared with output of the floating point controller,

the absolute error is divergent and the fixed point controller
can not achieve normal performance because fixed point
format can not offer enough high precision. To solve the
problem, best-precision fixed-point arithmetic is conceived.
At the same time a best-precision fixed-point controller and
modules are implemented in the paper.

R3 = 7.5K V d = 2.5V Vi is a 5V 1KHz square

Scope

1/C2/R1
Add 3

Add 2

z
Delay 3

7.5

A. Best-precision fixed point algorithm

Best-precision fixed point is a format which can be used
in FPGA. Just as fixed-point, a best-precision fixed point
data consists with two parts: integer mantissa and exponent.
In our design, integer mantissa uses signed twoscomplement notation, and exponent uses true code. There
are some differences between best-precision fixed point
number and fixed point one. Exponent of the former is

-K-

Vd +C 1+R2/R1+C1/C2

-KRamp

Figure3.

-5

Replace the continuous function with discrete one [2],

we get,

Ts

1.5

-3

t
R
C
1
v o = 2 + 1 v i
vi d C
C2
C 2 R 1 0
R1
dv i
R
C
t
vd
R 2C1
+ 1 + 2 + 1 v d +
dt
R
C
C
1
2
2 R1

Pulse
Generator

x 10

Make inverse Laplace transform to Eq. (2), we get

time domain expression as below,

-K-

0.5

Output of the regulator

R
C
1
1
+ 1 + 2 + 1 +
+ R 2 C 1 s V d (s )
R 1 C 2 C 2 R1 s

Where, Ts is sampling interval, and v o 2 (n) =

10

1/C2/R1*Vd *Ts

Discrete model of the PID controller

385

variable while the latter is fixed; Integer mantissa range of

the former is f(2N-1)through f(2N-1) and zero, while the
latters is -(2N-1) through 2N-1. In other word, the former
contains no redundant sign bits which mean that all bits are
significant while the latter may contains redundant bits. The
attributes of a best-precision fixed point data can be
represented as being sN,M where the s indicates that the
quantity is signed, the N indicates that there are N-bit
integer mantissa, and the unsigned M indicates that there
are M-bit exponent.
A floating-point number can be converted to bestprecision fixed point format by determining radix point and
normalize integer mantissa and exponent. The expression
that a floating-point number Vfl is converted to integer
mantissa Vfp of a best-precision fixed point number can be
written as [6],
Vfp = [Vfl 2 NV]
7
Where, NV is Vfps exponent which is variable. [ ] denotes
integer mantissa Vfp is converted by truncation or rounding.

simulation of the redundant sign bits counter is shown in

Fig.6.

Figure6.

Simulation of the redundant sign bits counter

Data in Fig.6 are explicated as follows:

Integer mantissa is 111110000111111 and exponent is 2, so
the number of redundant sign bits is 4. After normalization,
integer mantissa is 1000011111110000 and exponent is 6.
The simulation of the addition is shown in Fig.7:

B. Basic modules
Adder and multiplier are basic modules in the digital PID
controller. In the design, attributes of operands are s16.5
best-precision fixed point format. The project is
programmed with VHDL, compiled and simulated with
Quartus 7.0, then implemented on a cyclone
EP1C6Q240C8 FPGA chip.
1) Adder: The addition of best-precision fixed -point
operands requires that the binary points of the addends
should be aligned[7]. The addition is then performed using
binary arithmetic. If the exponents are not equal, the binary
point of the smaller exponent should be shifted up by the
difference between the two exponents in order to offer high
precision. The relation of the operands and results can be
written as:
Nx<Ny
Z = [X 2 Ny-Nx + Y]2-Nz
8
Nz=Nx+L
9
Where, Nx Ny Nz are the exponents of X Y Z
separatelyL is the length of redundant sign bits of [X 2
Ny-Nx
+ Y].
Adding two operands in best-precision fixed-point
format can be implemented as follows: Firstly, compute the
difference between the two exponents and set it as zero if
any of two operands is zero. Secondly, send them to
corresponding registers according to the sign of the
difference (the operand whose exponent is smaller will be
sent to register A, another will be sent to register B).
Thirdly, the operand in register B is shifted to the left by
the difference. Fourthly, add the two operands and check
redundant sign bits number of the result and normalize it.
Finally, compute exponent according to Eq.(9). Redundant
sign bits counter designed by dichotomy uses 97 logic
elements with a latency of less than 4 clock cycles. The

Figure7.

Simulation of the adder

Data in Fig.7 are explicated as follows:

-17475/28+28564/219=-17461/28
2) Multiplier: The multiplication of two bestprecision fixed point numbers is simpler than addition
because its not necessary to align the binary points. The
result of the algorithm is directly obtained by multiplying
the integer mantissa with the exception that it should be
normalized. The expression can be shown as:
Z = [X 2Nx ][Y 2Ny ]2Nz
10
Nz=Nx+Ny+N- L
11
Where, XYZ are floating point operands. N is integer
mantissa length and L is the length of redundant sign bits of
[X 2Nx][Y 2Ny].
Multiplication of two numbers in best-precision fixed
point format can be implemented as follows: Firstly,
multiply the integer mantissas with the radix-2 booth
arithmetic and produce a middle result. Compared with
direct multiplication, booth arithmetic can effectively
reduce resource utilization. Secondly, count redundant sign
bits of the middle result and normalize it. Because two
operands are normalized, redundant sign bits are no more
than 3. Finally, compute exponent according to Eq.(11).
The simulation of best-precision fixed point multiplier is
shown in Fig.8:

Figure8.

Simulation of the multiplier

Data in Fig.8 are explicated as follows:

386

(27955/28 )(17825/210)=30413/24

(a)output of the best-prec is ion fixed-point controller

10
5

C. Implementation of digital PID controller

According to the module in Fig.3, the best-precision
fixed point digital PID controller is implemented.
Hierarchy of the controller is shown in Fig.9. It mainly
includes following modules: twocomplement, adder,
multiplication and delayer. The controller requires 1377
logic elements with a latency of 30 clock cycles. Among
the LEs every adder module takes 240 LEs and multiplier
module takes 149 LEs.

0
-5
-10

0.5

1.5

2.5

3.5

4.5

5
-3

x 10

0.01
0
-0.01
-0.02

0.5

1.5

2.5

3.5

4.5

5
-3

x 10

Figure11. Output and error of the best-precision fixed point controller

So we can conclude that the proposed controller provides

minor error, higher dynamic range and avoids
disadvantages of long and complex process.
IV.

Figure9.

(b)absolute error of the best-precision fixed-point controller

0.02

CONCLUSION

In this paper, the whole process is presented, as well as

FPGA implementation details for best-precision fixed
point digital PID controller. Along with its simple
application, high reliability and fast response speed, the
controller is able to achieve wide dynamic range, higher
precision. At the same time, best-precision fixed point
arithmetic can be applied in FPGA implementation of
other digital systems.

Hierarchy of the controller

In the wave-simulation of the PID controller, following

parameters are taken: clock frequency is 50MHz, sampling
time is 1ussimulation time is 5mssimulation part result
is shown in Fig.9. Where, a/2qa=1, b/2qb =0.01333, c/2qc
=8.0625, d/2qd =0.075, x(n)/2qx is sampling value of input
vi s(n)/2qr is the controllers digital output vo (n) .
Compared with golden reference (floating point format
output data in Fig.5(b)), data in Fig.10 have little
difference.

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Figure10. Wave-simulation of the best-precision fixed point controller

In order to illustrating a more clear compare against gold

reference, We figure the data of wave-simulation with
Matlab, and output and error of the best-precision fixed
point controller are shown in Fig.11. We can see that the
output response of the controller has little difference and its
absolute error is periodic and less than 0.0180.

387